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RE: [LinuxBIOS] LNXI Merge: lnxi-patch02/16
by Lu, Yinghai 06 Sep '05

06 Sep '05

Why usb2? Amd8111 usb2 already be disabled, and can not be used .... YH -----Original Message----- From: linuxbios-bounces(a)openbios.org [mailto:linuxbios-bounces@openbios.org] On Behalf Of jason schildt Sent: Friday, September 02, 2005 3:03 PM To: linuxbios(a)openbios.org Subject: [LinuxBIOS] LNXI Merge: lnxi-patch02/16 DESCRIPTION: --------------------------------------------------------- ## lnxi-patch-2 ## - (3)files src/southbridge/amd/amd8111/amd8111_lpc.c powermanagment removed. copied to public tree src/southbridge/amd/amd8111/Config.lb src/southbridge/amd/amd8111/amd8111_usb.c uncommented amd8111_enable DIFFSTAT: --------------------------------------------------------- Config.lb | 9 ++++----- amd8111_lpc.c | 12 ++++-------- amd8111_usb.c | 2 +- 3 files changed, 9 insertions(+), 14 deletions(-) PATCH: --------------------------------------------------------- Index: amd8111_lpc.c =================================================================== --- amd8111_lpc.c (revision 1105) +++ amd8111_lpc.c (working copy) @@ -84,7 +84,7 @@ return; } printk_spew("for IRQ, reg 0x%08x value 0x%08x 0x%08x\n", - a->reg, a->value_low, a->value_high); + a->reg, a->value_low, a->value_high); } } @@ -113,13 +113,9 @@ byte = pci_read_config8(dev, 0x46); pci_write_config8(dev, 0x46, byte | (1<<0)); - /* power after power fail */ + /* Enable 5Mib Rom window */ byte = pci_read_config8(dev, 0x43); - if (pwr_on) { - byte &= ~(1<<6); - } else { - byte |= (1<<6); - } + byte |= 0xC0; pci_write_config8(dev, 0x43, byte); /* Enable Port 92 fast reset */ @@ -179,7 +175,7 @@ static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) { pci_write_config32(dev, 0x70, - ((device & 0xffff) << 16) | (vendor & 0xffff)); + ((device & 0xffff) << 16) | (vendor & 0xffff)); } static struct pci_operations lops_pci = { Index: Config.lb =================================================================== --- Config.lb (revision 1105) +++ Config.lb (working copy) @@ -1,12 +1,11 @@ config chip.h driver amd8111.o -#driver amd8111_usb.o +driver amd8111_usb.o driver amd8111_lpc.o driver amd8111_ide.o driver amd8111_acpi.o -#driver amd8111_usb2.o -#driver amd8111_ac97.o -#driver amd8111_nic.o +driver amd8111_usb2.o +driver amd8111_ac97.o +driver amd8111_nic.o driver amd8111_pci.o driver amd8111_smbus.o -object amd8111_reset.o Index: amd8111_usb.c =================================================================== --- amd8111_usb.c (revision 1105) +++ amd8111_usb.c (working copy) @@ -26,7 +26,7 @@ .enable_resources = pci_dev_enable_resources, .init = 0, .scan_bus = scan_static_bus, -// .enable = amd8111_enable, + .enable = amd8111_enable, .ops_pci = &lops_pci, }; -- Using Opera's revolutionary e-mail client: http://www.opera.com/mail/ -- LinuxBIOS mailing list LinuxBIOS(a)openbios.org http://www.openbios.org/mailman/listinfo/linuxbios

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RE: [LinuxBIOS] LNXI Merge: lnxi-patch-11/16
by Lu, Yinghai 06 Sep '05

06 Sep '05

Before cache as ram working, I used fixed size to replace unsigned to make sure romcc can compile my in_coherent.c Do you have own internal version ROMCC that make use unsigned well....? YH -----Original Message----- From: linuxbios-bounces(a)openbios.org [mailto:linuxbios-bounces@openbios.org] On Behalf Of jason schildt Sent: Friday, September 02, 2005 3:03 PM To: linuxbios(a)openbios.org Subject: [LinuxBIOS] LNXI Merge: lnxi-patch-11/16 DESCRIPTION: ------------------------------------------------ ## lnxi-patch-11 ## src/northbridge/amd/amdk8/incoherent_ht.c Removed K8_HT_FREQ_1G test as we can now compile this with romcc. Bug fix added to ht_optimize_link() To ignore status bits when we read the link freq. Comment added that suggests s/uint8_t/unsigned/g that could save code generated by romcc. DIFFSTAT: ------------------------------------------------ incoherent_ht.c | 22 ++++++++++++---------- 1 files changed, 12 insertions(+), 10 deletions(-) PATCH: ------------------------------------------------ Index: northbridge/amd/amdk8/incoherent_ht.c =================================================================== --- northbridge/amd/amdk8/incoherent_ht.c (revision 1105) +++ northbridge/amd/amdk8/incoherent_ht.c (working copy) @@ -1,15 +1,16 @@ /* This should be done by Eric 2004.12 yhlu add multi ht chain dynamically support + */ #include <device/pci_def.h> #include <device/pci_ids.h> #include <device/hypertransport_def.h> -#ifndef K8_HT_FREQ_1G_SUPPORT - #define K8_HT_FREQ_1G_SUPPORT 0 -#endif - +/* We can reduce the size of code generated by romcc by + * changing all of the fixed size types that live in registers + * into simple unsigned variables. (ie s/uint8_t/unsigned/g) + */ #ifndef K8_SCAN_PCI_BUS #define K8_SCAN_PCI_BUS 0 #endif @@ -130,21 +131,20 @@ /* AMD 8131 Errata 48 */ if (id == (PCI_VENDOR_ID_AMD | (PCI_DEVICE_ID_AMD_8131_PCIX << 16))) { freq_cap &= ~(1 << HT_FREQ_800Mhz); - return freq_cap; } /* AMD 8151 Errata 23 */ if (id == (PCI_VENDOR_ID_AMD | (PCI_DEVICE_ID_AMD_8151_SYSCTRL << 16))) { freq_cap &= ~(1 << HT_FREQ_800Mhz); - return freq_cap; } /* AMD K8 Unsupported 1Ghz? */ if (id == (PCI_VENDOR_ID_AMD | (0x1100 << 16))) { - #if K8_HT_FREQ_1G_SUPPORT == 1 - if (is_cpu_pre_e0()) // CK804 support 1G? - #endif - freq_cap &= ~(1 << HT_FREQ_1000Mhz); + /* Supported starting with E0 */ + device_t dev_2 = PCI_DEV(0,0x18,2); + if(pci_read_config32(dev_2,0x9c) < 0x20f00) { + freq_cap &= ~(1 << HT_FREQ_1000Mhz); + } } return freq_cap; @@ -199,8 +199,10 @@ /* See if I am changing the link freqency */ old_freq = pci_read_config8(dev1, pos1 + LINK_FREQ(offs1)); + old_freq &= 0x0f; needs_reset |= old_freq != freq; old_freq = pci_read_config8(dev2, pos2 + LINK_FREQ(offs2)); + old_freq &= 0x0f; needs_reset |= old_freq != freq; /* Set the Calulcated link frequency */ -- Jason W. Schildt LinuxBIOS Software Engineer Linux Networx -- LinuxBIOS mailing list LinuxBIOS(a)openbios.org http://www.openbios.org/mailman/listinfo/linuxbios

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[LinuxBIOS] LNXI Merge: lnxi-patch-08/16
by jason schildt 06 Sep '05

06 Sep '05

DESCRIPTION: ---------------------------------------------------- ## lnxi-patch-8 ## src/mainboard/arima/hdama/mptable.c Add smp_write_processors_inorder() to workaround 2.6.11 bug. dynamically compute ioapic_id vs. hardcode. Add SATA support. Added reboot_if_hotswap() to catch bad board strapping hardware bug. DIFFSTAT: ---------------------------------------------------- mptable.c | 213 ++++++++++++++++++++++++++++++++++++++++++++++++-------------- 1 files changed, 167 insertions(+), 46 deletions(-) PATCH: ---------------------------------------------------- Index: mainboard/arima/hdama/mptable.c =================================================================== --- mainboard/arima/hdama/mptable.c (revision 1105) +++ mainboard/arima/hdama/mptable.c (working copy) @@ -3,7 +3,61 @@ #include <device/pci.h> #include <string.h> #include <stdint.h> +#include <cpu/x86/lapic.h> +#include <arch/cpu.h> +#include <arch/io.h> +#define HT_INIT_CONTROL 0x6c +#define HTIC_BIOSR_Detect (1<<5) + +/* If we assume a symmetric processor configuration we can + * get all of the information we need to write the processor + * entry from the bootstrap processor. + * Plus I don't think linux really even cares. + * Having the proper apicid's in the table so the non-bootstrap + * processors can be woken up should be enough. + */ +void smp_write_processors_inorder(struct mp_config_table *mc) +{ + int boot_apic_id; + int order_id; + unsigned apic_version; + unsigned cpu_features; + unsigned cpu_feature_flags; + struct cpuid_result result; + device_t cpu; + + boot_apic_id = lapicid(); + apic_version = lapic_read(LAPIC_LVR) & 0xff; + result = cpuid(1); + cpu_features = result.eax; + cpu_feature_flags = result.edx; + /* order the output of the cpus to fix a bug in kernel 6 11 */ + for(order_id = 0;order_id <256; order_id++) { + for(cpu = all_devices; cpu; cpu = cpu->next) { + unsigned long cpu_flag; + if ((cpu->path.type != DEVICE_PATH_APIC) || + (cpu->bus->dev->path.type != DEVICE_PATH_APIC_CLUSTER)) + { + continue; + } + if (!cpu->enabled) { + continue; + } + cpu_flag = MPC_CPU_ENABLED; + if (boot_apic_id == cpu->path.u.apic.apic_id) { + cpu_flag = MPC_CPU_ENABLED | MPC_CPU_BOOTPROCESSOR; + } + if(cpu->path.u.apic.apic_id == order_id) { + smp_write_processor(mc, + cpu->path.u.apic.apic_id, apic_version, + cpu_flag, cpu_features, cpu_feature_flags); + break; + } + } + } +} + static unsigned node_link_to_bus(unsigned node, unsigned link) { device_t dev; @@ -38,6 +92,21 @@ return 0; } +unsigned max_apicid(void) +{ + unsigned max_apicid; + device_t dev; + max_apicid = 0; + for(dev = all_devices; dev; dev = dev->next) { + if (dev->path.type != DEVICE_PATH_APIC) + continue; + if (dev->path.u.apic.apic_id > max_apicid) { + max_apicid = dev->path.u.apic.apic_id; + } + } + return max_apicid; +} + void *smp_write_config_table(void *v) { static const char sig[4] = "PCMP"; @@ -50,6 +119,10 @@ unsigned char bus_8131_1; unsigned char bus_8131_2; unsigned char bus_8111_1; + unsigned apicid_base; + unsigned apicid_8111; + unsigned apicid_8131_1; + unsigned apicid_8131_2; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); memset(mc, 0, sizeof(*mc)); @@ -68,8 +141,12 @@ mc->mpe_checksum = 0; mc->reserved = 0; - smp_write_processors(mc); + smp_write_processors_inorder(mc); + apicid_base = max_apicid() + 1; + apicid_8111 = apicid_base; + apicid_8131_1 = apicid_base + 1; + apicid_8131_2 = apicid_base + 2; { device_t dev; @@ -124,7 +201,7 @@ smp_write_bus(mc, bus_isa, "ISA "); /* IOAPIC handling */ - smp_write_ioapic(mc, 2, 0x11, 0xfec00000); + smp_write_ioapic(mc, apicid_8111, 0x11, 0xfec00000); { device_t dev; struct resource *res; @@ -133,7 +210,7 @@ if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { - smp_write_ioapic(mc, 0x03, 0x11, res->base); + smp_write_ioapic(mc, apicid_8131_1, 0x11, res->base); } } /* 8131 apic 4 */ @@ -141,44 +218,44 @@ if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { - smp_write_ioapic(mc, 0x04, 0x11, res->base); + smp_write_ioapic(mc, apicid_8131_2, 0x11, res->base); } } } /* ISA backward compatibility interrupts */ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_isa, 0x00, 0x02, 0x00); + bus_isa, 0x00, apicid_8111, 0x00); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_isa, 0x01, 0x02, 0x01); + bus_isa, 0x01, apicid_8111, 0x01); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_isa, 0x00, 0x02, 0x02); + bus_isa, 0x00, apicid_8111, 0x02); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_isa, 0x03, 0x02, 0x03); + bus_isa, 0x03, apicid_8111, 0x03); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_isa, 0x04, 0x02, 0x04); + bus_isa, 0x04, apicid_8111, 0x04); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_isa, 0x05, 0x02, 0x05); + bus_isa, 0x05, apicid_8111, 0x05); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_isa, 0x06, 0x02, 0x06); + bus_isa, 0x06, apicid_8111, 0x06); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_isa, 0x07, 0x02, 0x07); + bus_isa, 0x07, apicid_8111, 0x07); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_isa, 0x08, 0x02, 0x08); + bus_isa, 0x08, apicid_8111, 0x08); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_isa, 0x09, 0x02, 0x09); + bus_isa, 0x09, apicid_8111, 0x09); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_isa, 0x0a, 0x02, 0x0a); + bus_isa, 0x0a, apicid_8111, 0x0a); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_isa, 0x0b, 0x02, 0x0b); + bus_isa, 0x0b, apicid_8111, 0x0b); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_isa, 0x0c, 0x02, 0x0c); + bus_isa, 0x0c, apicid_8111, 0x0c); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_isa, 0x0d, 0x02, 0x0d); + bus_isa, 0x0d, apicid_8111, 0x0d); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_isa, 0x0e, 0x02, 0x0e); + bus_isa, 0x0e, apicid_8111, 0x0e); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_isa, 0x0f, 0x02, 0x0f); + bus_isa, 0x0f, apicid_8111, 0x0f); /* Standard local interrupt assignments */ smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, @@ -188,46 +265,48 @@ /* PCI Ints: Type Trigger Polarity Bus ID PCIDEVNUM|IRQ APIC ID PIN# */ /* On board nics */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x03<<2)|0, 0x02, 0x13); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x04<<2)|0, 0x02, 0x13); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x03<<2)|0, apicid_8111, 0x13); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x04<<2)|0, apicid_8111, 0x13); + /* On board SATA */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x05<<2)|0, apicid_8111, 0x11); /* PCI Slot 1 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x01<<2)|0, 0x02, 0x11); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x01<<2)|1, 0x02, 0x12); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x01<<2)|2, 0x02, 0x13); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x01<<2)|3, 0x02, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x01<<2)|0, apicid_8111, 0x11); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x01<<2)|1, apicid_8111, 0x12); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x01<<2)|2, apicid_8111, 0x13); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x01<<2)|3, apicid_8111, 0x10); /* PCI Slot 2 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x02<<2)|0, 0x02, 0x12); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x02<<2)|1, 0x02, 0x13); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x02<<2)|2, 0x02, 0x10); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x02<<2)|3, 0x02, 0x11); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x02<<2)|0, apicid_8111, 0x12); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x02<<2)|1, apicid_8111, 0x13); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x02<<2)|2, apicid_8111, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x02<<2)|3, apicid_8111, 0x11); /* PCI Slot 3 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x01<<2)|0, 0x02, 0x11); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x01<<2)|1, 0x02, 0x12); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x01<<2)|2, 0x02, 0x13); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x01<<2)|3, 0x02, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x01<<2)|0, apicid_8111, 0x11); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x01<<2)|1, apicid_8111, 0x12); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x01<<2)|2, apicid_8111, 0x13); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x01<<2)|3, apicid_8111, 0x10); /* PCI Slot 4 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x02<<2)|0, 0x02, 0x12); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x02<<2)|1, 0x02, 0x13); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x02<<2)|2, 0x02, 0x10); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x02<<2)|3, 0x02, 0x11); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x02<<2)|0, apicid_8111, 0x12); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x02<<2)|1, apicid_8111, 0x13); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x02<<2)|2, apicid_8111, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x02<<2)|3, apicid_8111, 0x11); /* PCI Slot 5 */ #warning "FIXME get the irqs right, it's just hacked to work for now" - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_1, (0x05<<2)|0, 0x02, 0x11); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_1, (0x05<<2)|1, 0x02, 0x12); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_1, (0x05<<2)|2, 0x02, 0x13); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_1, (0x05<<2)|3, 0x02, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_1, (0x05<<2)|0, apicid_8111, 0x11); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_1, (0x05<<2)|1, apicid_8111, 0x12); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_1, (0x05<<2)|2, apicid_8111, 0x13); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_1, (0x05<<2)|3, apicid_8111, 0x10); /* PCI Slot 6 */ #warning "FIXME get the irqs right, it's just hacked to work for now" - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_1, (0x04<<2)|0, 0x02, 0x10); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_1, (0x04<<2)|1, 0x02, 0x11); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_1, (0x04<<2)|2, 0x02, 0x12); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_1, (0x04<<2)|3, 0x02, 0x13); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_1, (0x04<<2)|0, apicid_8111, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_1, (0x04<<2)|1, apicid_8111, 0x11); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_1, (0x04<<2)|2, apicid_8111, 0x12); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_1, (0x04<<2)|3, apicid_8111, 0x13); /* There is no extension information... */ @@ -239,9 +318,51 @@ return smp_next_mpe_entry(mc); } +void reboot_if_hotswap(void) +{ + /* Hack patch work around for hot swap enable 33mhz problem */ + device_t dev; + uint32_t data; + unsigned long htic; + int reset; + int i; + + reset = 0; + printk_debug("Looking for bad PCIX MHz input\n"); + dev = dev_find_slot(1, PCI_DEVFN(0x02,0)); + data = pci_read_config32(dev, 0xa0); + if(!(((data>>16)&0x03)==0x03)) { + reset=1; + printk_debug("Bad PCIX MHz - Reset\n"); + } + printk_debug("Looking for bad Hot Swap Enable\n"); + dev = dev_find_slot(1, PCI_DEVFN(0x01,0)); + data = pci_read_config32(dev, 0x48); + if(data & 0x0c) { + reset=1; + printk_debug("Bad Hot Swap start - Reset\n"); + } + if(reset) { + /* enable cf9 */ + dev = dev_find_slot(node_link_to_bus(0, 0), PCI_DEVFN(0x04,3)); + pci_write_config8(dev, 0x41, 0xf1); + /* reset */ + dev = dev_find_slot(0, PCI_DEVFN(0x18,0)); + htic = pci_read_config32(dev, HT_INIT_CONTROL); + htic &= ~HTIC_BIOSR_Detect; + pci_write_config32(dev, HT_INIT_CONTROL, htic); + outb(0x0e, 0x0cf9); + } + else { + printk_debug("OK 133MHz & Hot Swap is off\n"); + } +} + unsigned long write_smp_table(unsigned long addr) { void *v; + reboot_if_hotswap(); + v = smp_write_floating_table(addr); return (unsigned long)smp_write_config_table(v); } -- Jason W. Schildt LinuxBIOS Software Engineer Linux Networx

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RE: [LinuxBIOS] LNXI Merge: lnxi-patch-01/16
by Lu, Yinghai 06 Sep '05

06 Sep '05

Actually amd8111_enable is not needed, it will be called from enable_dev ....at first. YH -----Original Message----- From: linuxbios-bounces(a)openbios.org [mailto:linuxbios-bounces@openbios.org] On Behalf Of jason schildt Sent: Friday, September 02, 2005 3:04 PM To: linuxbios(a)openbios.org Subject: [LinuxBIOS] LNXI Merge: lnxi-patch-01/16 ## lnxi-patch-1 ## - (2)files src/southbridge/amd/amd8111/amd8111_acpi.c // amd8111_enable is commented out in public tree, but enabled in // hdama. resolution: copied over for merge DIFFSTAT --------------------------------------------------------- amd8111_acpi.c | 5 +++-- amd8111_pci.c | 1 + 2 files changed, 4 insertions(+), 2 deletions(-) PATCH --------------------------------------------------------- Index: southbridge/amd/amd8111/amd8111_pci.c =================================================================== --- southbridge/amd/amd8111/amd8111_pci.c (revision 1105) +++ southbridge/amd/amd8111/amd8111_pci.c (working copy) @@ -55,6 +55,7 @@ .enable_resources = pci_bus_enable_resources, .init = pci_init, .scan_bus = pci_scan_bridge, + /* PCI Subordinate bus reset is not implemented */ .ops_pci = &lops_pci, }; Index: southbridge/amd/amd8111/amd8111_acpi.c =================================================================== --- southbridge/amd/amd8111/amd8111_acpi.c (revision 1105) +++ southbridge/amd/amd8111/amd8111_acpi.c (working copy) @@ -97,6 +97,7 @@ #endif + /* power after power fail */ on = MAINBOARD_POWER_ON_AFTER_POWER_FAIL; get_option(&on, "power_on_after_fail"); byte = pci_read_config8(dev, PREVIOUS_POWER_STATE); @@ -106,7 +107,7 @@ } pci_write_config8(dev, PREVIOUS_POWER_STATE, byte); printk_info("set power %s after power fail\n", on?"on":"off"); - + /* Throttle the CPU speed down for testing */ on = SLOW_CPU_OFF; get_option(&on, "slow_cpu"); @@ -177,7 +178,7 @@ .enable_resources = acpi_enable_resources, .init = acpi_init, .scan_bus = scan_static_bus, -// .enable = amd8111_enable, + .enable = amd8111_enable, .ops_pci = &lops_pci, .ops_smbus_bus = &lops_smbus_bus, }; Using Opera's revolutionary e-mail client: http://www.opera.com/mail/ -- LinuxBIOS mailing list LinuxBIOS(a)openbios.org http://www.openbios.org/mailman/listinfo/linuxbios

2 1

RE: [LinuxBIOS] LNXI Merge: lnxi-patch-15/16
by Lu, Yinghai 06 Sep '05

06 Sep '05

Any reason for you disabling Cache as RAM for Tyan MB? YH -----Original Message----- From: linuxbios-bounces(a)openbios.org [mailto:linuxbios-bounces@openbios.org] On Behalf Of jason schildt Sent: Friday, September 02, 2005 3:04 PM To: linuxbios(a)openbios.org Subject: [LinuxBIOS] LNXI Merge: lnxi-patch-15/16 DESCRIPTION: ------------------------------------------------ ## lnxi-patch-15 ## src/mainboard/.../Options.lb Disabled cache_as_ram: USE_CACHE_RAM CONFIG_USE_INIT tyan/s2881/Options.lb tyan/s2882/Options.lb tyan/s2891/Options.lb tyan/s4880/Options.lb tyan/s2892/Options.lb tyan/s2875/Options.lb tyan/s4882/Options.lb tyan/s2885/Options.lb tyan/s2895/Options.lb DIFFSTAT: ------------------------------------------------ s2875/Options.lb | 4 ++-- s2881/Options.lb | 4 ++-- s2882/Options.lb | 4 ++-- s2885/Options.lb | 4 ++-- s2891/Options.lb | 4 ++-- s2892/Options.lb | 4 ++-- s2895/Options.lb | 4 ++-- s4880/Options.lb | 4 ++-- s4882/Options.lb | 4 ++-- 9 files changed, 18 insertions(+), 18 deletions(-) PATCH: ------------------------------------------------ Index: s2881/Options.lb =================================================================== --- s2881/Options.lb (revision 1105) +++ s2881/Options.lb (working copy) @@ -130,10 +130,10 @@ ## ## enable CACHE_AS_RAM specifics ## -default USE_DCACHE_RAM=1 +default USE_DCACHE_RAM=0 default DCACHE_RAM_BASE=0xcf000 default DCACHE_RAM_SIZE=0x1000 -default CONFIG_USE_INIT=1 +default CONFIG_USE_INIT=0 ## ## Build code to setup a generic IOAPIC Index: s2882/Options.lb =================================================================== --- s2882/Options.lb (revision 1105) +++ s2882/Options.lb (working copy) @@ -130,10 +130,10 @@ ## ## enable CACHE_AS_RAM specifics ## -default USE_DCACHE_RAM=1 +default USE_DCACHE_RAM=0 default DCACHE_RAM_BASE=0xcf000 default DCACHE_RAM_SIZE=0x1000 -default CONFIG_USE_INIT=1 +default CONFIG_USE_INIT=0 ## ## Build code to setup a generic IOAPIC Index: s2891/Options.lb =================================================================== --- s2891/Options.lb (revision 1105) +++ s2891/Options.lb (working copy) @@ -139,10 +139,10 @@ ## ## enable CACHE_AS_RAM specifics ## -default USE_DCACHE_RAM=1 +default USE_DCACHE_RAM=0 default DCACHE_RAM_BASE=0xcf000 default DCACHE_RAM_SIZE=0x1000 -default CONFIG_USE_INIT=1 +default CONFIG_USE_INIT=0 ## Index: s4880/Options.lb =================================================================== --- s4880/Options.lb (revision 1105) +++ s4880/Options.lb (working copy) @@ -130,10 +130,10 @@ ## ## enable CACHE_AS_RAM specifics ## -default USE_DCACHE_RAM=1 +default USE_DCACHE_RAM=0 default DCACHE_RAM_BASE=0xcf000 default DCACHE_RAM_SIZE=0x1000 -default CONFIG_USE_INIT=1 +default CONFIG_USE_INIT=0 ## ## Build code to setup a generic IOAPIC Index: s2892/Options.lb =================================================================== --- s2892/Options.lb (revision 1105) +++ s2892/Options.lb (working copy) @@ -139,10 +139,10 @@ ## ## enable CACHE_AS_RAM specifics ## -default USE_DCACHE_RAM=1 +default USE_DCACHE_RAM=0 default DCACHE_RAM_BASE=0xcf000 default DCACHE_RAM_SIZE=0x1000 -default CONFIG_USE_INIT=1 +default CONFIG_USE_INIT=0 ## Index: s2875/Options.lb =================================================================== --- s2875/Options.lb (revision 1105) +++ s2875/Options.lb (working copy) @@ -130,10 +130,10 @@ ## ## enable CACHE_AS_RAM specifics ## -default USE_DCACHE_RAM=1 +default USE_DCACHE_RAM=0 default DCACHE_RAM_BASE=0xcf000 default DCACHE_RAM_SIZE=0x1000 -default CONFIG_USE_INIT=1 +default CONFIG_USE_INIT=0 ## ## Build code to setup a generic IOAPIC Index: s4882/Options.lb =================================================================== --- s4882/Options.lb (revision 1105) +++ s4882/Options.lb (working copy) @@ -130,10 +130,10 @@ ## ## enable CACHE_AS_RAM specifics ## -default USE_DCACHE_RAM=1 +default USE_DCACHE_RAM=0 default DCACHE_RAM_BASE=0xcf000 default DCACHE_RAM_SIZE=0x1000 -default CONFIG_USE_INIT=1 +default CONFIG_USE_INIT=0 ## ## Build code to setup a generic IOAPIC Index: s2885/Options.lb =================================================================== --- s2885/Options.lb (revision 1105) +++ s2885/Options.lb (working copy) @@ -130,10 +130,10 @@ ## ## enable CACHE_AS_RAM specifics ## -default USE_DCACHE_RAM=1 +default USE_DCACHE_RAM=0 default DCACHE_RAM_BASE=0xcf000 default DCACHE_RAM_SIZE=0x1000 -default CONFIG_USE_INIT=1 +default CONFIG_USE_INIT=0 ## ## Build code to setup a generic IOAPIC Index: s2895/Options.lb =================================================================== --- s2895/Options.lb (revision 1105) +++ s2895/Options.lb (working copy) @@ -136,10 +136,10 @@ ## ## enable CACHE_AS_RAM specifics ## -default USE_DCACHE_RAM=1 +default USE_DCACHE_RAM=0 default DCACHE_RAM_BASE=0xcf000 default DCACHE_RAM_SIZE=0x1000 -default CONFIG_USE_INIT=1 +default CONFIG_USE_INIT=0 ## ## Build code to setup a generic IOAPIC -- Jason W. Schildt LinuxBIOS Software Engineer Linux Networx -- LinuxBIOS mailing list LinuxBIOS(a)openbios.org http://www.openbios.org/mailman/listinfo/linuxbios

2 1

RE: [LinuxBIOS] LNXI Merge: lnxi-patch-11/16
by Lu, Yinghai 06 Sep '05

06 Sep '05

I remember that if changed that to unsigned, for four ways system it will not be compiled by ROMCC. YH -----Original Message----- From: linuxbios-bounces(a)openbios.org [mailto:linuxbios-bounces@openbios.org] On Behalf Of Jason Schildt Sent: Tuesday, September 06, 2005 7:18 AM To: Stefan Reinauer Cc: linuxbios(a)openbios.org Subject: Re: [LinuxBIOS] LNXI Merge: lnxi-patch-11/16 On Tue, Sep 06, 2005 at 12:08:50PM +0200, Stefan Reinauer wrote: > * jason schildt <jschildt(a)lnxi.com> [050903 00:03]: > > +/* We can reduce the size of code generated by romcc by > > + * changing all of the fixed size types that live in registers > > + * into simple unsigned variables. (ie s/uint8_t/unsigned/g) > > + */ > > Why is this? I would consider specifying an 8bit type to be more > space-safing than using some generic untyped integer value. If not this > should be fixed in romcc.. You're right in your thinking, but at this time ROMCC converts it to an unsigned anyway and winds up producing more code doing so. So in the end the space saving measure costs more in code size produced by ROMCC. > > > /* AMD K8 Unsupported 1Ghz? */ > > if (id == (PCI_VENDOR_ID_AMD | (0x1100 << 16))) { > > - if (is_cpu_pre_e0()) // CK804 support 1G? > > > + device_t dev_2 = PCI_DEV(0,0x18,2); > > + if(pci_read_config32(dev_2,0x9c) < 0x20f00) { > > The function call looks a lot more readable here. How much is the gain > of manual inlining here? > > Stefan > > -- > LinuxBIOS mailing list > LinuxBIOS(a)openbios.org > http://www.openbios.org/mailman/listinfo/linuxbios -- Jason W. Schildt LinuxBIOS Software Engineer Linux Networx -- LinuxBIOS mailing list LinuxBIOS(a)openbios.org http://www.openbios.org/mailman/listinfo/linuxbios

1 0

[LinuxBIOS] [LinuxbiosV1] Starting the real time clock on STPC Elite
by Fathi BOUDRA 06 Sep '05

06 Sep '05

hi, Using Linuxbios V1 on a STPC Elite motherboard, the date and time were not kept. It seems to be that this thread is related to the same problem : http://www.linuxbios.org/pipermail/linuxbios/2002-December/001393.html Could someone using the STPC Elite confirm the problem ? Or suggest a solution to resolved it ? Cheers, Fathi

1 0

[LinuxBIOS] RE: Does LinuxBIOS support the Mac Mini?
by Angel 03 Sep '05

03 Sep '05

Well, the wiki says it supports the PPC series MPC74xx, MPC4xx and MPC7xx. The CPU built in the Mac Mini is a MPC7447 (revision B I believe), so I think it should be supported, shouldn't it? The wiki also says the Motorola northbridge MPC107 is supported. According to this page ( http://e-www.motorola.com/webapp/sps/site/prod_summary.jsp?code=MPC107 ) this chipset seems to be only suitable for older CPU up to the MPC7410. I couldn't find any information about the chipset used in the Mac Mini. But as Apple is just an OEM, it should be from Motorola/Freescale as well.

3 3

[LinuxBIOS] LNXI Merge: lnxi-patch-01/16
by jason schildt 03 Sep '05

03 Sep '05

## lnxi-patch-1 ## - (2)files src/southbridge/amd/amd8111/amd8111_acpi.c // amd8111_enable is commented out in public tree, but enabled in // hdama. resolution: copied over for merge DIFFSTAT --------------------------------------------------------- amd8111_acpi.c | 5 +++-- amd8111_pci.c | 1 + 2 files changed, 4 insertions(+), 2 deletions(-) PATCH --------------------------------------------------------- Index: southbridge/amd/amd8111/amd8111_pci.c =================================================================== --- southbridge/amd/amd8111/amd8111_pci.c (revision 1105) +++ southbridge/amd/amd8111/amd8111_pci.c (working copy) @@ -55,6 +55,7 @@ .enable_resources = pci_bus_enable_resources, .init = pci_init, .scan_bus = pci_scan_bridge, + /* PCI Subordinate bus reset is not implemented */ .ops_pci = &lops_pci, }; Index: southbridge/amd/amd8111/amd8111_acpi.c =================================================================== --- southbridge/amd/amd8111/amd8111_acpi.c (revision 1105) +++ southbridge/amd/amd8111/amd8111_acpi.c (working copy) @@ -97,6 +97,7 @@ #endif + /* power after power fail */ on = MAINBOARD_POWER_ON_AFTER_POWER_FAIL; get_option(&on, "power_on_after_fail"); byte = pci_read_config8(dev, PREVIOUS_POWER_STATE); @@ -106,7 +107,7 @@ } pci_write_config8(dev, PREVIOUS_POWER_STATE, byte); printk_info("set power %s after power fail\n", on?"on":"off"); - + /* Throttle the CPU speed down for testing */ on = SLOW_CPU_OFF; get_option(&on, "slow_cpu"); @@ -177,7 +178,7 @@ .enable_resources = acpi_enable_resources, .init = acpi_init, .scan_bus = scan_static_bus, -// .enable = amd8111_enable, + .enable = amd8111_enable, .ops_pci = &lops_pci, .ops_smbus_bus = &lops_smbus_bus, }; Using Opera's revolutionary e-mail client: http://www.opera.com/mail/

1 0

[LinuxBIOS] LNXI Merge: lnxi-patch02/16
by jason schildt 03 Sep '05

03 Sep '05

DESCRIPTION: --------------------------------------------------------- ## lnxi-patch-2 ## - (3)files src/southbridge/amd/amd8111/amd8111_lpc.c powermanagment removed. copied to public tree src/southbridge/amd/amd8111/Config.lb src/southbridge/amd/amd8111/amd8111_usb.c uncommented amd8111_enable DIFFSTAT: --------------------------------------------------------- Config.lb | 9 ++++----- amd8111_lpc.c | 12 ++++-------- amd8111_usb.c | 2 +- 3 files changed, 9 insertions(+), 14 deletions(-) PATCH: --------------------------------------------------------- Index: amd8111_lpc.c =================================================================== --- amd8111_lpc.c (revision 1105) +++ amd8111_lpc.c (working copy) @@ -84,7 +84,7 @@ return; } printk_spew("for IRQ, reg 0x%08x value 0x%08x 0x%08x\n", - a->reg, a->value_low, a->value_high); + a->reg, a->value_low, a->value_high); } } @@ -113,13 +113,9 @@ byte = pci_read_config8(dev, 0x46); pci_write_config8(dev, 0x46, byte | (1<<0)); - /* power after power fail */ + /* Enable 5Mib Rom window */ byte = pci_read_config8(dev, 0x43); - if (pwr_on) { - byte &= ~(1<<6); - } else { - byte |= (1<<6); - } + byte |= 0xC0; pci_write_config8(dev, 0x43, byte); /* Enable Port 92 fast reset */ @@ -179,7 +175,7 @@ static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) { pci_write_config32(dev, 0x70, - ((device & 0xffff) << 16) | (vendor & 0xffff)); + ((device & 0xffff) << 16) | (vendor & 0xffff)); } static struct pci_operations lops_pci = { Index: Config.lb =================================================================== --- Config.lb (revision 1105) +++ Config.lb (working copy) @@ -1,12 +1,11 @@ config chip.h driver amd8111.o -#driver amd8111_usb.o +driver amd8111_usb.o driver amd8111_lpc.o driver amd8111_ide.o driver amd8111_acpi.o -#driver amd8111_usb2.o -#driver amd8111_ac97.o -#driver amd8111_nic.o +driver amd8111_usb2.o +driver amd8111_ac97.o +driver amd8111_nic.o driver amd8111_pci.o driver amd8111_smbus.o -object amd8111_reset.o Index: amd8111_usb.c =================================================================== --- amd8111_usb.c (revision 1105) +++ amd8111_usb.c (working copy) @@ -26,7 +26,7 @@ .enable_resources = pci_dev_enable_resources, .init = 0, .scan_bus = scan_static_bus, -// .enable = amd8111_enable, + .enable = amd8111_enable, .ops_pci = &lops_pci, }; -- Using Opera's revolutionary e-mail client: http://www.opera.com/mail/

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