This patch fixes various LPC bugs in the ICH-4 and ICH-5 code that I
noticed while working on the ICH-3:
* DMA configuration read only half of the existing bits
* 'posted memory write enable' code looks to have been mis-inherited
from AMD
* NMI/SERR configuration was done in PCI space instead of I/O space
* Secondary IDE would be enabled whenever primary IDE was enabled
* i82801xx_enable worked incorrectly when called for a PCI device
without a corresponding disable bit
I don't have any way to test that these do more than compile, although
the identical ICH-3 code seems to work OK. The i82801xx_enable functions
should be looked at closely since there are differences between the 'CA,
'DBM, and 'ER code.
PATCH:
--- src/southbridge/intel/i82801er/i82801er_lpc.c.orig 2005-09-08
13:34:49.312500000 -0500
+++ src/southbridge/intel/i82801er/i82801er_lpc.c 2005-09-14
11:07:02.588125000 -0500
@@ -8,9 +8,11 @@
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include <pc80/mc146818rtc.h>
+#include <pc80/isa-dma.h>
+#include <arch/io.h>
#include "i82801er.h"
-void isa_dma_init(void); /* from /pc80/isa-dma.c */
+
#define NMI_OFF 0
@@ -52,7 +54,7 @@
{
uint16_t word;
int i;
- word = pci_read_config8(dev, PCI_DMA_CFG);
+ word = pci_read_config16(dev, PCI_DMA_CFG);
word &= ((1 << 10) - (1 << 8));
for(i = 0; i < 8; i++) {
if (i == 4)
@@ -124,9 +126,15 @@
i82801er_enable_serial_irqs(dev);
+#ifdef SUSPICIOUS_LOOKING_CODE
+ // The ICH-5 datasheet does not mention this configuration
register.
+ // This code may have been inherited (incorrectly) from code for
the AMD 766 southbridge,
+ // which *does* support this functionality.
+
/* posted memory write enable */
byte = pci_read_config8(dev, 0x46);
pci_write_config8(dev, 0x46, byte | (1<<0));
+#endif
/* power after power fail */
/* FIXME this doesn't work! */
@@ -145,16 +153,16 @@
#endif
/* Set up NMI on errors */
- byte = pci_read_config8(dev, 0x61);
- byte |= (1 << 3); /* IOCHK# NMI Enable */
- byte |= (1 << 6); /* PCI SERR# Enable */
- pci_write_config8(dev, 0x61, byte);
- byte = pci_read_config8(dev, 0x70);
+ byte = inb(0x61);
+ byte &= ~(1 << 3); /* IOCHK# NMI Enable */
+ byte &= ~(1 << 2); /* PCI SERR# Enable */
+ outb(byte, 0x61);
+ byte = inb(0x70);
nmi_option = NMI_OFF;
get_option(&nmi_option, "nmi");
if (nmi_option) {
- byte |= (1 << 7); /* set NMI */
- pci_write_config8(dev, 0x70, byte);
+ byte &= ~(1 << 7); /* set NMI */
+ outb(byte, 0x70);
}
/* Initialize the real time clock */
--- src/southbridge/intel/i82801dbm/i82801dbm_lpc.c.orig
2005-09-08 13:34:50.750000000 -0500
+++ src/southbridge/intel/i82801dbm/i82801dbm_lpc.c 2005-09-14
11:07:20.103750000 -0500
@@ -8,9 +8,11 @@
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include <pc80/mc146818rtc.h>
+#include <pc80/isa-dma.h>
+#include <arch/io.h>
#include "i82801dbm.h"
-void isa_dma_init(void); /* from /pc80/isa-dma.c */
+
#define NMI_OFF 0
@@ -52,7 +54,7 @@
{
uint16_t word;
int i;
- word = pci_read_config8(dev, PCI_DMA_CFG);
+ word = pci_read_config16(dev, PCI_DMA_CFG);
word &= ((1 << 10) - (1 << 8));
for(i = 0; i < 8; i++) {
if (i == 4)
@@ -124,9 +126,15 @@
i82801dbm_enable_serial_irqs(dev);
+#ifdef SUSPICIOUS_LOOKING_CODE
+ // The ICH-4 datasheet does not mention this configuration
register.
+ // This code may have been inherited (incorrectly) from code for
the AMD 766 southbridge,
+ // which *does* support this functionality.
+
/* posted memory write enable */
byte = pci_read_config8(dev, 0x46);
pci_write_config8(dev, 0x46, byte | (1<<0));
+#endif
/* power after power fail */
/* FIXME this doesn't work! */
@@ -145,16 +153,16 @@
#endif
/* Set up NMI on errors */
- byte = pci_read_config8(dev, 0x61);
- byte |= (1 << 3); /* IOCHK# NMI Enable */
- byte |= (1 << 6); /* PCI SERR# Enable */
- pci_write_config8(dev, 0x61, byte);
- byte = pci_read_config8(dev, 0x70);
+ byte = inb(0x61);
+ byte &= ~(1 << 3); /* IOCHK# NMI Enable */
+ byte &= ~(1 << 2); /* PCI SERR# Enable */
+ outb(byte, 0x61);
+ byte = inb(0x70);
nmi_option = NMI_OFF;
get_option(&nmi_option, "nmi");
if (nmi_option) {
- byte |= (1 << 7); /* set NMI */
- pci_write_config8(dev, 0x70, byte);
+ byte &= ~(1 << 7); /* set NMI */
+ outb(byte, 0x70);
}
/* Initialize the real time clock */
--- src/southbridge/intel/i82801er/i82801er_ide.c.orig 2005-09-14
11:46:49.213125000 -0500
+++ src/southbridge/intel/i82801er/i82801er_ide.c 2005-09-14
11:21:59.916250000 -0500
@@ -26,7 +26,7 @@
word = pci_read_config16(dev, 0x42);
word &= ~((1 << 15));
- if (enable_a) {
+ if (enable_b) {
/* Enable secondary ide interface */
word |= (1<<15);
printk_debug("IDE1 ");
--- src/southbridge/intel/i82801dbm/i82801dbm_ide.c.orig
2005-09-14 11:45:41.197500000 -0500
+++ src/southbridge/intel/i82801dbm/i82801dbm_ide.c 2005-09-14
11:21:10.385000000 -0500
@@ -26,7 +26,7 @@
word = pci_read_config16(dev, 0x42);
word &= ~((1 << 15));
- if (enable_a) {
+ if (enable_b) {
/* Enable secondary ide interface */
word |= (1<<15);
printk_debug("IDE1 ");
--- src/southbridge/intel/i82801er/i82801er.c.orig 2005-09-08
13:34:49.343750000 -0500
+++ src/southbridge/intel/i82801er/i82801er.c 2005-09-14
11:56:26.666250000 -0500
@@ -6,48 +6,58 @@
void i82801er_enable(device_t dev)
{
- device_t lpc_dev;
- unsigned int index;
- uint16_t reg_old, reg;
-
-// all 82801er device ares in bus 0
- unsigned int devfn;
- devfn = PCI_DEVFN(0x1f, 0); // lpc
- lpc_dev = dev_find_slot(0, devfn); // 0
- if (!lpc_dev ) {
- return;
- }
-#if 0
- if ((lpc_dev->vendor != PCI_VENDOR_ID_INTEL) ||
- (lpc_dev->device != PCI_DEVICE_ID_INTEL_82801ER_1F0)) {
- uint32_t id;
- id = pci_read_config32(lpc_dev, PCI_VENDOR_ID);
- if (id != (PCI_VENDOR_ID_INTEL |
(PCI_DEVICE_ID_INTEL_82801ER_1F0 << 16))) {
- return;
- }
- }
-#endif
-
- index = (dev->path.u.pci.devfn & 7);
- if((dev->path.u.pci.devfn & ~0x7)==devfn) { // D=0x1f
- if(index==0){ //1f0
- index = 14;
- }
- } else { // D=0x1d
- index += 8;
- }
-
- reg_old = pci_read_config16(lpc_dev, FUNC_DIS);
- reg = reg_old;
- reg &= ~(1<<index); // enable it
- if (!dev->enabled) {
- reg |= (1<<index); // disable it
- }
- if (reg != reg_old) {
- pci_write_config16(lpc_dev, FUNC_DIS, reg);
- }
- reg = pci_read_config16(lpc_dev, FUNC_DIS);
-
+ unsigned int index = 0;
+ uint8_t bHasDisableBit = 0;
+ uint16_t cur_disable_mask, new_disable_mask;
+
+// all 82801er devices are in bus 0
+ unsigned int devfn = PCI_DEVFN(0x1f, 0); // lpc
+ device_t lpc_dev = dev_find_slot(0, devfn); // 0
+ if (!lpc_dev)
+ return;Z
+
+ // Calculate disable bit position for specified device:function
+ // NOTE: For ICH-5, only the following devices can be disabled:
+ // D31: F0, F1, F2, F3, F5, F6,
+ // D29: F0, F1, F2, F3, F7
+
+ if (PCI_SLOT(dev->path.u.pci.devfn) == 31) {
+ index = PCI_FUNC(dev->path.u.pci.devfn);
+
+ switch (index) {
+ case 0:
+ case 1:
+ case 2:
+ case 3:
+ case 5:
+ case 6:
+ bHasDisableBit = 1;
+ break;
+
+ default:
+ break;
+ };
+
+ if (index == 0)
+ index = 14; // D31:F0 bit is an
exception
+
+ } else if (PCI_SLOT(dev->path.u.pci.devfn) == 29) {
+ index = 8 + PCI_FUNC(dev->path.u.pci.devfn);
+
+ if ((PCI_FUNC(dev->path.u.pci.devfn) < 4) ||
(PCI_FUNC(dev->path.u.pci.devfn) == 7))
+ bHasDisableBit = 1;
+ }
+
+ if (bHasDisableBit) {
+ cur_disable_mask = pci_read_config16(lpc_dev, FUNC_DIS);
+ new_disable_mask = cur_disable_mask & ~(1<<index);
// enable it
+ if (!dev->enabled) {
+ new_disable_mask |= (1<<index); // disable it
+ }
+ if (new_disable_mask != cur_disable_mask) {
+ pci_write_config16(lpc_dev, FUNC_DIS,
new_disable_mask);
+ }
+ }
}
struct chip_operations southbridge_intel_i82801er_ops = {
--- src/southbridge/intel/i82801dbm/i82801dbm.c.orig 2005-09-08
13:34:50.765625000 -0500
+++ src/southbridge/intel/i82801dbm/i82801dbm.c 2005-09-14
11:58:02.353750000 -0500
@@ -6,48 +6,57 @@
void i82801dbm_enable(device_t dev)
{
- device_t lpc_dev;
- unsigned int index;
- uint16_t reg_old, reg;
-
-// all 82801dbm device ares in bus 0
- unsigned int devfn;
- devfn = PCI_DEVFN(0x1f, 0); // lpc
- lpc_dev = dev_find_slot(0, devfn); // 0
- if (!lpc_dev ) {
- return;
- }
-#if 0
- if ((lpc_dev->vendor != PCI_VENDOR_ID_INTEL) ||
- (lpc_dev->device != PCI_DEVICE_ID_INTEL_82801DBM_1F0)) {
- uint32_t id;
- id = pci_read_config32(lpc_dev, PCI_VENDOR_ID);
- if (id != (PCI_VENDOR_ID_INTEL |
(PCI_DEVICE_ID_INTEL_82801DBM_1F0 << 16))) {
- return;
- }
- }
-#endif
-
- index = (dev->path.u.pci.devfn & 7);
- if((dev->path.u.pci.devfn & ~0x7)==devfn) { // D=0x1f
- if(index==0){ //1f0
- index = 14;
- }
- } else { // D=0x1d
- index += 8;
- }
-
- reg_old = pci_read_config16(lpc_dev, FUNC_DIS);
- reg = reg_old;
- reg &= ~(1<<index); // enable it
- if (!dev->enabled) {
- reg |= (1<<index); // disable it
- }
- if (reg != reg_old) {
- pci_write_config16(lpc_dev, FUNC_DIS, reg);
- }
- reg = pci_read_config16(lpc_dev, FUNC_DIS);
-
+ unsigned int index = 0;
+ uint8_t bHasDisableBit = 0;
+ uint16_t cur_disable_mask, new_disable_mask;
+
+// all 82801dbm devices are in bus 0
+ unsigned int devfn = PCI_DEVFN(0x1f, 0); // lpc
+ device_t lpc_dev = dev_find_slot(0, devfn); // 0
+ if (!lpc_dev)
+ return;
+
+ // Calculate disable bit position for specified device:function
+ // NOTE: For ICH-4, only the following devices can be disabled:
+ // D31: F0, F1, F3, F5, F6,
+ // D29: F0, F1, F2, F7
+
+ if (PCI_SLOT(dev->path.u.pci.devfn) == 31) {
+ index = PCI_FUNC(dev->path.u.pci.devfn);
+
+ switch (index) {
+ case 0:
+ case 1:
+ case 3:
+ case 5:
+ case 6:
+ bHasDisableBit = 1;
+ break;
+
+ default:
+ break;
+ };
+
+ if (index == 0)
+ index = 14; // D31:F0 bit is an
exception
+
+ } else if (PCI_SLOT(dev->path.u.pci.devfn) == 29) {
+ index = 8 + PCI_FUNC(dev->path.u.pci.devfn);
+
+ if ((PCI_FUNC(dev->path.u.pci.devfn) < 3) ||
(PCI_FUNC(dev->path.u.pci.devfn) == 7))
+ bHasDisableBit = 1;
+ }
+
+ if (bHasDisableBit) {
+ cur_disable_mask = pci_read_config16(lpc_dev, FUNC_DIS);
+ new_disable_mask = cur_disable_mask & ~(1<<index);
// enable it
+ if (!dev->enabled) {
+ new_disable_mask |= (1<<index); // disable it
+ }
+ if (new_disable_mask != cur_disable_mask) {
+ pci_write_config16(lpc_dev, FUNC_DIS,
new_disable_mask);
+ }
+ }
}
struct chip_operations southbridge_intel_i82801dbm_control = {
