coreboot

coreboot@coreboot.org

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39687 discussions

[RFC] Proposal to move all FSP 1.x binaries to "legacy" branch
by Desimone, Nathaniel L 09 Sep '20

09 Sep '20

Hi Everyone, Given that the newest coreboot releases have not supported the FSP 1.x specification for years now, seems that the 1.x FSP binaries at https://github.com/intel/FSP have become increasingly limited in their usefulness. For this reason, I would like to move those older binaries off master branch and create a new “legacy” branch to store them. I'll be sure to mention the legacy branch in the readme.md file in master. Any concerns with this change? Thanks, Nate

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New Defects reported by Coverity Scan for coreboot
by scan-admin＠coverity.com 08 Sep '20

08 Sep '20

Hi, Please find the latest report on new defect(s) introduced to coreboot found with Coverity Scan. 1 new defect(s) introduced to coreboot found with Coverity Scan. New defect(s) Reported-by: Coverity Scan Showing 1 of 1 defect(s) ** CID 1432491: Error handling issues (CHECKED_RETURN) /src/mainboard/google/volteer/mainboard.c: 46 in mainboard_update_soc_chip_config() ________________________________________________________________________________________________________ *** CID 1432491: Error handling issues (CHECKED_RETURN) /src/mainboard/google/volteer/mainboard.c: 46 in mainboard_update_soc_chip_config() 40 dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; 41 dev->ops->get_smbios_strings = mainboard_smbios_strings; 42 } 43 44 void mainboard_update_soc_chip_config(struct soc_intel_tigerlake_config *cfg) 45 { >>> CID 1432491: Error handling issues (CHECKED_RETURN) >>> Calling "tlcl_lib_init" without checking return value (as is done elsewhere 10 out of 11 times). 46 tlcl_lib_init(); 47 if (cr50_is_long_interrupt_pulse_enabled()) { 48 printk(BIOS_INFO, "Enabling S0i3.4\n"); 49 } else { 50 /* 51 * Disable S0i3.4, preventing the GPIO block from switching to ________________________________________________________________________________________________________ To view the defects in Coverity Scan visit, https://u15810271.ct.sendgrid.net/ls/click?upn=HRESupC-2F2Czv4BOaCWWCy7my0P…

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Intel DCI-DbC on Skylake-U
by Benjamin Doron 07 Sep '20

07 Sep '20

Hi all, Does Skylake-U support DCI over USB3-DbC (standard USB 3.0 debug cable), or only with the SVT-CCA? I've seen conflicting information on this matter. In my attempts (using USB3-DbC), Intel System Debugger was able to successfully identify only the PCH as a "custom" configuration, but just once (perhaps due to an issue with the host, but now, the "Target Indicator" indicates an "access error"). Debugging the PCH is not very useful to me, but as far as I can tell, my board (an Acer Aspire VN7-572G laptop) should be compatible with DCI in general. I'm not certain what I'm looking to see on the schematics or boardview, but I think that the CPU and PCH JTAG lines are connected. The ME also permits CPU debugging (if it's relevant, Boot Guard is disabled). Thanks for any and all help, Benjamin Doron

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Re: [coreboot]: Help request with SMSC SCH3114 superio.
by Jose Trujillo 02 Sep '20

02 Sep '20

Dear Michal, I am sorry for the late reply but on Friday something went wrong with my coreboot installation and was unable to boot and I have to reinstall it again and I just resumed this morning on this issue. (you) don't think loading the watchdog module will help in any way, actually the opposite. (Me) I did the modprobe of the watchdog module just to ask linux to give me the base address of the runtime registers "0xa00" of the original bios. (you) I recommend using https://github.com/adurbin/iotools (you) Superiotool will simply dump all registers and may alternatively dump IO too. (Me) Thank you for your great advice I will go by the Superiotool route (patching it) but so far I am dumping using "ioports" in the following way: on root: for i in $(seq 0xa00 0xa7f); do echo -n "$i: "; inb $i; done; $i = $((++i)) (you) I assume you have configured runtime registers IOBASE right? (Me) I found out (because of your advise) that the runtime registers base address was wrong on my devicetree (0xe00 instead 0xa00) I set it correctly then linux was able to "see" this range and dumped the registers with the string shown above. Now I can compare both dumps and I can see the pins for the UART ports 2-4 are all GPIO inputs (1). (Me) I set manually the GPIOs from linux using ioport's function outb and all the 4 ports work correctly. Now I am trying to set from coreboot but I am still unsuccessful. Looking at you dell Optiplex 9010 you set the following runtime registers under romstage.c -> mainboard_early_init /* Disable SMIs and clear SMI status */ outb(0, SCH5545_RUNTIME_REG_BASE + SCH5545_RR_SMI_EN); outb(SCH5545_SMI_GLOBAL_STS, SCH5545_RUNTIME_REG_BASE + SCH5545_RR_SMI_STS); and I do similar to you under romstage.c -> mainboard_early_init: outb(0x55, 0x2e); outb(0x05, 0x0a3f); /* GP50= RI_2 : in */ outb(0x05, 0x0a40); /* GP51= DCD_2 : in */ outb(0x05, 0x0a41); /* GP52= RXD_2 : in */ outb(0x04, 0x0a42); /* GP53= TXD_2 : out */ outb(0x05, 0x0a43); /* GP54= DSR_2 : in */ outb(0x04, 0x0a44); /* GP55= RTS_2 : out */ outb(0x05, 0x0a45); /* GP56= CTS_2 : in */ outb(0x04, 0x0a46); /* GP57= DTR_2 : out */ outb(0xaa, 0x2e); but It doesn't work. Also I set the same code under mainboard.c -> mainboard_init but neither work. Any advice on this? because I cannot find any information on the datasheet on how to set those registers and I suppose I just have to set to the 0xa00 base address + register. Thank you, Jose Trujillo.

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Flashing coreboot on asus KGPE-D16
by Ale 02 Sep '20

02 Sep '20

Hello, I have an Asus KGPE-D16 motherboard, is it possible, as far as you know, to flash coreboot with the internal method, i.e. using flashrom on Ubuntu/Debian? Moreover I would like to know if is possible to download the coreboot.rom from anywhere (maybe with seabios included) Thank you very much! Best regards Alessio

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New Defects reported by Coverity Scan for coreboot
by scan-admin＠coverity.com 01 Sep '20

01 Sep '20

Hi, Please find the latest report on new defect(s) introduced to coreboot found with Coverity Scan. 1 new defect(s) introduced to coreboot found with Coverity Scan. 3 defect(s), reported by Coverity Scan earlier, were marked fixed in the recent build analyzed by Coverity Scan. New defect(s) Reported-by: Coverity Scan Showing 1 of 1 defect(s) ** CID 1432270: Parse warnings (PARSE_ERROR) /3rdparty/arm-trusted-firmware/include/lib/libc/stdint.h: 93 in () ________________________________________________________________________________________________________ *** CID 1432270: Parse warnings (PARSE_ERROR) /3rdparty/arm-trusted-firmware/include/lib/libc/stdint.h: 93 in () 87 #define INTMAX_C(x) x ## LL 88 #define UINTMAX_C(x) x ## ULL 89 90 typedef signed char int8_t; 91 typedef short int16_t; 92 typedef int int32_t; >>> CID 1432270: Parse warnings (PARSE_ERROR) >>> invalid redeclaration of type name "int64_t" (declared at line 1413 of "/home/coreboot/slave-root/workspace/coreboot-coverity/cov-int/emit/9bbe52bbb28b/config/29ec7ea376092a30b16589a913b3478c/gcc-config-0/coverity-compiler-compat.h") 93 typedef long long int64_t; 94 95 typedef unsigned char uint8_t; 96 typedef unsigned short uint16_t; 97 typedef unsigned int uint32_t; 98 typedef unsigned long long uint64_t; ________________________________________________________________________________________________________ To view the defects in Coverity Scan visit, https://u15810271.ct.sendgrid.net/ls/click?upn=HRESupC-2F2Czv4BOaCWWCy7my0P…

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New on blogs.coreboot.org: [GSoC] libgfxinit: Add support for Bay Trail
by blogs.coreboot.org 31 Aug '20

31 Aug '20

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New on blogs.coreboot.org: [GSoC] Address Sanitizer, Wrap-up
by blogs.coreboot.org 31 Aug '20

31 Aug '20

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Thinkpad T410 flashing questions
by Stéphane Delaunay 30 Aug '20

30 Aug '20

Hello everyone, I came across an old T410 that I'd like to install coreboot on to swap the wifi-adapter, remove the IME and overall "upgrade" the laptop a bit. Now, though many other Thinkpads from that era are well supported, the T410 was still unsupported until it was added recently in 4.11 and I've read conflicting reports on how well it works with coreboot. The official documentation (https://doc.coreboot.org/mainboard/lenovo/t410.html) only mentions issues with the dock and vboot, which is fine by me. Also, this patch looks quite promising - https://review.coreboot.org/c/coreboot/+/11791 Is that already part of the main repository as of 4.12 or do I have to add it somehow? Also, the documentation links to a tutorial for flashing a powered chip, yet I have read that people have used guides for other laptops using USB programmers and (more or less successfully) flashed the laptop. Is it possible to use a ch431a programmer at 3.3v while the laptop is powered down or could that seriously damage the hardware? Is there anything else I should be cautious of with this board? Has somebody maybe even got experience with flashing the T410? Kind regards, Steph

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New Defects reported by Coverity Scan for coreboot
by scan-admin＠coverity.com 25 Aug '20

25 Aug '20

Hi, Please find the latest report on new defect(s) introduced to coreboot found with Coverity Scan. 1 new defect(s) introduced to coreboot found with Coverity Scan. 2 defect(s), reported by Coverity Scan earlier, were marked fixed in the recent build analyzed by Coverity Scan. New defect(s) Reported-by: Coverity Scan Showing 1 of 1 defect(s) ** CID 1431994: Error handling issues (CHECKED_RETURN) /src/vendorcode/google/chromeos/cse_board_reset.c: 18 in cse_board_reset() ________________________________________________________________________________________________________ *** CID 1431994: Error handling issues (CHECKED_RETURN) /src/vendorcode/google/chromeos/cse_board_reset.c: 18 in cse_board_reset() 12 13 void cse_board_reset(void) 14 { 15 struct cr50_firmware_version version; 16 17 /* Initialize TPM and get the cr50 firmware version. */ >>> CID 1431994: Error handling issues (CHECKED_RETURN) >>> Calling "tlcl_lib_init" without checking return value (as is done elsewhere 9 out of 10 times). 18 tlcl_lib_init(); 19 cr50_get_firmware_version(&version); 20 /* 21 * Cr50 firmware versions 0.[3|4].20 or newer support strap config 0xe where PLTRST from 22 * AP is connected to cr50's PLTRST# signal. So return immediately and trigger a 23 * global reset. ________________________________________________________________________________________________________ To view the defects in Coverity Scan visit, https://u15810271.ct.sendgrid.net/ls/click?upn=HRESupC-2F2Czv4BOaCWWCy7my0P…

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