coreboot March 2025

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31 discussions

[coreboot - Support #584] (New) [x200] DDR3 SPD value are read but memtest doesn't display them
by David Duchesne 21 Mar '25

21 Mar '25

Issue #584 has been reported by David Duchesne. ---------------------------------------- Support #584: [x200] DDR3 SPD value are read but memtest doesn't display them https://ticket.coreboot.org/issues/584 * Author: David Duchesne * Status: New * Priority: Normal * Target version: none * Start date: 2025-03-19 ---------------------------------------- Hello, Before opening an issue on memtest issue tracker, I would like to know if the DDR3 SPD reading is correct because with memtest 7.20 (64bit build), the main screen is fully empty, instead of showing: ``` Memory SPD Information ---- - Slot 0 : RAM SIZE / SPEED / PART NUMBER - Slot 1 : RAM SIZE / SPEED / PART NUMBER ``` Also, no mention of the RAM CAS just above. It is empty. Otherwise the test is running correctly. I'm having the same issue with a t400, r400 & t500 and memtest 7.20 (and earlier) All my lenovo are running coreboot 24.12 and have **CONFIG_DUMP_SMBIOS_TYPE17=y** Otherwise dmidecode have no issue reporting those values, see below. Any advice appreciated. Thanks. ``` $ dmidecode -t 17 # dmidecode 3.6 Getting SMBIOS data from sysfs. SMBIOS 3.0 present. Handle 0x000A, DMI type 17, 40 bytes Memory Device Array Handle: 0x0009 Error Information Handle: Not Provided Total Width: 64 bits Data Width: 64 bits Size: 4 GB Form Factor: SODIMM Set: None Locator: Channel-0-DIMM-0 Bank Locator: BANK 0 Type: DDR3 Type Detail: Unknown Synchronous Speed: 1067 MT/s Manufacturer: Samsung Serial Number: 4608a20b Asset Tag: Channel-0-DIMM-0-AssetTag Part Number: M471B5273CH0-CF8 Rank: 2 Configured Memory Speed: 1067 MT/s Minimum Voltage: Unknown Maximum Voltage: Unknown Configured Voltage: Unknown Handle 0x000B, DMI type 17, 40 bytes Memory Device Array Handle: 0x0009 Error Information Handle: Not Provided Total Width: 64 bits Data Width: 64 bits Size: 4 GB Form Factor: SODIMM Set: None Locator: Channel-1-DIMM-0 Bank Locator: BANK 1 Type: DDR3 Type Detail: Unknown Synchronous Speed: 1067 MT/s Manufacturer: Samsung Serial Number: 4608a20b Asset Tag: Channel-1-DIMM-0-AssetTag Part Number: M471B5273CH0-CF8 Rank: 2 Configured Memory Speed: 1067 MT/s Minimum Voltage: Unknown Maximum Voltage: Unknown Configured Voltage: Unknown ``` -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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2025-03-19 - coreboot Leadership Meeting Canceled
by mina＠coreboot.org 18 Mar '25

18 Mar '25

Dear coreboot Community, Please note that our leadership meeting scheduled for tomorrow, March 19 has been canceled, as the issue on the agenda has already been resolved. Thank you. Best regards, Mina.

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coreboot Meetings Announcement And Agenda Call
by mina＠coreboot.org 17 Mar '25

17 Mar '25

Dear coreboot Community, Our upcoming leadership meeting is scheduled for Wednesday, March 19, 2025. [1] Please take a moment to update the agenda with matters you wish to see addressed during the meeting. [2] Thank you. Best regards, Mina Asante. [1](https://coreboot.org/calendar.html) [2](https://docs.google.com/document/d/1NRXqXcLBp5pFkHiJbrLdv3Spqh1Hu086HYkK…

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coreboot 25.03 release schedule
by coreboot org 13 Mar '25

13 Mar '25

Hi everyone, This is the notification that we're two weeks away from the coreboot 25.03 release tag, scheduled for Thursday, March 27th. Please mark patches you want to be merged before the release with the hashtag “coreboot_release_25.03”. There's no promise that these will get merged, but we will try to get everything on the list in. Mark any patches that need to be merged *after* the release with the hashtag "post_coreboot_release_25.03" As usual, we have a 1 week delay after the new version is tagged before the announcement to allow for testing of the release. This gives us a chance to fix any issues that are found before making the release public. The 25.03 public announcement is scheduled for April 3rd. If you have any questions or concerns, please let the coreboot release team know or reply to this email. Thanks, Martin

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[coreboot - Feature #461] Replacing Haswell mrc.bin blob with free software
by gaspar ilom 12 Mar '25

12 Mar '25

Issue #461 has been updated by gaspar ilom. The patch train got merged: https://review.coreboot.org/c/coreboot/+/81897/4 Anyway, in heads we have made an effort to use NRI on the W541 and T440p boards. However boot times are between 10 and 20s. So it seems like the mrc cache is not properly build and reused. Also, on the W541 S3 resume does not work (just reboots the machine). I can offer testing and helping debugging this feature: https://github.com/linuxboot/heads/pull/1923 ---------------------------------------- Feature #461: Replacing Haswell mrc.bin blob with free software https://ticket.coreboot.org/issues/461#change-1999 * Author: akjuxr3 akjuxr3 * Status: In Progress * Priority: Normal * Assignee: Angel Pons * Category: chipset configuration * Target version: none * Start date: 2020-04-01 * Related links: https://review.coreboot.org/q/topic:haswell-nri * Affected hardware: All Haswell mainboards ---------------------------------------- Currently in case of the ability to run as less amount of closed source software as possible and still have Microcode updates the reduced Intel ME with disabled bit in IFD and the lga1155 or the mobile versions of those cpus are the only option for x86_64 out there. The next cpu generation (Haswell) inside for example T440p and W541 require the binary blob mrc.bin Are there any plans of replacing the Haswell mrc.bin with free software? Or have the x86_64 platform be given up when the goal is to run just free software and the people should move to aarch64 or risc-v? -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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2025_03_12 coreboot Group Review Sesssion
by mina＠coreboot.org 10 Mar '25

10 Mar '25

Hello coreboot! Please note that we have an upcoming group review session scheduled for Wednesday, March 12. https://meet.google.com/kpu-yozw-gtt Check the coreboot calendar for the time in your timezone: https://coreboot.org/calendar.html As usual, we'll begin by reviewing a few patches together, then switch to individual reviews. However, everyone will still be available if you have questions about the patch you're reviewing. Here is the link to the list of patches to be reviewed this week: (https://docs.google.com/spreadsheets/d/1io-tewVlkX3PAkhR9ttCKjJXiXR9Emy6qsY…). Kindly add any specific patches you'd like the group to review to the top of the sheet. Thank you. Best regards, Mina.

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[coreboot - Bug #580] (New) smbios table only recorded data for one slot
by Keith Hui 09 Mar '25

09 Mar '25

Issue #580 has been reported by Keith Hui. ---------------------------------------- Bug #580: smbios table only recorded data for one slot https://ticket.coreboot.org/issues/580 * Author: Keith Hui * Status: New * Priority: Normal * Category: coreboot common code * Start date: 2025-03-09 * Affected hardware: asus/p8z77-v_le_plus ---------------------------------------- I entered smbios slot description for 5 slots in devicetree (via an overridetree.cb), but after booting only the last slot is recorded in the data table. overridetree.cb ``` device domain 0 on subsystemid 0x1043 0x84ca inherit device ref peg11 on # PCIEX_16_2 smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthLong" "PCIEX16_2" "SlotDataBusWidth8X" end chip southbridge/intel/bd82x6x register "usb_port_config" = "{ /* not relevant */ }" register "gen1_dec" = "0x000c0291" # NCT6779 HWM register "gen4_dec" = "0x0000ff29" # Could be for KB3722 EC device ref pcie_rp1 on # PCIEX_16_3 (electrical x2 or x4) smbios_slot_desc "SlotTypePciExpressGen2X4" "SlotLengthLong" "PCIEX16_3" "SlotDataBusWidth4X" end device ref pcie_rp3 on smbios_slot_desc "SlotTypePciExpressGen2X1" "SlotLengthShort" "PCIEX1_1" "SlotDataBusWidth1X" end device ref pcie_rp4 on smbios_slot_desc "SlotTypePciExpressGen2X1" "SlotLengthShort" "PCIEX1_2" "SlotDataBusWidth1X" end device ref pcie_rp5 on # RTL8111F LAN chip drivers/net register "customized_leds" = "0x482" device pci 00.0 on subsystemid 0x1043 0x8505 end end end device ref pcie_rp6 on # ASM1083 PCI bridge subsystemid 0x1043 0x8489 smbios_slot_desc "SlotTypePci" "SlotLengthLong" "PCI1" "SlotDataBusWidth32Bit" end device ref pcie_rp7 on # Marvell 88SE9120 ESATA6G subsystemid 0x1043 0x83ba end device ref pcie_rp8 on # ASM1042 USB3 subsystemid 0x1043 0x8488 end device ref hda on subsystemid 0x1043 0x841a end device ref lpc on chip superio/nuvoton/nct6779d device pnp 2e.1 off end # Parallel device pnp 2e.2 on # UART A io 0x60 = 0x3f8 irq 0x70 = 4 end device pnp 2e.3 off end # UART B, IR device pnp 2e.5 on # PS2 KBC io 0x60 = 0x0060 # KBC1 base io 0x62 = 0x0064 # KBC2 base irq 0x70 = 1 # Keyboard IRQ irq 0x72 = 12 # Mouse IRQ # KBC 12Mhz/A20 speed/sw KBRST drq 0xf0 = 0x82 end device pnp 2e.6 off end # CIR device pnp 2e.7 off end # GPIOs 6-8 device pnp 2e.8 off end # WDT1 GPIO 0-1 device pnp 2e.108 on end # GPIO0 device pnp 2e.109 on end # GPIO1 device pnp 2e.509 on end # GPIO5 all in device pnp 2e.a on # ACPI drq 0xe7 = 0x11 drq 0xf2 = 0x5d # Enable PME end device pnp 2e.b on # H/W Monitor, FP LED io 0x60 = 0x290 io 0x62 = 0 irq 0x70 = 0 drq 0xe4 = 0xf9 # Use GP50/52/55 end device pnp 2e.d off end # WDT1 device pnp 2e.e off end # CIR wake-up device pnp 2e.f off end device pnp 2e.14 on end # Port 80 UART device pnp 2e.16 off end # Deep sleep end end end end ``` Output of dmidecode -t9 ``` # dmidecode 3.6 Getting SMBIOS data from sysfs. SMBIOS 3.0.0 present. Handle 0x0015, DMI type 9, 19 bytes System Slot Information Designation: PCI1 Type: PCI Data Bus Width: 32 bit Current Usage: In Use Length: Long ID: 0 Characteristics: 5.0 V is provided 3.3 V is provided PME signal is supported Bus Address: 0000:00:1c.4 Data Bus Width (Base): 1 Peer Devices: 0 ``` I expect to see all 5 slots returned. -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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[announce] flashprog v1.4 is out!
by Nico Huber 09 Mar '25

09 Mar '25

Hi, I'm glad to announce the release of flashprog v1.4. This time we've mostly updated the flash chip database, added 90 new entries and polished many existing ones. You can read more about it in the full release notes[1]. As usual, you can download the source via Git[2] (tag `v1.4`) or as tarball[3]. Cheers, Nico [1] https://flashprog.org/wiki/Flashprog/v1.4 [2] https://github.com/SourceArcade/flashprog [3] https://flashprog.org/releases/flashprog-v1.4.tar.bz2

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2025-03-05 - coreboot Leadership Meeting Minutes
by mina＠coreboot.org 06 Mar '25

06 Mar '25

# 2025-03-05 - coreboot Leadership Meeting ## Attendees Mina Asante, Jon Murphy, Felix Singer, Benjamin Doron, Felix Held, Andre, Andy Ebrahiem, Jeremy Compostella, Martin Roth, Matt DeVillier, David Hendricks, Jay Talbott, Julius Werner, Karthik R. ## Open Action Items * 2024-11-27 * [Open] Send out poll with regards to LLM usage (requested by SFC) * 2024-10-30 * [Open] Add clarification to docs, “do not use gerrit change-id or CB: format in reference to already-merged patches”. * 2024-10-16 * [Open] Matt: Set up a meeting to discuss board status alternatives and send out invites. * Decouple data collection with uploading * Require gerrit credentials or other auth to push * Json format? * https://github.com/chrultrabook/linux-tools/blob/main/debugging.sh * 2024-09-18 * [Open] Jon: Schedule a dedicated meeting to discuss the Coverity defects and action plan. * Werner: Send out an invite for the meeting. Sent out a poll to find a time slot: https://rallly.co/invite/1c8J3azXAcje * 2024-05-01 * [Open] Nick Van Der Harst volunteered for Dutch. "gogo gogo" would like to translate to Russian (?) * 2024-01-10 * Nico: (https://review.coreboot.org/q/topic:enforce_region_api) * [Open] Daniel: Look at how we want to localize (non-console) strings for coreboot. Long term project. ## Minutes ### [Benjamin] Add support for sharing SMM with the payload * To support UEFI secure boot effectively, we need to perform the verify and write steps of its variables together, in SMM. Consequently, we propose a solution where coreboot ‘owns’ SMM (initialises and installs all its regular SMI handlers), and the payload is permitted to install its own SMI handlers within a dedicated SMRAM region that coreboot will call into (and return from) for payload-specific use-cases. While this was developed for EDK2, to support secure boot, note that it’s not UEFI-specific, and contains nothing specific to secure boot. This is a superior solution to one we proposed in 2023, called “[Add support for calling SMM payloads.](https://docs.google.com/document/d/1S1hLGc7nhBIaD3wN3eylyjhMMqEo… * Earlier proposal handed SMM control to the payload, which caused issues since some things like suspend/resume and EC functionality needed to be provided in SMM controlled by coreboot. * This new approach allows EDK2 to read, verify, and potentially write secure boot related variables in an "atomic" manner (using coreboot's SPI driver on the backend?). This solves a problem from the earlier solution where secure boot variables could be changed by an attacker in between EDK2 and coreboot interactions. * [A.I] Benjamin to publish a[ blog post at the 9E blog](https://9elements.com/blog/) about this so that we can review the design in more detail. (DFAD/ETA: unknown, probably after university exams) ### [Martin] Updating website * Privacy Policy * Leadership page * Trademark & logo ### [Martin] Email server * As we agreed previously, the email service remained on Stefan’s server. This includes the mailing list * Stefan, Patrick and myself are admins there. ### [Jon] cbmem updates * Google is pursuing testing of coreboot with Android. As such, we do need to make some changes to coreboot mechanisms to facilitate a slightly different OS. Can we get review on some cbmem changes to add support in sysfs: (https://review.coreboot.org/q/topic:%22cb em-in-sysfs%22) ### [Martin] We can post blogs on the coreboot blog if people are interested in writing things. * Don’t want to make it an advertising area, but we’d like news about devices using coreboot. * Martin can write something about opensil with coreboot after the Phoenix & Turin Proof-of-Concept (Non-production) openSIL releases. # Next Leadership Meeting * March 19, 2025. * [coreboot Calendar](https://coreboot.org/calendar.html). # Notice Decisions shown here are not necessarily final, and are based on the current information available. If there are questions or comments about decisions made, or additional information to present, please put it on the leadership meeting agenda and show up if possible to discuss it. Of course, items may also be discussed on the mailing list, but as it's difficult to interpret tone over email, controversial topics frequently do not have good progress in those discussions. For particularly difficult issues, it may be best to try to schedule another meeting. # coreboot leadership meeting minutes https://docs.google.com/document/d/1NRXqXcLBp5pFkHiJbrLdv3Spqh1Hu086HYkKrgK…

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coreboot Meetings Announcement And Agenda Call
by mina＠coreboot.org 03 Mar '25

03 Mar '25

Dear coreboot Community, Please note that we have an upcoming leadership meeting scheduled for Wednesday, March 5, 2025. [1] Kindly review the agenda and share your thoughts or suggest additional items you would like to discuss during the meeting. [2] Thank you. ## Current Agenda Items ### [Benjamin] Add support for sharing SMM with the payload * To support UEFI secure boot effectively, we need to perform the verify and write steps of its variables together, in SMM. Consequently, we propose a solution where coreboot ‘owns’ SMM (initialises and installs all its regular SMI handlers), and the payload is permitted to install its own SMI handlers within a dedicated SMRAM region that coreboot will call into (and return from) for payload-specific use-cases. While this was developed for EDK2, to support secure boot, note that it’s not UEFI-specific, and contains nothing specific to secure boot. This is a superior solution to one we proposed in 2023, called “Add support for calling SMM payloads.” [1](https://coreboot.org/calendar.html) [2](https://docs.google.com/document/d/1NRXqXcLBp5pFkHiJbrLdv3Spqh1Hu086HYkK…

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coreboot March 2025