coreboot March 2025

coreboot@coreboot.org

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28 discussions

[coreboot - Feature #583] (New) Allow reconfiguring PCIe slots on Asus P8Z77-V
by Keith Hui 19 Apr '25

19 Apr '25

Issue #583 has been reported by Keith Hui. ---------------------------------------- Feature #583: Allow reconfiguring PCIe slots on Asus P8Z77-V https://ticket.coreboot.org/issues/583 * Author: Keith Hui * Status: New * Priority: Normal * Assignee: Keith Hui * Category: board support * Target version: none * Start date: 2024-11-30 * Related links: https://review.coreboot.org/c/coreboot/+/85413 * Affected hardware: mb/asus/p8z77-v ---------------------------------------- Vendor firmware allows configuring the PCIe slots in three different ways, by reallocating 4 of the PCIe lanes between PCIEX16_3, PCIEX1_1, PCIEX1_2, and the onboard ASM1061 serial ATA controller providing 2 additional SATA ports. The options are (devices not shown are disabled): * X4: PCIEX16_3 as x4 * X1: PCIEX16_3 as x1, PCIEX1_1, PCIEX1_2 * Auto: PCIEX16_3 as x1, PCIEX1_1, ASM1061 The technical details have been worked out and implemented as patch CB:85413. However, two issues remain: 1. Despite our best efforts, PCIEX1_2 still doesn't work. 2. Configuring PCIEX16_3 for 4x requires changing a PCH soft strap from firmware, and coreboot lacks infrastructure for doing so. It has been established that the descriptor itself, which contains the soft straps, needs to be reflashed to make this change. This issue tracks our progress implementing this feature. -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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git tag 24.12 (would clobber existing tag)
by Paul Menzel 05 Apr '25

05 Apr '25

Dear coreboot folks, Just a quick question, if there the 24.12 tag was renewed back in December(?). $ LANG= git fetch --tags From ssh://review.coreboot.org:29418/coreboot ! [rejected] 24.12 -> 24.12 (would clobber existing tag) I don’t think, I manually added a tag, but I can’t say for certain, what I did several months ago. Kind regards, Paul [1]: https://doc.coreboot.org/releases/coreboot-24.12-relnotes.html

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coreboot Meetings Announcement And Agenda Call
by mina＠coreboot.org 31 Mar '25

31 Mar '25

Dear coreboot Community, Please be reminded that we have an upcoming leadership meeting scheduled for Wednesday, April 2, 2025. [1] Kindly take a moment to update the agenda with matters you wish to see addressed during the meeting. [2] Thank you. ## Current Agenda Items ### [Martin] What’s going on with the GPL & Cisco? ### [Martin] Discussion about having meetings between companies and coreboot. * We would like to have some regular meetings with companies or other groups where upcoming plans can be discussed. ## Notifications * coreboot 25.03 release is complete. We will do a blog post for it tomorrow. [1](https://coreboot.org/calendar.html) [2](https://docs.google.com/document/d/1NRXqXcLBp5pFkHiJbrLdv3Spqh1Hu086HYkK…

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[coreboot - Support #588] (New) Deguard AssertionError using ./generatedelta.py on Dell Optiplex 5040 SFF (0T7D40) full rom dump
by Walter Sonius 31 Mar '25

31 Mar '25

Issue #588 has been reported by Walter Sonius. ---------------------------------------- Support #588: Deguard AssertionError using ./generatedelta.py on Dell Optiplex 5040 SFF (0T7D40) full rom dump https://ticket.coreboot.org/issues/588 * Author: Walter Sonius * Status: New * Priority: Normal * Category: userspace utilities * Target version: none * Start date: 2025-03-31 ---------------------------------------- Running the deguard `./generatedelta.py` on the flashrom dumped rom from a Dell Optiplex 5040 SFF (0T7D40 A00, Q170 chipset, ME 11.8.92.4222) 1.22 BIOS results in the following AssertionError: ``` ./generatedelta.py --input dell_optiplex_5040_sff_bios122.rom --output data/delta/dell5040sff Traceback (most recent call last): File "/home/neon/deguard/./generatedelta.py", line 55, in <module> mfs = MFS(me.entry_data("MFS")) ^^^^^^^^^^^^^^^^^^^^^^^^^ File "/home/neon/deguard/lib/mfs.py", line 43, in __init__ page = MFSPage(self.data[page * self.PAGE_SIZE:(page + 1) * self.PAGE_SIZE], page) # Load page ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ File "/home/neon/deguard/lib/mfs.py", line 164, in __init__ self.chunks[chunk] = MFSChunk(data, chunk_id) ^^^^^^^^^^^^^^^^^^^^^^^^ File "/home/neon/deguard/lib/mfs.py", line 273, in __init__ assert self.crc == MFS.Crc16(self.data + struct.pack("<H", self.chunk_id)) ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ AssertionError ``` This "AssertionError" can be skipped by using "Filip Lewiński" [filipleple patch](https://codeberg.org/libreboot/deguard/issues/1) on `lib/mfs.py`: ``` - assert self.crc == MFS.Crc16(self.data + struct.pack("<H", self.chunk_id)) + print(f"Chunk ID: {self.chunk_id}, Data: {self.data.hex()[:100]}, Expected CRC: {self.crc}, Calculated CRC: {MFS.Crc16(self.data + struct.pack('<H', self.chunk_id))}") + # assert self.crc == MFS.Crc16(self.data + struct.pack("<H", self.chunk_id)) + if (self.crc != MFS.Crc16(self.data + struct.pack("<H", self.chunk_id))): + print ("Invalid CRC!!!\n") ``` It now lists the following 52 CRC invalid errors, but will create a delta folder structure like the example optiplex 3050 although it misses the `ptt` folder and some other files differ: ``` ./generatedelta.py --input dell_optiplex_5040_sff_bios122.rom --output data/delta/dell5040sff | grep "CRC: 0," Chunk ID: 9662, Data: 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Expected CRC: 0, Calculated CRC: 40051 Chunk ID: 9668, Data: 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Expected CRC: 0, Calculated CRC: 31713 Chunk ID: 9669, Data: 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Expected CRC: 0, Calculated CRC: 18640 Chunk ID: 8173, Data: 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Expected CRC: 0, Calculated CRC: 20614 Chunk ID: 8174, Data: 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Expected CRC: 0, Calculated CRC: 1493 Chunk ID: 8175, Data: 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Expected CRC: 0, Calculated CRC: 14052 Chunk ID: 8176, Data: 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Expected CRC: 0, Calculated CRC: 9641 Chunk ID: 8177, Data: 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Expected CRC: 0, Calculated CRC: 5784 Chunk ID: 8178, Data: 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Expected CRC: 0, Calculated CRC: 17355 Chunk ID: 8179, Data: 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Expected CRC: 0, Calculated CRC: 28922 Chunk ID: 8180, Data: 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Expected CRC: 0, Calculated CRC: 59757 Chunk ID: 8181, Data: 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Expected CRC: 0, Calculated CRC: 55900 Chunk ID: 8182, Data: 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Expected CRC: 0, Calculated CRC: 36623 Chunk ID: 8183, Data: 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Expected CRC: 0, Calculated CRC: 48190 Chunk ID: 8184, Data: 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Expected CRC: 0, Calculated CRC: 44032 Chunk ID: 8185, Data: 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Expected CRC: 0, Calculated CRC: 40753 Chunk ID: 8186, Data: 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Expected CRC: 0, Calculated CRC: 51810 Chunk ID: 8187, Data: 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Expected CRC: 0, Calculated CRC: 63827 Chunk ID: 8188, Data: 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Expected CRC: 0, Calculated CRC: 24772 Chunk ID: 8189, Data: 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Expected CRC: 0, Calculated CRC: 21493 Chunk ID: 8190, Data: 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Expected CRC: 0, Calculated CRC: 1702 Chunk ID: 8191, Data: 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Expected CRC: 0, Calculated CRC: 13719 Chunk ID: 8192, Data: 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Expected CRC: 0, Calculated CRC: 61908 Chunk ID: 8193, Data: 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Expected CRC: 0, Calculated CRC: 49893 Chunk ID: 8194, Data: 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Expected CRC: 0, Calculated CRC: 38838 Chunk ID: 8195, Data: 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Expected CRC: 0, Calculated CRC: 42119 Chunk ID: 8196, Data: 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Expected CRC: 0, Calculated CRC: 15632 Chunk ID: 8197, Data: 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Expected CRC: 0, Calculated CRC: 3617 Chunk ID: 8198, Data: 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Expected CRC: 0, Calculated CRC: 23410 Chunk ID: 8199, Data: 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Expected CRC: 0, Calculated CRC: 26691 Chunk ID: 8200, Data: 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Expected CRC: 0, Calculated CRC: 30845 Chunk ID: 8201, Data: 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Expected CRC: 0, Calculated CRC: 19276 Chunk ID: 8202, Data: 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Expected CRC: 0, Calculated CRC: 7711 Chunk ID: 8203, Data: 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Expected CRC: 0, Calculated CRC: 11566 Chunk ID: 8204, Data: 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Expected CRC: 0, Calculated CRC: 46265 Chunk ID: 8205, Data: 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Expected CRC: 0, Calculated CRC: 34696 Chunk ID: 8206, Data: 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Expected CRC: 0, Calculated CRC: 53979 Chunk ID: 8207, Data: 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Expected CRC: 0, Calculated CRC: 57834 Chunk ID: 8208, Data: 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Expected CRC: 0, Calculated CRC: 62119 Chunk ID: 8209, Data: 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Expected CRC: 0, Calculated CRC: 49558 Chunk ID: 8210, Data: 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Expected CRC: 0, Calculated CRC: 38085 Chunk ID: 8211, Data: 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Expected CRC: 0, Calculated CRC: 42996 Chunk ID: 8212, Data: 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Expected CRC: 0, Calculated CRC: 15971 Chunk ID: 8213, Data: 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Expected CRC: 0, Calculated CRC: 3410 Chunk ID: 8214, Data: 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Expected CRC: 0, Calculated CRC: 22529 Chunk ID: 8215, Data: 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Expected CRC: 0, Calculated CRC: 27440 Chunk ID: 8216, Data: 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Expected CRC: 0, Calculated CRC: 31502 Chunk ID: 10199, Data: 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Expected CRC: 0, Calculated CRC: 3459 Chunk ID: 6000, Data: 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Expected CRC: 0, Calculated CRC: 48953 Chunk ID: 6001, Data: 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Expected CRC: 0, Calculated CRC: 35848 Chunk ID: 6002, Data: 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Expected CRC: 0, Calculated CRC: 55643 Chunk ID: 6003, Data: 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, Expected CRC: 0, Calculated CRC: 60010 ``` A tree view of the new delta folder: ``` data/delta/dell5040sff/ └── home ├── amt │ ├── rtfd │ │ ├── acl │ │ │ ├── tnf0 │ │ │ ├── tnf1 │ │ │ └── tnf2 │ │ ├── amt.wol │ │ ├── hshStr.crt19 │ │ ├── hshStr.crt23 │ │ ├── hshStr.crt24 │ │ ├── hshStr.crt25 │ │ └── hshStr.crt26 │ └── skip_rtfd │ └── uim.policy ├── bup │ ├── bup_sku │ │ ├── emu_fuse_map │ │ ├── fuse_ip_base │ │ └── plat_n_sku │ ├── invokemebx │ └── mbp ├── fwupdate │ ├── fwuavgerase │ ├── fwuavgwrite │ └── fwuoemid ├── gpio │ └── csme_pins ├── icc │ ├── dynregs │ ├── header │ ├── namestr │ ├── prof0 │ ├── prof1 │ ├── prof2 │ ├── prof3 │ ├── prof4 │ ├── prof5 │ └── prof6 ├── mca │ ├── eom │ └── ish_policy ├── mctp │ └── device_ports ├── pavp │ ├── hdcp_ports │ └── lspcon_port ├── policy │ ├── Bist │ │ └── auto_config │ ├── cfgmgr │ │ └── cfg_rules │ ├── hci │ │ ├── sysintid1 │ │ ├── sysintid2 │ │ └── sysintid3 │ └── pwdmgr │ └── segreto └── secureboot ├── bootpolres ├── bootpoltype ├── enfpolicy ├── kmid └── pubkeyhash ``` Diffing this compared to the example delta 3050 folder: ``` diff -bur optiplex_3050 optiplex_5040_sff_strip Binary files optiplex_3050/home/bup/bup_sku/emu_fuse_map and optiplex_5040_sff_strip/home/bup/bup_sku/emu_fuse_map differ Binary files optiplex_3050/home/bup/bup_sku/plat_n_sku and optiplex_5040_sff_strip/home/bup/bup_sku/plat_n_sku differ Only in optiplex_5040_sff_strip/home/bup: invokemebx Binary files optiplex_3050/home/bup/mbp and optiplex_5040_sff_strip/home/bup/mbp differ Binary files optiplex_3050/home/icc/dynregs and optiplex_5040_sff_strip/home/icc/dynregs differ Binary files optiplex_3050/home/icc/prof0 and optiplex_5040_sff_strip/home/icc/prof0 differ Only in optiplex_3050/home/icc: prof10 Only in optiplex_3050/home/icc: prof7 Only in optiplex_3050/home/icc: prof8 Only in optiplex_3050/home/icc: prof9 Only in optiplex_5040_sff_strip/home/policy: Bist Binary files optiplex_3050/home/policy/cfgmgr/cfg_rules and optiplex_5040_sff_strip/home/policy/cfgmgr/cfg_rules differ diff -bur optiplex_3050/home/policy/hci/sysintid1 optiplex_5040_sff_strip/home/policy/hci/sysintid1 --- optiplex_3050/home/policy/hci/sysintid1 2025-03-31 15:36:47.220784635 +0200 +++ optiplex_5040_sff_strip/home/policy/hci/sysintid1 2025-03-31 16:01:29.335254012 +0200 @@ -1 +1 @@ -�n$� \ No newline at end of file +_�� \ No newline at end of file diff -bur optiplex_3050/home/policy/hci/sysintid2 optiplex_5040_sff_strip/home/policy/hci/sysintid2 --- optiplex_3050/home/policy/hci/sysintid2 2025-03-31 15:36:47.220784635 +0200 +++ optiplex_5040_sff_strip/home/policy/hci/sysintid2 2025-03-31 16:01:29.335254012 +0200 @@ -1 +1 @@ -��t` \ No newline at end of file +�� \ No newline at end of file diff -bur optiplex_3050/home/policy/hci/sysintid3 optiplex_5040_sff_strip/home/policy/hci/sysintid3 --- optiplex_3050/home/policy/hci/sysintid3 2025-03-31 15:36:47.220784635 +0200 +++ optiplex_5040_sff_strip/home/policy/hci/sysintid3 2025-03-31 16:01:29.335254012 +0200 @@ -1 +1 @@ -Ȯ� \ No newline at end of file +�a< \ No newline at end of file diff -bur optiplex_3050/home/policy/pwdmgr/segreto optiplex_5040_sff_strip/home/policy/pwdmgr/segreto --- optiplex_3050/home/policy/pwdmgr/segreto 2025-03-31 15:36:47.221784637 +0200 +++ optiplex_5040_sff_strip/home/policy/pwdmgr/segreto 2025-03-31 16:01:29.335254012 +0200 @@ -1 +1 @@ -��к \ No newline at end of file +�"�H \ No newline at end of file ``` After deleting (strip) the `secureboot` and `amt,fwupd,pavp` folders it will generate a 2M consumer ME image when using `finalimage.py`. `./finalimage.py --delta data/delta/dell5040sff --version 11.6.0.1126 -pch H --sku 2M --fake-fpfs data/fpfs/zero --input external/asrock_h110_me_11.6.0.1126.bin --output 5040sff_patched_me.bin` When enabling the HAP bit on the original IFD and replacing the ME with the downgraded and deguarded ME should complete the manual. Is it correct to replace the current corporate ME firmware around ~7MB from the original image with this 2MB donor consumer variant, will it be similar like the Optiplex 3050 from the example or should I find a older vulnerable corporate ME firmware? Which file(s) of this dump may I distribute / upload to this ticket license wise to improve debugging? Using the service mode jumper on this Dell Optiplex 5040 SFF I was able to fully read and write the whole firmware even the ME regions (checksum checked it). Anyone else experience or success using a 'ch341a_spi' or 'raspberry spi' doing in-situ flash recover on this particular Dell or similar in case I need it? https://www.dell.com/support/product-details/en-uk/product/optiplex-5040-sf… -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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Q on flashing IFD from within coreboot (IVB boards)
by Keith Hui 30 Mar '25

30 Mar '25

I have narrowed the IFD update logic to one UEFI module within vendor BIOS: PcieLaneDxe, and after running Ghidra on it, I have learned enough to start implementing it on coreboot. All is in pursuit of this: https://review.coreboot.org/c/coreboot/+/85413 It will also help with the recently upstream p8z77-v_le_plus, and Sabertooth Z77. Turns out vendor is also just reflashing the IFD after configuring some GPIOs on the board. They don't seem concerned about SPI controller freezing. My code is going to look like this: 8<------ static enum cb_err reprogram_ifd(u8 new_pciepcs1) { const unsigned int PCHSTRP9 = 0x124; u16 lvscc = RCBA16(0x38c4); const unsigned int lbes_map[] = { 256, 4 * KiB, 8 * KiB, 64 * KiB }; u8 * ifdbuf; u8 erase_opcode = (lvscc >> 8) & 0xff; unsigned int erase_size = lbes_map[lvscc & 0b11]; unsigned int i; ifdbuf = malloc(erase_size); /* Read */ memcpy(ifdbuf, (void *) 0xff800000, erase_size); /* Patch */ ifdbuf[PCHSTRP9] &= 0b11111100; ifdbuf[PCHSTRP9] |= (pciepcs1 & 0b11); /* Erase */ /* Write */ for (i = 0; i < erase_size; i+=64) { if (is_write_needed (ifdbuf+i, 64) { /* Write all 64 bytes if anything within isn't 0xff */ } } free(ifdbuf); return CB_SUCCESS; } 8<------ Q1: So far all boards in the Asus p8x7x-series family that need this use 8MiB SPI flash, so they're mapped to 0xff800000 when run as 32-bit. What is the right address to use when coreboot is compiled as 64-bit? Would I have to do "max int - 8 MiB"? Q2: I may have asked this before. Can I use SPI_FLASH Kconfig and the SPI flash driver? Can I use this without a FMD file? Or am I better off rolling my own again? Thanks Keith

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[coreboot - Support #581] (New) success new variant "compaq_pro_6300_sff" for hp/snb_ivb_desktops compatible with "compaq_8300_elite_sff" template
by Walter Sonius 29 Mar '25

29 Mar '25

Issue #581 has been reported by Walter Sonius. ---------------------------------------- Support #581: success new variant "compaq_pro_6300_sff" for hp/snb_ivb_desktops compatible with "compaq_8300_elite_sff" template https://ticket.coreboot.org/issues/581 * Author: Walter Sonius * Status: New * Priority: Normal * Category: board support * Target version: none * Start date: 2025-03-15 ---------------------------------------- Successful flash and coreboot SeaBIOS functioning of a HP "compaq_pro_6300_sff" with a unchanged "compaq_8300_elite_sff" template using coreboot (24.12-758-g1e7ba810c6bb) and SeaBIOS (version rel-1.16.3-0-ga6ed6b70). These two HP Compaq devices are extremely similar, they use the same OEM proprietary BIOS upgrade files. Hardware wise the only 3 noticeable differences are that the "compaq_8300_elite_sff" comes with a Q77 chipset, SuperIO NPCD378 and J32 labeled 16x length "white" PCI-E slot versus a Q75 chipset, SuperIO NPCD379HAKFX with the J32 labeled slot populated with a limited physical 1x length "black" PCI-E slot on the "compaq_pro_6300_sff". Flashing from OEM proprietary BIOS 3.08revA enabling the FDO jumper on the motherboard as described for the compaq_8300_elite_sff works by booting with "iomem=relaxed" kernel parameter and specifying the specific 16MB chip 25Q128A: flashrom -p internal -w cbtest.rom -c "MT25QL128" Tested and Working: Poweron/Poweroff/Reboot CPU i3-3220 / e3-1225v2 RAM 1x 2x 4x populated slots total of 4GB/8GB/16GB/24GB (both 1.35v and 1.5v modules mixed with ECC) Serial port (including coreboot) PS2 keyboard (including SeaBIOS) PS2 mouse SATA 3 ports (blue/white/white) USB 2.0 4x front & 2x back ports USB 3.0 4x back ports Ethernet 1Gbit/100Mbit Display port works in SeaBIOS and OS VGA port only works in OS! PCI using realtek RTL8169 1Gb PCIE 3.0 16x using 2.0 8x 10Gb intel X540-AT2 / using 1.0 16x Nvidia Geforce 6200 LE (also works in SeaBIOS) PCIE 2.0 1x using 2.0 1x 2.5Gb realtek RTL8125 PCIE 2.0 1x using 1.0 1x 1Gb intel 82574L (SeaBIOS loads option rom) Audio built-in speaker (plays music in OS compared to legacy bleep pc-speaker) Audio front panel 3.5 mm headphone jack (auto disables built-in Speakers and selects Headphones) Audio front panel 3.5 mm headphone&mic jack (only microphone works with 4 pin 3.5mm combi mic/headphone) Audio back panel 3.5mm green jack (manually select Line Out and it works) Sensors CPU and 2 motherboard sensors SuperIO Booting USB / SATA(HDD/DVD) OS: Fedora-mate Linux kernel 6.11.4 / 6.13.6, KDE neon Linux kernel 6.8.0-52 Flashrom: needs additional parameters compared to OEM BIOS both for read/write depending on flashrom version? flashrom -p internal:boardmismatch=force,ich_spi_mode=hwseq -w test.rom -c "Opague flash chip" Tested not Working: RAM ECC functioning (see coreboot log) SATA port black Wakeonlan, it just auto wakes from itself so cannot verify... iGPU multigpu with PCIE nvidia geforce 6200 le, only PCIE nvidia geforce works and iGPU gets disabled. What to do next to get this "compaq_pro_6300_sff" variant officially supported? *Supply more logs/info? *Fill a bug for the ECC not working or first get this variant supported as is? *Fill a bug that VGA doesn't work in SeaBIOS? *Fill a bug/ticket on the flashrom support list for the difference in parameters needed pre/post flash? https://support.hp.com/us-en/drivers/hp-compaq-pro-6300-small-form-factor-p… https://support.hp.com/in-en/drivers/hp-compaq-elite-8300-small-form-factor… Walter Sonius ---Files-------------------------------- cb-log-hp-compaq_pro_6300_sff.txt (51.8 KB) -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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[coreboot - Support #585] (New) acpi MSDM / SLIC table usage?
by Walter Sonius 29 Mar '25

29 Mar '25

Issue #585 has been reported by Walter Sonius. ---------------------------------------- Support #585: acpi MSDM / SLIC table usage? https://ticket.coreboot.org/issues/585 * Author: Walter Sonius * Status: New * Priority: Normal * Category: Documentation * Target version: none * Start date: 2025-03-20 * Affected OS: Windows 8 Pro / Windows 10 Pro ---------------------------------------- What option(s) does one need to compile this feature into a coreboot & edk2 build and where does one put the `slic_file` and in what format? Couldn't find anything in the documentation nor the commits that introduce MSDM/SLIC support: https://review.coreboot.org/c/coreboot/+/44995 https://review.coreboot.org/c/coreboot/+/7202 -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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[coreboot - Bug #569] (New) coreinfo: i386-elf-gcc-ar: Cannot find binary 'i386-elf-ar'
by Matthias Brugger 28 Mar '25

28 Mar '25

Issue #569 has been reported by Matthias Brugger. ---------------------------------------- Bug #569: coreinfo: i386-elf-gcc-ar: Cannot find binary 'i386-elf-ar' https://ticket.coreboot.org/issues/569 * Author: Matthias Brugger * Status: New * Priority: Normal * Target version: none * Start date: 2024-11-14 * Affected versions: master * Related links: https://doc.coreboot.org/tutorial/part1.html ---------------------------------------- Hi, when trying to compile the qemu example with latest branch, I get the following error: ``` ~/src/coreboot/$ make -C payloads/coreinfo/ Makefile:358: warning: overriding recipe for target '/home/mbrugger/src/coreboot/payloads/coreinfo/libpayload/arch/x86/exec.libc.o' Makefile:358: warning: ignoring old recipe for target '/home/mbrugger/src/coreboot/payloads/coreinfo/libpayload/arch/x86/exec.libc.o' AR /home/mbrugger/src/coreboot/payloads/coreinfo/libpayload/libpci.a /home/mbrugger/src/coreboot/payloads/libpayload/../../util/crossgcc/xgcc/bin/i386-elf-gcc-ar: Cannot find binary 'i386-elf-ar' make[1]: *** [Makefile.mk:116: /home/mbrugger/src/coreboot/payloads/coreinfo/libpayload/libpci.a] Error 1 make: *** [../libpayload/Makefile.payload:153: /home/mbrugger/src/coreboot/payloads/coreinfo/libpayload/libpayload.a] Error 2 ``` I double checked and ./util/crossgcc/xgcc/bin/i386-elf-ar exists. I suppose it's a problem in the cross compilation of i386-elf-gcc-ar -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

2 3

coreboot Meetings Announcement And Agenda Call
by mina＠coreboot.org 28 Mar '25

28 Mar '25

Dear coreboot Community, Kindly note that we have an upcoming leadership meeting scheduled for Wednesday, April 2, 2025. [1] Please take a moment to update the agenda with matters you wish to see addressed during the meeting. [2] Thank you. Best regards, Mina Asante. [1](https://coreboot.org/calendar.html) [2](https://docs.google.com/document/d/1NRXqXcLBp5pFkHiJbrLdv3Spqh1Hu086HYkK…

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[coreboot - Bug #507] (Closed) Windows GPU driver fails to load on AMD based google/guybrush, google/skyrim boards
by Matt DeVillier 27 Mar '25

27 Mar '25

Issue #507 has been updated by Matt DeVillier. Status changed from New to Closed This isn't an issue when not using vboot/PSP verstage, so closing for now. ---------------------------------------- Bug #507: Windows GPU driver fails to load on AMD based google/guybrush, google/skyrim boards https://ticket.coreboot.org/issues/507#change-2049 * Author: Matt DeVillier * Status: Closed * Priority: Normal * Target version: none * Start date: 2023-08-30 * Affected versions: 4.15, 4.16, 4.17, 4.18, 4.19, 4.21, main * Affected hardware: google/guybrush, google/skyrim ---------------------------------------- The Windows GPU drivers on AMD Cezanne and Mendocino platform ChromeOS devices (google guybrush and skyrim boards respectively) fail to load due to the PSP boot mode being `Development` vs `Production.` On these platforms, the PSP only boots in `Production` mode when ChromeOS verified boot mode is active. Possible solutions include having the PSP boot in `Production` mode when vboot is not used at all, when CONFIG_CHROMEOS is not set, or (always) when PSP signed verstage is used. Any of these require changes to the PSP firmware from AMD. -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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2002

coreboot March 2025