coreboot July 2024

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20 discussions

[coreboot - Bug #548] (New) Computer Fails To Recognize Upgraded WiFi Card
by Jeremy Brown 19 Oct '24

19 Oct '24

Issue #548 has been reported by Jeremy Brown. ---------------------------------------- Bug #548: Computer Fails To Recognize Upgraded WiFi Card https://ticket.coreboot.org/issues/548 * Author: Jeremy Brown * Status: New * Priority: Normal * Target version: none * Start date: 2024-07-15 ---------------------------------------- I am running coreboot 24.05 on my Lenovo X201. I decided to upgrade my WiFi card from an Intel Centrino Advanced-N 6205 to an Intel Wireless-AC 7260; since I selected the option to support Intel PCIe cards in my build config I expected everything to work but my computer fails to recognize the new card. The old card is still recognized if I reinstall it so I know I didn't mess up the socket somehow; I've read reports of the 7260 [working with a modded factory BIOS](https://richbits.rbarnes.org/installing-the-intel-7260-in-the-thinkpa… so I don't think there's an electrical issue. I've attached lspci data from both chips, lmk if additional information is needed. ---Files-------------------------------- 6205_lspci_tree.txt (1.63 KB) 7260_lspci_tree.txt (1.57 KB) 6205_lspci.txt (12.8 KB) 7260_lspci.txt (12.2 KB) -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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Gerrit Gitiles is back - for now
by Felix Singer 20 Sep '24

20 Sep '24

I've just enabled Gitiles again. We will observe which effect this has on Gerrit now. Fingers crossing that it won't cause a high load anymore :) Felix

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Announcement: Introducing UEFI Capsule Update Integration for coreboot with EDK II
by Beata Skierka 18 Sep '24

18 Sep '24

Hello, We are pleased to announce the launch of a project by 3mdeb aimed at integrating UEFI Capsule Update for coreboot with EDK II as a payload. This initiative aims to bring the capsule-based update method, providing an alternative to the traditional flashrom-based method, which becomes more and more difficult to implement, due to the restricted OS-level access to the firmware storage. One of the main goals is also to ease the integration and firmware update deployments via the fwupd for devices running open-source firmware (based on coreboot + EDK II). For a detailed project outline, please visit our Dasharo documentation [1]. We are looking for feedback through comments on this thread or via the built-in discussion module on the website. Although the project plan has been already accepted by the NLnet Foundation, there may be still some room for justified changes. You can track project's progress via the GitHub Project [2]. Your feedback and participation would be much appreciated. We welcome your involvement in discussions, reviewing, and testing. You might already have seen some first patches as a results of this project getting started, such us: - https://review.coreboot.org/c/coreboot/+/82247 - https://review.coreboot.org/c/coreboot/+/82248 - https://review.coreboot.org/c/coreboot/+/82249 - https://review.coreboot.org/c/coreboot/+/82610 We acknowledge and appreciate the funding support from the NLnet Foundation. [1] https://docs.dasharo.com/projects/capsule-updates/ [2] https://github.com/orgs/Dasharo/projects/7/views/1 Best regards, Beata Skierka Project Manager https://3mdeb.com | @3mdeb_com

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[coreboot - Bug #549] (New) coreboot 24.05: SeaBIOS Windows 10/11 BSOD "ACPI BIOS ERROR" (Thinkpad W530)
by Simon Dominic 23 Aug '24

23 Aug '24

Issue #549 has been reported by Simon Dominic. ---------------------------------------- Bug #549: coreboot 24.05: SeaBIOS Windows 10/11 BSOD "ACPI BIOS ERROR" (Thinkpad W530) https://ticket.coreboot.org/issues/549 * Author: Simon Dominic * Status: New * Priority: Normal * Category: board support * Target version: master * Start date: 2024-07-31 * Affected versions: master * Affected hardware: Lenovo ThinkPad W530 * Affected OS: Windows 10/11 ---------------------------------------- When using the latest coreboot (i.e. using command `git clone https://review.coreboot.org/coreboot`), which is currently 24.05, to build a rom for Thinkpad W530, I get BSOD with "ACPI BIOS ERROR" when trying to boot into Windows 10 or 11 from SeaBIOS. Even just booting from a Windows install usb will show this error. This is even with incorporating the vga bios files (so i can external displays to work) - see my defconfig. Did consider using EDK2 apparently Windows support is pretty solid, but could never make a successful build - not that `make` command had errors, but once flashing, would just having white underscore and have to recover with external flashing. A separate issue to write about in and of itself, but I prefer SeaBIOS so I'll be sticking with that. I am quite new to coreboot - using for only about 2-3 months now. Let me know if there is further information I should provide. ---Files-------------------------------- defconfig (590 Bytes) w530_bsod.jpg (1.98 MB) -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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[coreboot - Bug #536] (New) Cannot build coreboot-sdk
by Michał Żygowski 22 Aug '24

22 Aug '24

Issue #536 has been reported by Michał Żygowski. ---------------------------------------- Bug #536: Cannot build coreboot-sdk https://ticket.coreboot.org/issues/536 * Author: Michał Żygowski * Status: New * Priority: Normal * Assignee: Martin Roth * Target version: none * Start date: 2024-04-24 ---------------------------------------- I have just tried building coreboot-sdk from scratch and could not get past the step of installing the required packages. Found out that diffutils dependency on libcurl4t64 break libcurl4 (change apt-get to apt to see verbose information message like below): ``` shell > [coreboot-sdk 2/4] RUN useradd -p locked -m coreboot && apt-get -qq update && apt -qqy install --no-install-recommends bash-completion bc bison bsdextrautils bzip2 ca-certificates ccache cmake cscope curl device-tree-compiler dh-autoreconf diffutils exuberant-ctags flex g++ gawk gcc git gnat-13 golang graphicsmagick-imagemagick-compat graphviz lcov less libcapture-tiny-perl libcrypto++-dev libcurl4 libcurl4-openssl-dev libdatetime-perl libelf-dev libfreetype-dev libftdi1-dev libglib2.0-dev libgmp-dev libgpiod-dev libjaylink-dev liblzma-dev libnss3-dev libncurses-dev libpci-dev libreadline-dev libssl-dev libtimedate-perl libusb-1.0-0-dev libxml2-dev libyaml-dev m4 make meson msitools neovim ninja-build openssh-client openssl parted patch pbzip2 pkg-config python3 python-is-python3 qemu-system-arm qemu-system-misc qemu-system-ppc qemu-system-x86 rsync sharutils shellcheck unifont unzip uuid-dev vim-common wget xz-utils zlib1g-dev && apt-get clean: 2.106 2.106 WARNING: apt does not have a stable CLI interface. Use with caution in scripts. 2.106 2.841 diffutils is already the newest version (1:3.10-1). 2.841 diffutils set to manually installed. 2.841 Some packages could not be installed. This may mean that you have 2.841 requested an impossible situation or if you are using the unstable 2.841 distribution that some required packages have not yet been created 2.841 or been moved out of Incoming. 2.841 The following information may help to resolve the situation: 2.841 2.841 Unsatisfied dependencies: 3.001 libcurl4t64 : Breaks: libcurl4 (< 8.7.1-3) 3.004 Error: Unable to correct problems, you have held broken packages. ``` Changing libcurl4 to libcurl4t64 allows the docker to continue the build process of coreboot-sdk. But is this the right thing to do? -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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[coreboot - Feature #420] (New) Use standard format of TPM event log
by Krystian Hebel 07 Aug '24

07 Aug '24

Issue #420 has been reported by Krystian Hebel. ---------------------------------------- Feature #420: Use standard format of TPM event log https://ticket.coreboot.org/issues/420 * Author: Krystian Hebel * Status: New * Priority: Normal * Target version: none * Start date: 2022-10-12 * Related links: [1] https://trustedcomputinggroup.org/wp-content/uploads/TCG_PCClientImplementa… [2] https://trustedcomputinggroup.org/wp-content/uploads/TCG_PCClient_PFP_r1p05… ---------------------------------------- Currently coreboot uses proprietary format for TPM event log. TCG has standardized log formats, differently for TPM1.2 (aka legacy or SHA1) [1] and TPM2.0 (aka crypto agile) [2], both of which can be parsed by Linux kernel and exposed in sysfs. I don't know of any tool outside of cbmem which can parse coreboot format; this includes payloads which may be interested in continuing chain of trust started by coreboot. Another incompatibility is caused by vboot's assignment of PCRs. Roles of PCRs are roughly specified by TCG in both of mentioned documents, they are more or less compatible with each other, but not with current coreboot code. These changes could break assumptions made by existing platforms, so they should be made as Kconfig options. This is a tracking issue to collect subtasks that need to be done in order to support standard event log formats. -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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Re: RW_MRC_CACHE always displays needs update and boot time is more
by Moorthi M.s 31 Jul '24

31 Jul '24

Hi Paul, > > Thanks for your reply. > > I figured out the issue. > > The ME CPU replayed option is printing as YES, and this forces the MRC > training on each reset. > > Updated the ME firmware, and the issue was solved. > > Regards, > Moorthi S > On Wed, Jul 31, 2024, 12:02 Paul Menzel <pmenzel(a)molgen.mpg.de> wrote: > >> Dear Moorthi, >> >> >> Welcome to coreboot. >> >> Am 31.07.24 um 07:45 schrieb Moorthi M.s: >> >> > I am developing coreboot (ver 4.17) along with UEFI payload for a custom >> > board derived from CFL H RVP11 CRB. >> > >> > I included the CACHE_MRC_SETTINGS to reduce the boot time on subsequent >> > power on. >> > >> > But the time was not reducing and on every power on, around 18 seconds >> are >> > taking between post code 0x92 (Ram Init) and 0x98 (Ram Init Exit). And >> > always prints as " MRC: cache data 'RW_MRC_CACHE' needs update". >> > >> > Because of this coreboot takes around 45 secs to boot. >> > >> > Why every time the MRC cache data is changing? Why the processor is not >> > using the MRC cached data? >> >> Without knowing the code you are using, nobody knows. Did you dump the >> cache data to compare? >> >> > Is there any other configurations needs to be done? >> Unfortunately, you did not provide enough information to answer your >> question. Please provide at least your configuration and the verbose >> logs. Best would be to upload your code (and the schematics). >> >> Also, why do you use coreboot 4.17? 24.05 is the latest release. >> >> >> Kind regards, >> >> Paul >> >> >> PS: Just to mention it, there are coreboot consultants [1], that might >> save you some time in the end. >> >> >> [1]: https://coreboot.org/consulting.html >> >

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RW_MRC_CACHE always displays needs update and boot time is more
by Moorthi M.s 31 Jul '24

31 Jul '24

Hi, I am developing coreboot (ver 4.17) along with UEFI payload for a custom board derived from CFL H RVP11 CRB. I included the CACHE_MRC_SETTINGS to reduce the boot time on subsequent power on. But the time was not reducing and on every power on, around 18 seconds are taking between post code 0x92 (Ram Init) and 0x98 (Ram Init Exit). And always prints as " MRC: cache data 'RW_MRC_CACHE' needs update". Because of this coreboot takes around 45 secs to boot. Why everytime the MRC cache data is changing? Why the processor is not using the MRC cached data? Is there any other configurations needs to be done? Regards, Moorthi S

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New extra-selectors mechanism on superiotool
by Maxim Polyakov 26 Jul '24

26 Jul '24

Hello community! I am adding support for f81866 and f81966 fintek chips in superiotool: https://review.coreboot.org/q/topic:%22fintek%22 However, there are some difficulties to make a dump of the registers of these chips. Their global LDN0 and HWM registers contain fields that switch the register banks of these devices. At the same time, these registers contain fields that should not change after they are configured. For example, <Port Select Register - Index 27h> register contains: BANK_PROG_SEL field[3-2] - Bank select for configuration registers (bank 0/1/2/3) and PORT_4E_EN[4] - 0: The configuration register port is 2E/2F. 1: The configuration register port is 4E/4F. I suggest introducing a new element in chip configuration for such registers - an extra selector: https://review.coreboot.org/c/coreboot/+/83196 It seems to me that this is the optimal solution. This allows superiotool to configure the register fields to select a bank before making a correct dump for the corresponding LDN in automatic mode. Please review. Thx // Regards, // Max

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2024-07-24 - coreboot Leadership Meeting Minutes
by mina＠coreboot.org 25 Jul '24

25 Jul '24

# 2024-07-24 - coreboot Leadership Meeting ## Attendees Martin Roth, Felix Singer, Felix Held, David Hendricks, Marshall Dawson, Maximilian Brune, Lean Sheng Tan, Nico Huber, Matt DeVillier, Werner Zeh, Paule Panter, Ron Minnich, Julius Werner, Jason Glenesk, Mina Asante. ## Announcements & Events * FOSSY conference: August 1-4 2024 in Portland, Oregon, USA https://sfconservancy.org/fossy * COSCUP - Taipei, Taiwan on 2024/08/03 ~ 2024/08/04 https://coscup.org/2024/en/landing * OSFC will be in Bochum Germany - September 3-5 https://www.osfc.io * OCP Global Summit: San Jose, California on October 15–17, 2024 https://www.opencompute.org/summit/global-summit ## Open Action Items * 2024-05-01 * Nick Van Der Harst volunteered for Dutch. "gogo gogo" would like to translate to Russian (?) * 2024-03-20 * Martin:To Add a note to the gerrit guidelines to email the leadership for further discussion and guidance when code submissions are not up to standard. * 2024-03-06 * Martin: To update gerrit contributing guidelines documentation. (https://doc.coreboot.org/contributing/index.html) * 2024-01-10 * Nico: [https://review.coreboot.org/q/topic:enforce_region_api] * Daniel: Look at how we want to localize (non console) strings for coreboot. Long term project. ## Minutes ### [Elyes] Submodules * chromeec and opensbi are a pain (#83466 and #83464 ) Not only they have not been updated for more than two years, they can block future improvements (as testing & prepare for C23 see (https://qa.coreboot.org/job/coreboot-toolchain/1646/testReport/junit/(root)… CV_RV64_/) ) * [Martin] I did a little work towards this a while back, looking at fixing chromeec by turning it from a submodule into something more like what we do for payloads. This would let different mainboards specify different versions. Unfortunately, this makes the CI very difficult, as one platform could check out a different version as another platform is building it. I’d suggest we just abandon chromeec from the build completely. Even Google never used it as a part of the coreboot build. * Julius mentioned that there was recently a discussion inside google about using the shared header. * Martin: The chromeEC submodule is huge and in my opinion we should just continue copying the single header file. * Decision: Drop ChromeEC submodule from coreboot. * [Max] regarding OpenSBI: The pain point is mostly src/arch/riscv/opensbi.c since it includes the sbi/fw-dynamic.h from the opensbi repo. I feel the pain since I have had trouble with it in the past too. There are 3 solutions I can think of. 1. We remove it and merge [https://review.coreboot.org/c/coreboot/+/83284] I will try to merge it anyway, since vendors tend to fork OpenSBI rather than upstreaming it. 2. We rewrite src/arch/riscv/opensbi.c to not include the opensbi header. Shouldn’t be too hard to add the structs and types that we need ourselfs. 3. We remove it and implement our own SBI implementation (very unlikely) * Ron (mostly) revived the SBI functionality from 10 years ago. The idea to remove the openSBI header is a good one. * Max - there are only a couple of structures we need. Will prepare a patch this week. ### [Elyes] prepare for experimental and incomplete C23 * If we opt to test and prepare for C23, and if we have to choose one functionality, would it be the use of nullptr constante and nullptr_t type ? (N3042) see [https://review.coreboot.org/c/coreboot/+/83459/8] Is that the right way? * One more question: If you have to choose only one “thing” that would improve the coreboot code (ISO C11 / 17) what would it be? * [Max] As a side note: If we use C23 I would like to make use of some of its features in coreboot code in general. For example using the “#embed” for our unit tests and using a separation to write long memory addresses (e.g. write 0xFFFF_FFFF instead of 0xFFFFFFFF) * Julius: I’d advocate we don’t do this - this is something brought in from c++ to address things that aren’t generally applicable to coreboot. It’d be very intrusive. * Ron: Unless there’s some benefit that we don’t currently see, what’s the point? * Julius: There’s no objection to using C23 in general, but the nullptr_t type doesn’t gain us anything. Max++ * Decision: Not looking to pursue this currently. ### [Sheng] RFC for UPL support patch by Max *[https://review.coreboot.org/c/coreboot/+/76591] * Please review. * Matt: Some of the names could be improved. * Martin: Let’s put this discussion off until next week - I’ll make sure that it’s in the list of patches to review. * UPL Spec is in github - please contribute. * [https://universalpayload.github.io/spec] * U-boot support: [https://patchwork.ozlabs.org/project/uboot/list/?series=416058] * Edk2 as well. Linuxboot will follow after ### [Nico] Flashprog releases and HW support * Flashprog does regular releases now. Is it ok to announce them on the coreboot ML (about every 3~4 months)? Just checking if anybody has feelings against it… * Probably a little more delicate: What to do about stale "Flashrom support" lines in docs and board_info.txt where it's known broken? remove? replace w/ Flashprog? do nothing? * Martin: Let’s add a line for flashprog support. If flashrom is broken on a platform mark it as no. * David: Do we want to create a CSV list for flash programs instead of separated lines? * Martin: this seems reasonable to me. * Nico: We’d need to update the various scripts to generate the website and lint the file. Nico can take a look at this. * Matt: Sure, we can even add non-open firmware flash packages. # Next Leadership Meeting * August 7,2024. * [coreboot Calendar](https://coreboot.org/calendar.html). # Notice * Decisions shown here are not necessarily final, and are based on the current information available. If there are questions or comments about decisions made, or additional information to present, please put it on the leadership meeting agenda and show up if possible to discuss it. Of course items may also be discussed on the mailing list, but as it's difficult to interpret tone over email, controversial topics frequently do not have good progress in those discussions. For particularly difficult issues, it may be best to try to schedule another meeting. # coreboot leadership meeting minutes [2024-07-24](https://docs.google.com/document/d/1NRXqXcLBp5pFkHiJbrLdv3Spqh1…

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coreboot July 2024