coreboot August 2023

coreboot@coreboot.org

23 participants
41 discussions

[coreboot - Feature #213] Have the bug tracker report activity to the mailing list
by Patrick Georgi 21 Aug '23

21 Aug '23

Issue #213 has been updated by Patrick Georgi. Related links updated Removed IRC as a target given the chaos we have around chat channels right now with libera.chat and matrix decoupling. Meanwhile, mailing list receives ticket updates ---------------------------------------- Feature #213: Have the bug tracker report activity to the mailing list https://ticket.coreboot.org/issues/213#change-1639 * Author: Patrick Georgi * Status: Resolved * Priority: Normal * Assignee: Patrick Georgi * Category: infrastructure * Start date: 2019-06-05 ---------------------------------------- This helps make the tracker more visible and therefore useful -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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[coreboot - Feature #213] (Resolved) Have the bug tracker report activity to the mailing list
by Patrick Georgi 21 Aug '23

21 Aug '23

Issue #213 has been updated by Patrick Georgi. Subject changed from Have the bug tracker report activity to IRC and the mailing list to Have the bug tracker report activity to the mailing list Status changed from New to Resolved Related links updated ---------------------------------------- Feature #213: Have the bug tracker report activity to the mailing list https://ticket.coreboot.org/issues/213#change-1638 * Author: Patrick Georgi * Status: Resolved * Priority: Normal * Assignee: Patrick Georgi * Category: infrastructure * Start date: 2019-06-05 * Related links: Removed IRC as a target given the chaos we have around chat channels right now with libera.chat and matrix decoupling. ---------------------------------------- This helps make the tracker more visible and therefore useful -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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[coreboot - Bug #309] crossgcc: Handle missing tarballs in download step
by Patrick Georgi 18 Aug '23

18 Aug '23

Issue #309 has been updated by Patrick Georgi. Assignee set to Felix Singer ---------------------------------------- Bug #309: crossgcc: Handle missing tarballs in download step https://ticket.coreboot.org/issues/309#change-1634 * Author: Patrick Georgi * Status: New * Priority: Normal * Assignee: Felix Singer * Start date: 2021-05-29 ---------------------------------------- We keep a copy of the tarballs used by crossgcc in coreboot releases in https://coreboot.org/releases/crossgcc-sources/, so we should fall back if a download failed. -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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[PATCH v2 00/20] x86: efi: Fixes and improvements for coreboot
by Simon Glass 18 Aug '23

18 Aug '23

This little series fixes various bugs and annoyances in coreboot and coreboot64. With this both coreboot and coreboot64 start up and work reasonably well on Brya (x86 Chromebook) and U-Boot can boot common Linux distros. - Make coreboot64 debug UART start reliably - Avoid the long USB-init delay on startup - Correct the timer speed on coreboo64 - Fix a bootstd cros bug (will likely be squashed into another patch) - Fix the terribly slow console scrolling With v2 I have also brought in some lost x86 patches so they are all in one series. Changes in v2: - Update the malloc size too - Add new patch - Add new patch - Add new patch - Add new patch - Add new patch - Add new patch - Add new patch - Add new patch - Add new patch - Add new patch Simon Glass (20): x86: coreboot: Add IDE and SATA x86: coreboot: Enable standard boot x86: coreboot: Rearrange arch_cpu_init() x86: Set the CPU vendor in SPL x86: Allow APCI in SPL x86: coreboot: Look for DBG2 UART in SPL too x86: coreboot: Enable CONFIG_SYS_NS16550_MEM32 x86: coreboot: Drop USB init on startup x86: coreboot: Align options between coreboot and coreboot64 x86: coreboot: Enable VIDEO_COPY efi: x86: Correct the condition for installing ACPI tables x86: smbios: Add a Kconfig indicating SMBIOS-table presence x86: Record the position of the SMBIOS tables efi: x86: Use the installed SMBIOS tables efi: x86: Install the SMBIOS tables if present x86: coreboot: Record the position of the SMBIOS tables x86: doc: Move into its own directory x86: doc: Update summaries and add links x86: doc: Split out manual booting into its own file x86: doc: coreboot: Mention 64-bit Linux distros arch/x86/cpu/coreboot/coreboot.c | 16 +- arch/x86/cpu/x86_64/cpu.c | 7 + arch/x86/dts/coreboot.dts | 1 + arch/x86/include/asm/global_data.h | 1 + arch/x86/lib/coreboot/cb_sysinfo.c | 1 + arch/x86/lib/tables.c | 3 + configs/coreboot64_defconfig | 25 +-- configs/coreboot_defconfig | 21 +- doc/arch/index.rst | 2 +- doc/arch/x86/index.rst | 12 ++ doc/arch/x86/manual_boot.rst | 276 +++++++++++++++++++++++++++ doc/arch/{ => x86}/x86.rst | 295 ++--------------------------- doc/board/coreboot/coreboot.rst | 38 +++- drivers/serial/Kconfig | 2 +- drivers/video/coreboot.c | 12 ++ include/asm-generic/global_data.h | 8 + lib/Kconfig | 20 +- lib/efi_loader/Makefile | 4 +- lib/efi_loader/efi_setup.c | 20 +- lib/efi_loader/efi_smbios.c | 37 +--- 20 files changed, 447 insertions(+), 354 deletions(-) create mode 100644 doc/arch/x86/index.rst create mode 100644 doc/arch/x86/manual_boot.rst rename doc/arch/{ => x86}/x86.rst (64%) -- 2.42.0.rc1.204.g551eb34607-goog

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Add ACPI PLD to new GFX (igpu) devices for Brya models
by Won Chung 17 Aug '23

17 Aug '23

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Trouble booting with mt8183
by Jared Baur 15 Aug '23

15 Aug '23

I am looking for some advice for configuring coreboot with a uImage fit payload for an mt8183 chromebook (Kukui Fennel)? I have said fitimage, I've modified the memlayout for the mt8183 board similar to https://github.com/coreboot/coreboot/commit/22e605c2c06f553b98131a87b634709… so that the fitimage fits in the cbfs and has space to load, and coreboot successfully builds. I've also enabled a bunch of debug settings for coreboot printing to serial. When flashing the ROM and rebooting, the serial console doesn't show anything past bootrom messages like so: ``` [DL] 00000000 00000000 010701 F0: 102B 0000 F3: 1006 0033 [0200] F3: 4001 00E0 [0200] F3: 0000 0000 V0: 0000 0000 [0001] 00: 1027 0002 01: 0000 0000 BP: 0C00 0251 [0000] G0: 1182 0000 EC: 0004 0000 [0001] S7: 0000 0000 [0000] CC: 0000 0000 [0001] T0: 0000 00DB [000F] Jump to BL ``` I am happy to post any configuration that would be helpful. I am hoping to just get some serial output from coreboot at this point in time, regardless of the payload.

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Haswell-E 2011-3 support
by Sid_key 14 Aug '23

14 Aug '23

Can someone help to implement 2011-3 support in coreboot? There are quite many 2011-3 chinese boards with broken bios, would be good to run coreboot on them to fix most problems. For example: Huananzhi X99 QD4 (Haswell-E/Broadwell-E 2011-3 CPU, B85/Q87/Z87 chipset) Huananzhi X99 BD4 (Haswell-E/Broadwell-E 2011-3 CPU, B85/Q87/Z87 chipset) I tried to make coreboot dt and to try booting Haswell-E over Haswell drivers, but faced FF postcode: dt: https://github.com/MrArtemSid/coreboot_huananzhi_x99-series/tree/staging1 haswell-e changes: https://github.com/MrArtemSid/coreboot/tree/haswell-e

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The coreboot 4.21 release tag in 1 week
by coreboot org 14 Aug '23

14 Aug '23

Hello coreboot, This is the notification that we're one week away from doing the coreboot 4.21 release tag on August 21st. As mentioned previously, we will have a 1 week delay after the new version is tagged to allow for testing after the release. This will give us a chance to fix any issues that are found during the release process before making the release public. The 4.21 announcement is scheduled for August 28th. If you have any questions or concerns, please let the coreboot release team know. We're using the IRC channel #coreboot_release to coordinate our activities. Martin

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[coreboot - Bug #495] (Response Needed) Stoney not booting PSPSecureOS -- Graphics driver takes 30 minutes to start
by CoolStar Organization 14 Aug '23

14 Aug '23

Issue #495 has been reported by CoolStar Organization. ---------------------------------------- Bug #495: Stoney not booting PSPSecureOS -- Graphics driver takes 30 minutes to start https://ticket.coreboot.org/issues/495 * Author: CoolStar Organization * Status: Response Needed * Priority: High * Category: chipset configuration * Target version: none * Start date: 2023-06-14 * Affected versions: 4.21, 4.15, 4.16, 4.17, 4.18, 4.19, master * Affected hardware: stoney * Affected OS: Windows 10, Windows 11 ---------------------------------------- Windows 11 Graphics driver takes 30 minutes to start on Stoney due to missing PSPSecureOS. Windows 10 20H2 and newer hangs on boot (potentially from the same thing) -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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[coreboot - Bug #496] (New) Missing malloc check in libpayload
by Keith Makan 14 Aug '23

14 Aug '23

Issue #496 has been reported by Keith Makan. ---------------------------------------- Bug #496: Missing malloc check in libpayload https://ticket.coreboot.org/issues/496 * Author: Keith Makan * Status: New * Priority: Normal * Target version: none * Start date: 2023-06-27 * Affected versions: 4.21 * Affected hardware: ALL * Affected OS: ALL ---------------------------------------- libpayload in payload/libpayload/drivers/options.c::get_option_as_string does not issue a NULL check against malloc's return code. Should there be a NOMEM error this may result in a NULL pointer deref or crash. The following code extract illustrates the mentioned issue: ` int get_option_as_string(const struct nvram_accessor *nvram, struct cb_cmos_option_table *option_table, char **dest, const char *name) { ... /* extra byte to ensure 0-terminated strings */ raw = malloc(cmos_length+1); memset(raw, 0, cmos_length+1); <--- no check against malloc's return code ` -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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coreboot August 2023