August 2023 - coreboot - mail.coreboot.org

[coreboot - Bug #496] (New) Missing malloc check in libpayload
by Keith Makan Aug. 14, 2023

Aug. 14, 2023

Issue #496 has been reported by Keith Makan. ---------------------------------------- Bug #496: Missing malloc check in libpayload https://ticket.coreboot.org/issues/496 * Author: Keith Makan * Status: New * Priority: Normal * Target version: none * Start date: 2023-06-27 * Affected versions: 4.21 * Affected hardware: ALL * Affected OS: ALL ---------------------------------------- libpayload in payload/libpayload/drivers/options.c::get_option_as_string does not issue a NULL check against malloc's return code. Should there be a NOMEM error this may result in a NULL pointer deref or crash. The following code extract illustrates the mentioned issue: ` int get_option_as_string(const struct nvram_accessor *nvram, struct cb_cmos_option_table *option_table, char **dest, const char *name) { ... /* extra byte to ensure 0-terminated strings */ raw = malloc(cmos_length+1); memset(raw, 0, cmos_length+1); <--- no check against malloc's return code ` -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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[PATCH v2 1/2] x86: coreboot: Update cbmem table
by Simon Glass Aug. 14, 2023

Aug. 14, 2023

This changed a few years ago to include an overflow flag. Bring in the new structure. This comes from coreboot commit: 6f5ead14b4 ("mb/google/nissa/var/joxer: Update eMMC DLL settings") Note: There are several implementations of this in coreboot. I have chosen to follow the one in src/lib/cbmem_console.c Signed-off-by: Simon Glass <sjg(a)chromium.org> --- (no changes since v1) arch/x86/include/asm/coreboot_tables.h | 19 ++++++++++++++++--- 1 file changed, 16 insertions(+), 3 deletions(-) diff --git a/arch/x86/include/asm/coreboot_tables.h b/arch/x86/include/asm/coreboot_tables.h index 4de137fbab9d..8db7c189b474 100644 --- a/arch/x86/include/asm/coreboot_tables.h +++ b/arch/x86/include/asm/coreboot_tables.h @@ -299,11 +299,24 @@ struct cb_vdat { #define CB_TAG_TIMESTAMPS 0x0016 #define CB_TAG_CBMEM_CONSOLE 0x0017 -struct cbmem_console { +#define CBMC_CURSOR_MASK ((1 << 28) - 1) +#define CBMC_OVERFLOW BIT(31) + +/* + * struct cbmem_console - In-memory console buffer for coreboot + * + * Structure describing console buffer. It is overlaid on a flat memory area, + * with body covering the extent of the memory. Once the buffer is full, + * output will wrap back around to the start of the buffer. The high bit of the + * cursor field gets set to indicate that this happened. If the underlying + * storage allows this, the buffer will persist across multiple boots and append + * to the previous log. + */ +struct __packed cbmem_console { u32 size; u32 cursor; - char body[0]; -} __packed; + u8 body[0]; +}; #define CB_TAG_MRC_CACHE 0x0018 -- 2.41.0.640.ga95def55d0-goog

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New Defects reported by Coverity Scan for coreboot
by scan-admin＠coverity.com Aug. 11, 2023

Aug. 11, 2023

Hi, Please find the latest report on new defect(s) introduced to coreboot found with Coverity Scan. 2 new defect(s) introduced to coreboot found with Coverity Scan. New defect(s) Reported-by: Coverity Scan Showing 2 of 2 defect(s) ** CID 1518442: Resource leaks (RESOURCE_LEAK) /3rdparty/vboot/futility/file_type_bios.c: 215 in ft_show_bios() ________________________________________________________________________________________________________ *** CID 1518442: Resource leaks (RESOURCE_LEAK) /3rdparty/vboot/futility/file_type_bios.c: 215 in ft_show_bios() 209 if (fmap_find_by_name(buf, len, fmap, fmap_name[c], &ah)) { 210 /* But the file might be truncated */ 211 fmap_limit_area(ah, len); 212 if (asprintf((char **)&ft_print_header, "bios::%s", 213 fmap_name[c]) <= 0) { 214 ERROR("Failed to allocate buffer for FT_PRINT"); >>> CID 1518442: Resource leaks (RESOURCE_LEAK) >>> Variable "buf" going out of scope leaks the storage it points to. 215 return 1; 216 } 217 218 /* Update the state we're passing around */ 219 state.c = c; 220 state.area[c].offset = ah->area_offset; ** CID 1518441: Resource leaks (RESOURCE_LEAK) /3rdparty/vboot/futility/file_type_bios.c: 215 in ft_show_bios() ________________________________________________________________________________________________________ *** CID 1518441: Resource leaks (RESOURCE_LEAK) /3rdparty/vboot/futility/file_type_bios.c: 215 in ft_show_bios() 209 if (fmap_find_by_name(buf, len, fmap, fmap_name[c], &ah)) { 210 /* But the file might be truncated */ 211 fmap_limit_area(ah, len); 212 if (asprintf((char **)&ft_print_header, "bios::%s", 213 fmap_name[c]) <= 0) { 214 ERROR("Failed to allocate buffer for FT_PRINT"); >>> CID 1518441: Resource leaks (RESOURCE_LEAK) >>> Handle variable "fd" going out of scope leaks the handle. 215 return 1; 216 } 217 218 /* Update the state we're passing around */ 219 state.c = c; 220 state.area[c].offset = ah->area_offset; ________________________________________________________________________________________________________ To view the defects in Coverity Scan visit, https://u15810271.ct.sendgrid.net/ls/click?upn=HRESupC-2F2Czv4BOaCWWCy7my0P…

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Custom Splash Screen
by Ahamed Husni Aug. 9, 2023

Aug. 9, 2023

Hi all, I want to display a custom logo in the splash screen for a specified amount of time (SeaBIOS as payload). How do I configure the logo and give a timeout when building coreboot? Any pointers will be really helpful. Regards, Husni.

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Termin mit Hinweis abgesagt: coreboot Leadership Meeting - Mi 9. Aug. 2023 19:00 - 20:00 (MESZ) (coreboot@coreboot.org)
by Patrick Georgi Aug. 9, 2023

Aug. 9, 2023

Dieser Termin wurde mit folgendem Hinweis abgesagt: "The entire leadership team can't make it today, so let's take the rare decision to cancel the meeting." coreboot Leadership Meeting Mittwoch 9. Aug. 2023 ⋅ 19:00 – 20:00 Mitteleuropäische Zeit - Berlin Mit Google Meet teilnehmen https://meet.google.com/pyt-newq-rbb?hs=224 Per Telefon teilnehmen (US) +1 608-618-4744 PIN: 143813170 Weitere Telefonnummern https://tel.meet/pyt-newq-rbb?pin=6680344120895&hs=0 Anhänge Notes - coreboot Leadership Meeting https://docs.google.com/document/d/1FdgO-uLMmdRzBiOYJmzwaf8MSTVNpn6lHbQk7H8… Meeting Minutes - If you don't have edit access and want it, please ask Patrick G. Organisator Patrick Georgi pgeorgi(a)google.com Gäste Patrick Georgi - Organisator gaumless(a)gmail.com Stefan Reinauer Werner Zeh David Hendricks Noga Smith sheng.tan(a)9elements.com subratabanik(a)google.com kapilporwal(a)google.com hughsient(a)gmail.com taruntuli(a)google.com maximilian.brune(a)9elements.com rangasai.v.chaganty(a)intel.com vincent.zimmer(a)intel.com Simon Glass Andreas Huber mattpapa(a)amazon.com WIM - Optional Dossym Nurmukhanov - Optional christian.walter(a)9elements.com - Optional marshalldawson3rd(a)gmail.com - Optional patrick.rudolph(a)9elements.com - Optional matt.devillier(a)gmail.com - Optional jeremy(a)system76.com - Optional Ron Minnich - Optional jaytalbott(a)sysproconsulting.com - Optional jonzhang(a)fb.com - Optional zaolin.daisuki(a)googlemail.com - Optional rminnich(a)gmail.com - Optional Julius Werner - Optional epeers(a)google.com - Optional felix.held(a)amd.corp-partner.google.com - Optional tcrawford(a)system76.com - Optional Rocky Phagura - Optional Desimone, Nathaniel L - Optional arthur(a)aheymans.xyz - Optional felix.singer12(a)gmail.com - Optional stefank.reinauer(a)gmail.com - Optional Shelley Chen - Optional kramasub(a)google.com - Optional nico.h(a)gmx.de - Optional jason.glenesk(a)amd.com - Optional Held, Felix - Optional felix-coreboot(a)felixheld.de - Optional felix(a)felixheld.de - Optional gduynisveld(a)eltan.com - Optional coreboot(a)coreboot.org - Optional ~~//~~ Einladung von Google Kalender: https://calendar.google.com/calendar/ Sie erhalten diese E-Mail, weil Sie ein Gast des Termins sind. Wenn Sie keine weiteren Informationen zu diesem Termin erhalten möchten, lehnen Sie die Einladung ab. Wenn Sie diese Einladung weiterleiten, kann jeder Empfänger eine Antwort an den Organisator senden und zur Gästeliste hinzugefügt werden. Außerdem könnte er weitere Nutzer einladen und Ihre Antwort ändern. Weitere Informationen https://support.google.com/calendar/answer/37135#forwarding

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The coreboot 4.21 release is scheduled for 2023_08_21
by coreboot org Aug. 7, 2023

Aug. 7, 2023

Hi everyone, This is the notification that we're planning on tagging the coreboot 4.21 release in 2 weeks on August 21st. Please let us know if there are any patches that need to make it into the release by setting the topic to “coreboot_release_4.21". This does not guarantee that the patch will be merged before then, but an effort will be made to get those patches merged. As always, we'd appreciate any platform testing that can be done now before the release is done. Starting with the 4.19 release we have a 1 week delay after the new version is tagged to allow for testing after the release. This will give us a chance to fix any issues that are found during the release process before making the release public. The 4.21 announcement is scheduled for August 28th. If you have any questions, please let the coreboot release team know. We're using the IRC channel #coreboot_release to coordinate our activities. Martin

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Tree maintenance and build nodes
by Kyösti Mälkki Aug. 6, 2023

Aug. 6, 2023

Hi A couple of questions, less technical than usual. Do we have any sample cases of bringing boards back from older branches? I would like to have a branch set up for bringing back some selected AGESA from 4.18 branch. My plan would be to backport features from ToT into said new branch and resolve issues there. Once considered clean enough, it should be a three commit drop (vendorcode, platform, boards) to land on master? Is there someone (corporate) currently funding or hiring personnel with reviews and tree maintenance as a priority? Is there currently anyone actually assigning from their existing resources to put attention to frameworks, while customers' board ports and resolving their issues have tight schedules? Regards, Kyösti Mälkki

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New Defects reported by Coverity Scan for coreboot
by scan-admin＠coverity.com Aug. 4, 2023

Aug. 4, 2023

Hi, Please find the latest report on new defect(s) introduced to coreboot found with Coverity Scan. 1 new defect(s) introduced to coreboot found with Coverity Scan. New defect(s) Reported-by: Coverity Scan Showing 1 of 1 defect(s) ** CID 1518331: Memory - illegal accesses (UNINIT) ________________________________________________________________________________________________________ *** CID 1518331: Memory - illegal accesses (UNINIT) /src/lib/libgcov.c: 255 in buffer_fn_data() 249 return &fn_buffer->next; 250 251 fail: 252 fprintf(stderr, "profiling:%s:Function %u %s %u\n", filename, fn_ix, 253 len ? "cannot allocate" : "counter mismatch", len ? len : ix); 254 >>> CID 1518331: Memory - illegal accesses (UNINIT) >>> Using uninitialized value "fn_buffer->info.ctrs[0].values" when calling "free_fn_data". 255 return (struct gcov_fn_buffer **)free_fn_data(gi_ptr, fn_buffer, ix); 256 } 257 258 /* Add an unsigned value to the current crc */ 259 260 static gcov_unsigned_t ________________________________________________________________________________________________________ To view the defects in Coverity Scan visit, https://u15810271.ct.sendgrid.net/ls/click?upn=HRESupC-2F2Czv4BOaCWWCy7my0P…

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Re: Run abuild only on sandybridge boards with MRC raminit. How?
by Keith Hui Aug. 3, 2023

Aug. 3, 2023

Hi Martin, Thanks for your reply. My abuild version is 0.11.01 dated this February. I recently put out a patch (CB:76775) to get abuild documentation back into the tree. I took a text capture of that version and incorporated it into the content. Eventually I was able to get that command line to do what I want (build only SNB boards), as is. I created coreboot-builds myself under main coreboot directory and mounted another filesystem there, at first a zram instance and then an ext4 image file on my external mechanical drive, so I don't wear down my SSD excessively. Build environment is Fedora 38. Bash version I haven't checked. My patch mentioned another earlier patch of mine on variant handling. Like I said at the time we either fix the handling or document the quirk. I documented the quirk. I also documented a real life case of ambiguity in the patch, which dovetails nicely into --skip_(un)set options I added documentation for. Two things we could look at. Regards Keith On Thu., Aug. 3, 2023, 17:12 Martin Roth, <gaumless(a)tutanota.com> wrote: > Hey Keith - I replied on the mailing list with some information, but this > reply is off list. I don't see anything wrong with your command line, and > the same command line is working for me, so I'd like to debug the issue if > you have time. > > - where did you run the command from? I'm wondering if abuild couldn't > make the coreboot-build directory. > > Can you try specifying the output directory? > util/abuild/abuild --timeless --skip_unset NORTHBRIDGE_INTEL_SANDYBRIDGE > -R /usr/src/coreboot -o /tmp/coreboot-builds > > If that works, great, it was a problem with the directory you were running > the command from. If not, here are a few questions since I don't want to > make any assumptions: > - What OS are you running this on? > - what version of abuild are you using? > - What bash version are you using? > > For reference: > - I'm on MX-linux, based on debian, version 21.3 > - % git --no-pager log -n1 --oneline -- util/abuild/abuild > 6a50e555fc util/abuild: Add per-build statistics tarfile > - % bash --version > GNU bash, version 5.1.4(1)-release (x86_64-pc-linux-gnu) > > >

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Run abuild only on sandybridge boards with MRC raminit. How?
by Keith Hui Aug. 3, 2023

Aug. 3, 2023

After 34 patches converting all sandybridge boards to Haswell-style SPD info, I now need to run abuild to see if I missed any, To save time, space, and possibly wear on my SSD I only want to run abuild on sandybridge boards (i.e. boards with NORTHBRIDGE_INTEL_SANDYBRIDGE Kconfig) and, for boards that don't force USE_NATIVE_RAMINIT, run it with that Kconfig off. I ran this from my mechanical USB drive: $ util/abuild/abuild --timeless --skip_unset NORTHBRIDGE_INTEL_SANDYBRIDGE -R /usr/src/coreboot And all boards get skipped. It seems right, until I saw these two known SNB boards getting skipped too, then I stopped the run. Building board INTEL_DQ67SW (using default config) Building INTEL_DQ67SW Creating config file for INTEL_DQ67SW... INTEL_DQ67SW (Skipping CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE not set) INTEL_DQ67SW config created. config file: coreboot-builds/INTEL_DQ67SW/config.build has incorrect config value INTEL_DQ67SW does not have NORTHBRIDGE_INTEL_SANDYBRIDGE set. Skipping at user's request. Building board INTEL_EMERALDLAKE2 (using default config) Building INTEL_EMERALDLAKE2 Creating config file for INTEL_EMERALDLAKE2... INTEL_EMERALDLAKE2 (Skipping CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE not set) INTEL_EMERALDLAKE2 config created. config file: coreboot-builds/INTEL_EMERALDLAKE2/config.build has incorrect config value INTEL_EMERALDLAKE2 does not have NORTHBRIDGE_INTEL_SANDYBRIDGE set. Skipping at user's request. Is what I did supposed to work? For the second item about USE_NATIVE_RAMINIT, do I really have to set a board config for each and every MRC raminit board and turn it off there?

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