coreboot July 2023

coreboot@coreboot.org

19 participants
30 discussions

[coreboot - Bug #496] (New) Missing malloc check in libpayload
by Keith Makan 14 Aug '23

14 Aug '23

Issue #496 has been reported by Keith Makan. ---------------------------------------- Bug #496: Missing malloc check in libpayload https://ticket.coreboot.org/issues/496 * Author: Keith Makan * Status: New * Priority: Normal * Target version: none * Start date: 2023-06-27 * Affected versions: 4.21 * Affected hardware: ALL * Affected OS: ALL ---------------------------------------- libpayload in payload/libpayload/drivers/options.c::get_option_as_string does not issue a NULL check against malloc's return code. Should there be a NOMEM error this may result in a NULL pointer deref or crash. The following code extract illustrates the mentioned issue: ` int get_option_as_string(const struct nvram_accessor *nvram, struct cb_cmos_option_table *option_table, char **dest, const char *name) { ... /* extra byte to ensure 0-terminated strings */ raw = malloc(cmos_length+1); memset(raw, 0, cmos_length+1); <--- no check against malloc's return code ` -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

2 1

Custom Splash Screen
by Ahamed Husni 09 Aug '23

09 Aug '23

Hi all, I want to display a custom logo in the splash screen for a specified amount of time (SeaBIOS as payload). How do I configure the logo and give a timeout when building coreboot? Any pointers will be really helpful. Regards, Husni.

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Tree maintenance and build nodes
by Kyösti Mälkki 06 Aug '23

06 Aug '23

Hi A couple of questions, less technical than usual. Do we have any sample cases of bringing boards back from older branches? I would like to have a branch set up for bringing back some selected AGESA from 4.18 branch. My plan would be to backport features from ToT into said new branch and resolve issues there. Once considered clean enough, it should be a three commit drop (vendorcode, platform, boards) to land on master? Is there someone (corporate) currently funding or hiring personnel with reviews and tree maintenance as a priority? Is there currently anyone actually assigning from their existing resources to put attention to frameworks, while customers' board ports and resolving their issues have tight schedules? Regards, Kyösti Mälkki

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Run abuild only on sandybridge boards with MRC raminit. How?
by Keith Hui 03 Aug '23

03 Aug '23

After 34 patches converting all sandybridge boards to Haswell-style SPD info, I now need to run abuild to see if I missed any, To save time, space, and possibly wear on my SSD I only want to run abuild on sandybridge boards (i.e. boards with NORTHBRIDGE_INTEL_SANDYBRIDGE Kconfig) and, for boards that don't force USE_NATIVE_RAMINIT, run it with that Kconfig off. I ran this from my mechanical USB drive: $ util/abuild/abuild --timeless --skip_unset NORTHBRIDGE_INTEL_SANDYBRIDGE -R /usr/src/coreboot And all boards get skipped. It seems right, until I saw these two known SNB boards getting skipped too, then I stopped the run. Building board INTEL_DQ67SW (using default config) Building INTEL_DQ67SW Creating config file for INTEL_DQ67SW... INTEL_DQ67SW (Skipping CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE not set) INTEL_DQ67SW config created. config file: coreboot-builds/INTEL_DQ67SW/config.build has incorrect config value INTEL_DQ67SW does not have NORTHBRIDGE_INTEL_SANDYBRIDGE set. Skipping at user's request. Building board INTEL_EMERALDLAKE2 (using default config) Building INTEL_EMERALDLAKE2 Creating config file for INTEL_EMERALDLAKE2... INTEL_EMERALDLAKE2 (Skipping CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE not set) INTEL_EMERALDLAKE2 config created. config file: coreboot-builds/INTEL_EMERALDLAKE2/config.build has incorrect config value INTEL_EMERALDLAKE2 does not have NORTHBRIDGE_INTEL_SANDYBRIDGE set. Skipping at user's request. Is what I did supposed to work? For the second item about USE_NATIVE_RAMINIT, do I really have to set a board config for each and every MRC raminit board and turn it off there?

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[coreboot - Feature #476] (New) Add option to convert coreboot-inited linear frame buffer to efifb directly
by Bill XIE 02 Aug '23

02 Aug '23

Issue #476 has been reported by Bill XIE. ---------------------------------------- Feature #476: Add option to convert coreboot-inited linear frame buffer to efifb directly https://ticket.coreboot.org/issues/476 * Author: Bill XIE * Status: New * Priority: Normal * Category: coreboot common code * Target version: none * Start date: 2023-03-30 * Affected OS: GNU/Linux ---------------------------------------- Currently, the linear frame buffer that coreboot initializes should be handled by Linux kernel with dedicated driver "simplefb", but most installer of GNU/Linux distributions only enables "efifb" support, which causes a GNU/Linux installer kexec-ed from a Linux payload running atop simplefb unable to output graphics. Currently, Grub payload could turn coreboot-initialized simplefb to efifb, which can be easily examined from the dmesg log of GNU/Linux booted from Grub payload running atop coreboot-inited linear frame buffer (simplefb). Chainloading a Linux payload with a minimal Grub payload only containing module "linux" and "cbfs" could make the Linux payload running atop efifb, of which GNU/Linux installers can make use, but the related code could be ported to coreboot to make things easier. -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

2 4

New Matrix channel #coreboot:matrix.org
by Nico Huber 31 Jul '23

31 Jul '23

Hi all, due to ongoing reliability issues with the matrix.org-to-libera.chat bridge, channel portalling is going to be disabled [1]. Hence there is a new Matrix channel #coreboot:matrix.org [2] that is bridged to the IRC channel on Libera. Hopefully, this will work a little better. AIUI, the old channel will become read-only on the Matrix network by August, 11th. So all Matrix users are encouraged to join the new channel. For direct IRC users, nothing changes. Best regards, Nico [1] https://libera.chat/news/matrix-deportalling [2] https://matrix.to/#/#coreboot:matrix.org

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[coreboot - Support #501] (New) Adding Hybrid GPU mode to my Clevo PC70HR (System76 Oryp 8)
by Timo J. 31 Jul '23

31 Jul '23

Issue #501 has been reported by Timo J.. ---------------------------------------- Support #501: Adding Hybrid GPU mode to my Clevo PC70HR (System76 Oryp 8) https://ticket.coreboot.org/issues/501 * Author: Timo J. * Status: New * Priority: Low * Category: chipset configuration * Target version: master * Start date: 2023-07-31 * Affected versions: master * Needs backport to: master * Related links: https://www.e-weekly.co.uk/download/rnd/drivers/clevo/pcxxhxx/esm7.pdf https://www.coreboot.org/Board:lenovo/Nvidia_Optimus https://github.com/coreboot/coreboot/tree/master/src/mainboard/system76/tgl… https://github.com/coreboot/coreboot/tree/master/src/mainboard/lenovo/t430 * Affected hardware: Clevo PC70HR ---------------------------------------- Hello there I'm trying to add support for the GPU MUX in my notebook but, i also seen it implemented in the Lenovo notebooks, and the GPIO also seems to be registered in my notebook, but it didn't take any use of it. in the file "coreboot/src/mainboard/system76/tgl-h/variants/oryp8/gpio.c" is following to find ` PAD_CFG_GPI(GPP_R16, NONE, DEEP), // BL_PWM_EN_EC PAD_CFG_GPI(GPP_R17, NONE, DEEP), // PLVDD_RST_EC PAD_CFG_GPI(GPP_R18, NONE, DEEP), // MUX_CTRL_BIOS PAD_CFG_GPI(GPP_R19, NONE, DEEP), // PS8461_SW` soo the GPIOs for the MUX exist and from the schematics i can see the MUX and how its connected ![](optimus.png) the Lenovo T430 got this in its devicetree.cb ` chip drivers/lenovo/hybrid_graphics device pnp ff.f on end # dummy register "detect_gpio" = "21" register "has_panel_hybrid_gpio" = "1" register "panel_hybrid_gpio" = "52" register "panel_integrated_lvl" = "1" register "has_backlight_gpio" = "0" register "has_dgpu_power_gpio" = "0" register "has_thinker1" = "1" end` but mine doesn't can you someone of you maybe give me a little advise how to do it? i really don't wanna break anything. ---Files-------------------------------- optimus.png (531 KB) -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

1 0

switch or router hardware with coreboot
by Carl-Daniel Hailfinger 28 Jul '23

28 Jul '23

Hi, is there any currently commercially available switch or router hardware (10Gbit/s or more) running coreboot and preferably also Linux? I'm currently trying to build a PoC network where all components have mostly FOSS firmware and operating systems. My Wifi access points and 1 Gbit/s switches are running U-Boot and OpenWrt, so on that tier I'm covered. OpenWrt is even running on very few select 10 Gbit/s switches, but there the bootloader seems to be U-Boot+blob. For routing, I'm currently using PCEngines APU2 with coreboot and Debian, but those are not really made to handle routing or even NAT at more than 1 Gbit/s. Once the PoC phase is done, I expect required routing/NAT/packet filtering bandwidth to exceed 5 Gbit/s and I'd like to use a coreboot based product for that. If necessary, I can add a few network cards to a general-purpose server, but a purpose-built device would be preferred. Suggestions? Comments? Thanks, Carl-Daniel

4 3

CPU with a faulty RAM controller? o_O AGESA debug info inside
by Mike Banon 28 Jul '23

28 Jul '23

Faulty CPUs are truly rare... But recently while building the A88XM-E coreboot test stand (more info at [1] "ProTip: buy a 5.25" fan controller while you still can" link below) ---> I got a used A10-6700 online for a dirt cheap price: the listing looked nice - a clear photo without any bent pins - but there was an intriguing note "one RAM slot doesn't work". So I thought: > That looks like a motherboard problem! Or something related to the seller's RAM sticks: either a faulty stick or a badly mismatching pair. Shouldn't happen on my spare well-tested A88XM-E with a known good RAM, especially with a beautiful coreboot replacing the crappy proprietary UEFI, so lets save a few bucks " However, I ran into the same problem: the board boots fine to OS but sees just one of two BLT8G3D1869DT1TX0 8GB RAM sticks, regardless if I use the XMP profile to run them at 1866MHz CL9 ( CPU_AMD_AGESA_OPENSOURCE_MEM_XMP_1 stuff which I created two years ago - [2] ) or keep them at turtle 1333Mhz CL9. Here are the most interesting AGESA events which happen while trying to initialize the RAM: *) WARNING Event: 04012100 Data: 0, 0, 0, 0 [0m ; AGESA.h tells: #define MEM_WARNING_CHANNEL_INTERLEAVING_NOT_ENABLED 0x04012100ul ///< Channel Interleaveing Requested, but could not be enabled *) WARNING Event: 04012200 Data: 0, 0, 0, 0 [0m ; AGESA.h tells: #define MEM_WARNING_BANK_INTERLEAVING_NOT_ENABLED 0x04012200ul ///< Bank Interleaveing Requested, but could not be enabled *) ERROR Event: 04010300 Data: 0, 0, 0, 0 [0m ; AGESA.h tells: #define MEM_ERROR_NO_DQS_POS_RD_WINDOW 0x04010300ul ///< No DQS Position window for RD DQS See the full AGESA log here - https://pastebin.com/FLWFk9SF . Please keep in mind that, if I replace this with another (bought later) A10-6700 - using the same A88XM-E / RAM / coreboot / OS - then everything works fine. So it's clearly a CPU problem, but may be possible to avoid from the firmware side... Do you think it's possible to workaround this problem (no matter how dirty the hack) from AGESA side and get this CPU working with both sticks? Is there anything I could try before giving up and making a DIY keychain or whatever? Any ideas? [1] https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/message/RDM… - " ProTip: buy a 5.25" fan controller while you still can " [2] https://review.coreboot.org/c/coreboot/+/40488 - vc/amd/agesa/f.../Proc/Mem/Tech/DDR3: Support XMP memory profiles -- Best regards, Mike Banon Open Source Community Manager of 3mdeb - https://3mdeb.com/

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Can't write new comments under "payloads/cbui: Add new payload CBUI" change
by Mike Banon 28 Jul '23

28 Jul '23

Good day! So, I found this Gerrit change: https://review.coreboot.org/c/coreboot/+/23586 - payloads/cbui: Add new payload CBUI Wanted to reply " Not tested yet, but looks like a nice idea " but got this: Error 400 (Bad Request): One or more comments were rejected in validation: Exceeding maximum number of comments: 5139 (existing) + 2 (new) > 5000 This issue might be blocking the further work on this change (and I don't see why there should be any limit at all) -- Best regards, Mike Banon Open Source Community Manager of 3mdeb - https://3mdeb.com/

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coreboot July 2023