coreboot June 2023

coreboot@coreboot.org

27 participants
29 discussions

[coreboot - Feature #476] (New) Add option to convert coreboot-inited linear frame buffer to efifb directly
by Bill XIE 01 Aug '23

01 Aug '23

Issue #476 has been reported by Bill XIE. ---------------------------------------- Feature #476: Add option to convert coreboot-inited linear frame buffer to efifb directly https://ticket.coreboot.org/issues/476 * Author: Bill XIE * Status: New * Priority: Normal * Category: coreboot common code * Target version: none * Start date: 2023-03-30 * Affected OS: GNU/Linux ---------------------------------------- Currently, the linear frame buffer that coreboot initializes should be handled by Linux kernel with dedicated driver "simplefb", but most installer of GNU/Linux distributions only enables "efifb" support, which causes a GNU/Linux installer kexec-ed from a Linux payload running atop simplefb unable to output graphics. Currently, Grub payload could turn coreboot-initialized simplefb to efifb, which can be easily examined from the dmesg log of GNU/Linux booted from Grub payload running atop coreboot-inited linear frame buffer (simplefb). Chainloading a Linux payload with a minimal Grub payload only containing module "linux" and "cbfs" could make the Linux payload running atop efifb, of which GNU/Linux installers can make use, but the related code could be ported to coreboot to make things easier. -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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Potential EC refactor for Lenovo laptops
by Avery 30 Jun '23

30 Jun '23

Hello, I've been reverse-engineering the ThinkPad X230's MEC 1619 EC firmware (G2HT35WW) and the UEFI binaries which interface with it on ports 62h/66h and 1600h/1604h. In particular I've been looking at the process for flashing new EC firmware, referencing the public MEC1618 datasheet[1], so I could try to flash new EC firmware on a corebooted ThinkPad; the relevant binaries are the following: * EcFwUpdateDxe 0C396FCA-6BDA-4A15-B6A3-A6FA4544BDB7 * EcIoDxe 114CA60C-D965-4C13-BEF7-C4062248E1FA * Installs a native protocol interface 3161DDAB-9600-4301-AAB2-93006395824A * EcIoSmm 03EBDB4B-96BA-4F40-8329-7F3AA8865707 * Installs a native protocol interface AADE7C97-98E7-4CFA-B4EF-BBE20506A31D From this, I found that these binaries uses at least some of the the EC register layout for Quanta's firmware for IT8518 ECs (ec/quanta/it8518/acpi/ec.asl), which is included in mb/google/stout. The stout codename refers to ThinkPad X131e, which are also Ivy Bridges, and also has a different mainboard tree in mb/lenovo/x131e which separately uses ec/lenovo/h8/acpi/ec.asl. The X230 mainboard also uses the H8S ASL. Both the H8S and IT8518 definitions line up pretty well for the most part, but here are also some evidence from my reversing on the X230: EcIoDxe exposes a function that appears to implement the SMBus Host Controller Interface specifications. The following are the EC registers used there: * 50h SMB_PRTCL * 51h SMB_STS * 52h SMB_ADDR * 53h SMB_CMD * 54h-73h SMB_DATA * 74h SMB_BCNT EcFwUpdateDxe also updates the register at 3Dh, bitwise-orring it with DFh. This action is said to restrict EC flash access past the boot sequence [2], and lines up with the description of "Password Control" given by the IT8518 ASL. Since the H8 configuration appears to be common across multiple boards, I believe these two can be merged seeing as the IT8518 definitions are a bit more detailed, potential mainboard-specific quirks notwithstanding. I'm curious to hear if there would be any issues or incompatibilities with this. Cheers, Avery [1]: https://ww1.microchip.com/downloads/aemDocuments/documents/OTH/ProductDocum… [2]: https://i.blackhat.com/USA-19/Thursday/us-19-Matrosov-Breaking-Through-Anot…

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disable efficient-cores or performance-cores in Intel 12th gen processors
by baptx 28 Jun '23

28 Jun '23

Hello, For people who use the 12th generation of Intel Core processors, they may want to disable efficient-cores in the BIOS to improve performance ( https://www.reddit.com/r/intel/comments/thp7jh/disabling_the_efficiency_cor…), is it supported by coreboot or Dasharo? Some people may also want to disable performance-cores instead to save more battery ( https://www.reddit.com/r/overclocking/comments/x0xu1c/can_you_disable_perfo…), is it supported also? If some of these disabling option are not available, is there any plan to support them and is there a workaround currently? Thanks.

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Legacy OS Support
by Mason McAlister 28 Jun '23

28 Jun '23

hello! any idea when Legacy OS/BIOS support is coming to Coreboot? i'd like to be able to boot legacy OSes (such as Windows 7 and below) on my chromebook, which is using MrChromebox's fork of Coreboot. i'm not "expecting" Legacy OS/BIOS support, UEFI is good enough, i think it'd just be cool if i could get windows XP or windows 7 on a chromebook. cheers! -Mason

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Coreboot's stance on Purism since 2015: What changed ?
by Alexandre Janvrin 28 Jun '23

28 Jun '23

Greetings, I have been shopping around for a laptop during the past few weeks, aiming for a mix of performance and privacy. During my search, I came across a blog post by mrnuke: - https://web.archive.org/web/20150223201313/https://blogs.coreboot.org/blog/… (the post was referenced in a Qube OS discussion related to Anti Evil Maid: https://groups.google.com/g/qubes-users/c/sEmZfOZqYXM/m/j5rHeex1BAAJ) I've noticed that this post has disappeared from Coreboot's blog, and that Coreboot now advertises Purism quite differently. From https://www.coreboot.org/users.html: "Purism manufactures security focused laptops designed chip by chip to work with free/libre and open source software. Purism laptops are the only independently-made, brand new, high-performance laptops on the market specifically meant to pair recent technologies with coreboot and a neutralized Intel Management Engine." I also came across Purism's public answer: https://puri.sm/posts/about-purism-and-librems-and-cake/ I guess the change in Coreboot's stance can be explained in a few manners: - Purism genuinely improved since 2015 and is now delivering on their promises, - mrnuke's opinion never reflected Coreboot's opinions, - Purism extended a "helping" hand to Coreboot, in order to align both parties' economical objectives, From an external viewpoint, I'd say that Purism has improved on their delivery, and their narrative seems to be grounded in reality rather than smoke and mirrors. (Even though they currently admit to still having some binary blobs here and there) Can you please provide more context, and indulge in the curiosity of a random user ? (Disclaimer: I do not intend to buy a Purism laptop, not because I think they are bad, but because I'll have a more "Do It Yourself" approach) Best regards, Alexandre (a security/privacy enthusiast)

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2023-06-28 - coreboot Leadership Meeting
by coreboot org 28 Jun '23

28 Jun '23

# 2023-06-28 - coreboot Leadership Attendees: DavidH, Jpmurphy, Coolstar, MattD, FelixS, WernerZ, JonathanH, StefanR, MartinR, JuliusW, RonM, KarthikR, DanielM ## Minutes: * [KyöstiM] Make build statistics downloadable from qa.coreboot.org Work to create such tar-file with timestamps and ccache stats started here: [https://review.coreboot.org/c/coreboot/+/75803](https://review.coreboot.org… * Martin will look at making the stats downloadable * [KyöstiM] Is ccache for clang intentionally disabled for coreboot-gerrit queue? I think it would be possible to configure ccache for separate gcc and clang backing storages. * Ccache was causing the build to take longer, so was disabled. Martin did look at separating the two ccache locations, but the GCC ccache is stored in ram, and there isn't typically enough memory to save both. * Look at separating GCC and clang builds into two separate builds. * Look at coverity builds - should probably only build GCC. * [coolstar] Pixel 2013 (Link) I2C bus ACPI (Windows vs Linux) * Attaches to IGD device because the i2c touchpad/touch screen are on it * Brand new drivers that are about to be submitted to MS to get signed – hardware pre-dates I2CSerialBus (which normally would be in HSW+), but new drivers on Windows use it. * It sounds like the best plan is to just push the patches and see if there are any other suggestions. * [Mailing list] Variants * There was a request on the mailing list to look at making a company’s board a variant of the CRB. We should give recommendations in the documentation about when variants should be used. * [Martin] vendors shouldn’t be under other vendors. CRBs shouldn’t be used as baseboards for other boards. * [Werner] Agree with Martin that variants should be used for whitelabel devices, but not for CRBs. * [Ron] Things are the way they are because early in the coreboot project, the other method of having vendors under CRBs was tried. The current method gives free reign to vendors to change whatever they want.Vendors like to tweak their own boards and do not like having other vendors introduce conflicting changes. * What about duplicated code and having to refactor functions out? * Ron - Sure, things can be refactored out, but deduping the code can be very tricky - it leads to a lot of #ifdefs and gets very messy. Mucking about in mainboard code may look good from an abstract firmware engineering standpoint, but leads to issues. * Daniel: Using CRBs for baseboards could work as a tree with another level, but agrees with Ron that having separate boards probably makes more sense. * Who should handle any refactoring? * Martin thinks that pushing refactoring to new coreboot engineers is going to make people want to not contribute to coreboot. * David - Definitely - can’t ask new people to rewrite as a vendor without giving any direction as to why or how, or point at a concrete example. * Ron - Agrees with David - pushing people too hard encourages forks. * Werner - could be a path to more contribution - submit initial patch, then look at rewriting. * David - teaching good code quality and coreboot standards is one thing, but pushing them without direction just leads to frustration from the new person. * Daniel - Experience shows that refactoring without understanding leads to poor refactors. We could use some documentation. Any comments could be written as documentation to help people. * David: “There are plenty of variants in the tree - look at them for examples.” is not helpful - people would have no idea which variant to look at. Especially when one doesn't exist. * Ron - stakes are much higher in firmware. It's easy to mess up and brick a bunch of systems. * Martin & David: Refactoring by beginners causes those beginners to rewrite the code in the CRB, which will lead to issues, especially if they can’t test it. * Stefan - Making code look nice is problematic and can break things. * David will write up some documentation on what was discussed here about when to use variants. Daniel & Werner can help. * Would it be interesting to have “shepherds” to help newcomers to the community? * FelixS: I’m doing this for the releases. * How time consuming is this? * The process is started 6 weeks before the release. It really varies, but typically a few hours a week. * Would people be interested in signing up to shepherd newcomers? * Matt, stefan, martin - sure * Martin will create a signup sheet * Ron, Jonathan, and Jpmurphy would be interested in shadowing until they feel confident. * Martin to send email to the mailing list with a request for additional shepherds. * Make script to help direct attention to patches (status:open and +1'd or +2'd, maybe other criteria) to help get them merged - send to mailing list periodically (weekly digest?). * [DanielM] relaying from Slack * Warner Losh: So I’m trying to understand something about a code change request I got for FreeBSD. A long time ago (2015), we committed: [https://cgit.freebsd.org/src/commit/?id=6c176113bbdd5](https://cgit.freebsd… to implement quirks for what’s not about 10-year-old chromebooks, but specified just the Acer Peppy. Later (2016), I expanded this to all coreboot instances since at the time I only knew that they were in chromebooks. Lately, we’re getting a lot of requests to add exception to the rules that are there. Starting in 2020, we started getting these. I’m wondering if there’s a better way and if people here even know what the issue is/was. DFBSD seems to have deleted all their code for this. [https://github.com/DragonFlyBSD/DragonFlyBSD/commit/ad8b9749306613f2978808b… and [https://github.com/DragonFlyBSD/DragonFlyBSD/commit/7f3d8d5546c701eceefe443… were the original dfbsd commits describing the problem with the emulated i8042. * Could someone reach out to Warner on slack? * Matt and coolstar fixed this in the EC codebase in Matt’s repo. # Notice Decisions shown here are not necessarily final, and are based on the current information available. If there are questions or comments about decisions made, or additional information to present, please put it on the leadership meeting agenda and show up if possible to discuss it. Of course items may also be discussed on the mailing list, but as it's difficult to interpret tone over email, controversial topics frequently do not have good progress in those discussions. For particularly difficult issues, it may be best to try to schedule another meeting. # coreboot leadership meeting minutes https://docs.google.com/document/d/1NRXqXcLBp5pFkHiJbrLdv3Spqh1Hu086HYkKrgK…

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New on blogs.coreboot.org: Libreboot 20230625 released!
by blogs.coreboot.org 25 Jun '23

25 Jun '23

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New on blogs.coreboot.org: No-microcode ROMs available in next Libreboot release (new stable release soon!)
by blogs.coreboot.org 25 Jun '23

25 Jun '23

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[Supported Devices] Acer Aspire TC-780A?
by Techflash 21 Jun '23

21 Jun '23

Hello. I am using an Acer Aspire TC-780A, it has an Intel Core i5-7400 CPU, and is currently running BIOS RO2-B2 by AMI. The machine has UEFI support, and according to `dmidecode`, the ROM is 6MB. For the information you've requested to be sent from the wiki: ====== `lspci -tvnn` ====== -[0000:00]-+-00.0 Intel Corporation Xeon E3-1200 v6/7th Gen Core Processor Host Bridge/DRAM Registers [8086:591f] +-02.0 Intel Corporation HD Graphics 630 [8086:5912] +-08.0 Intel Corporation Xeon E3-1200 v5/v6 / E3-1500 v5 / 6th/7th/8th Gen Core Processor Gaussian Mixture Model [8086:1911] +-14.0 Intel Corporation 100 Series/C230 Series Chipset Family USB 3.0 xHCI Controller [8086:a12f] +-14.2 Intel Corporation 100 Series/C230 Series Chipset Family Thermal Subsystem [8086:a131] +-16.0 Intel Corporation 100 Series/C230 Series Chipset Family MEI Controller #1 [8086:a13a] +-17.0 Intel Corporation Q170/Q150/B150/H170/H110/Z170/CM236 Chipset SATA Controller [AHCI Mode] [8086:a102] +-1c.0-[01]----00.0 Realtek Semiconductor Co., Ltd. RTL8111/8168/8411 PCI Express Gigabit Ethernet Controller [10ec:8168] +-1f.0 Intel Corporation H110 Chipset LPC/eSPI Controller [8086:a143] +-1f.2 Intel Corporation 100 Series/C230 Series Chipset Family Power Management Controller [8086:a121] \-1f.4 Intel Corporation 100 Series/C230 Series Chipset Family SMBus [8086:a123] ====== `superiotool -dV` ====== *Probing for XXX... failed* Probing for ITE Super I/O (init=standard) at 0x2e... Found ITE IT8772F (id=0x8772, rev=0x1) at 0x2e Register dump: idx 20 21 22 23 24 2e 2f val 87 72 01 01 00 00 00 def 87 72 02 00 00 00 00 LDN 0x01 (COM1) idx 30 60 61 70 f0 f1 val 00 03 f8 04 00 50 def 00 03 f8 04 00 50 LDN 0x04 (Environment controller) idx 30 60 61 62 63 70 f0 f1 f2 f3 f4 f5 f6 f9 fa fb val 01 0a 30 0a 20 00 20 00 20 00 00 00 f0 48 00 00 def 00 02 90 02 30 09 00 00 00 00 00 MM MM MM MM MM LDN 0x05 (Keyboard) idx 30 60 61 62 63 70 71 f0 val 01 00 60 00 64 01 02 08 def 01 00 60 00 64 01 02 08 LDN 0x06 (Mouse) idx 30 70 71 f0 val 01 0c 02 00 def 00 0c 02 00 LDN 0x07 (GPIO) idx 25 26 27 28 29 2a 2b 2c 60 61 62 63 70 71 72 73 74 b0 b1 b2 b3 b4 b8 b9 ba bb bc bd c0 c1 c2 c3 c4 c8 c9 ca cb cc cd e0 e1 e2 e3 e4 e9 f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 fa fb val 01 0c 0e 23 c0 00 48 02 0a 10 0a 00 00 01 20 38 00 00 00 00 01 00 00 00 00 00 00 00 01 0c 0e 23 80 01 0c 0e 23 c0 23 00 00 00 00 00 07 00 00 00 00 00 2e 00 00 00 00 00 00 def 00 f3 00 00 00 00 MM 01 00 00 00 00 00 00 20 38 00 00 00 00 00 00 20 00 00 00 00 00 01 00 00 40 00 01 00 00 00 00 00 00 00 00 00 00 MM 00 00 00 00 00 00 00 00 00 00 00 00 LDN 0x0a (Consumer IR) idx 30 60 61 70 f0 val 00 00 00 00 06 def 00 03 10 0b 06 *Probing for XXX... failed* === flashrom -p internal -V === flashrom v1.2 on Linux 6.3.8-arch1-1 (x86_64) flashrom is free software, get the source code at https://flashrom.org flashrom was built with libpci 3.8.0, GCC 12.1.0, little endian Command line (3 args): flashrom -p internal -V Using clock_gettime for delay loops (clk_id: 1, resolution: 1ns). Initializing internal programmer /sys/class/mtd/mtd0 does not exist No coreboot table found. Using Internal DMI decoder. No DMI table found. Found ITE Super I/O, ID 0x8772 on port 0x2e Found chipset "Intel H110" with PCI ID 8086:a143. This chipset is marked as untested. If you are using an up-to-date version of flashrom *and* were (not) able to successfully update your firmware with it, then please email a report to flashrom(a)flashrom.org including a verbose (-V) log. Thank you! Enabling flash write... BIOS_SPI_BC = 0xa88: BIOS Interface Lock-Down: enabled, Boot BIOS Straps: 0x0 (SPI) Top Swap: not enabled SPI Read Configuration: prefetching enabled, caching enabled, BIOS_CNTL = 0x89: BIOS Lock Enable: disabled, BIOS Write Enable: enabled SPIBAR = 0x00007fde70a8b000 (phys = 0xfe010000) 0x04: 0xe800 (HSFS) HSFS: FDONE=0, FCERR=0, AEL=0, SCIP=0, PRR34_LOCKDN=0, WRSDIS=1, FDOPSS=1, FDV=1, FLOCKDN=1 SPI Configuration is locked down. Reading OPCODES... done 0x06: 0x0010 (HSFC) HSFC: FGO=0, HSFC=8, WET=0, FDBC=0, SME=0 0x0c: 0x00000000 (DLOCK) DLOCK: BMWAG_LOCKDN=0, BMRAG_LOCKDN=0, SBMWAG_LOCKDN=0, SBMRAG_LOCKDN=0, PR0_LOCKDN=0, PR1_LOCKDN=0, PR2_LOCKDN=0, PR3_LOCKDN=0, PR4_LOCKDN=0, SSEQ_LOCKDN=0 0x50: 0x00004acb (FRAP) BMWAG 0x00, BMRAG 0x00, BRWA 0x4a, BRRA 0xcb 0x54: 0x00000000 FREG0: Flash Descriptor region (0x00000000-0x00000fff) is read-only. 0x58: 0x07ff0200 FREG1: BIOS region (0x00200000-0x007fffff) is read-write. 0x5C: 0x01ff0001 FREG2: Management Engine region (0x00001000-0x001fffff) is locked. Not all flash regions are freely accessible by flashrom. This is most likely due to an active ME. Please see https://flashrom.org/ME for details. At least some flash regions are read protected. You have to use a flash layout and include only accessible regions. For write operations, you'll additionally need the --noverify-all switch. See manpage for more details. 0xa0: 0x80 (SSFS) SSFS: SCIP=0, FDONE=0, FCERR=0, AEL=0 0xa1: 0xfe0000 (SSFC) SSFC: SCGO=0, ACS=0, SPOP=0, COP=0, DBC=0, SME=0, SCF=6 0xa4: 0x0000 (PREOP) 0xa6: 0x0000 (OPTYPE) 0xa8: 0x00000000 (OPMENU) 0xac: 0x00000000 (OPMENU+4) 0xc4: 0xf3d82005 (LVSCC) LVSCC: BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20, VCL=1 0xc8: 0x20452045 (UVSCC) UVSCC: BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20 Enabling hardware sequencing because some important opcode is locked. OK. The following protocols are supported: Programmer-specific. Probing for Programmer Opaque flash chip, 0 kB: Hardware sequencing reports 1 attached SPI flash chip with a density of 8192 kB. Found Programmer flash chip "Opaque flash chip" (8192 kB, Programmer-specific) mapped at physical address 0x0000000000000000. Found Programmer flash chip "Opaque flash chip" (8192 kB, Programmer-specific). No operations were specified. Restoring PCI config space for 00:1f:5 reg 0xdc === Additional info === - Specs sheet: The best I could find is this unofficial one for the 780, not the 780A, but they're extremely similar machines as far as I can tell. https://www.manua.ls/acer/aspire-tc-780/specifications - Other relevant info: None really. If anyone would like me to try something, feel free. This machine is running Arch Linux, so anything that can run on Linux should work fine. I also have an EFI Shell binary installed, **and the official BIOS flashing EFI script from Acer**.

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How to best handle new Intel Saphire Rapids server boards based on Intel Archer City?
by Paul Menzel 21 Jun '23

21 Jun '23

[Annie, Yiwei, I only added you to Cc. It’d be great if you made sure that all involved people are subscribed to the coreboot mailing list.] Dear coreboot folks, Two server boards based on Intel Archer City board, commit 30e743e7cc7f (mb/ibm: Add 4 SPR sockets server board IBM SBP1) [1], were pushed to Gerrit for review: 1. mb/inventec: Add Intel SPR server board Inventec Transformers [2] Change-Id: Ic9d99c3aadaa9f69e6d14d4b1a6c5157f5590684 2. bytedance/bd_egs (Eaglestream) [3] Change-Id: I091bc78e39cd76b3c6b9a10a1fcf58e9d671ef5d Some code seems to be copied – like bootblock.c [4] – and almost identical to the reference platform. To avoid future maintenance burden, could more knowledgeable people comment, if server boards differ drastically so separate boards are justified or if they should be made variants. I also noticed `mainboard_config_iio()`. Should that be moved to the devicetree? Kind regards, Paul [1]: https://review.coreboot.org/c/coreboot/+/73392 "mb/ibm: Add 4 SPR sockets server board IBM SBP1" [2]: https://review.coreboot.org/c/coreboot/+/75598 "mb/inventec: Add Intel SPR server board Inventec Transformers" [3]: https://review.coreboot.org/c/coreboot/+/75722 "mb/bytedance: Add 2 SPR sockets server board bd_egs" [4]: https://review.coreboot.org/c/coreboot/+/75598/5/src/mainboard/inventec/tra…

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coreboot June 2023