April 2023 - coreboot - mail.coreboot.org

[GSOC appplication] Contributor
by 이다영 April 3, 2023

April 3, 2023

My name is Dayoung Lee, and I am interested in becoming a contributor for the Coreboot project as a part of Google Summer of Code (GSoC). I am currently in my final year of university, majoring in Electronic Engineering. I have extensive project experience working with embedded systems. My background includes working with hardware in a Linux environment, as well as coding in Assembly and C languages. Additionally, I have hands-on experience with machine learning, specifically in object detection projects. My solid understanding of hardware concepts from my undergraduate studies will be a significant asset to this project. These experiences have led me to develop a strong interest in the Coreboot project. While browsing through potential projects, I found one that particularly caught my attention: Learn hardware behavior from I/O and memory access logs Although I am aware that it might be late in the application process, I am eager to seize this opportunity and contribute to the Coreboot project. I would be grateful if you could consider my application and give me a chance to participate. Thank you for considering my application, and I look forward to contributing to the Coreboot community. Best regards, Dayoung Lee

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GSoC 23 - Contributor Introduction
by Utkarsh Verma April 3, 2023

April 3, 2023

Dear all, My name is Utkarsh Verma and I am a final-year undergraduate student. I want to participate in this year's GSoC and contribute to coreboot. This is not the first time I've found out about the coreboot project. I stumbled upon it last year when I wished to change the BIOS on my laptop as the vendor BIOS is a bit buggy. Since coreboot didn't directly support my laptop, I wanted to work towards adding support for it. However, time and skill constraints forced me to leave it for later. Now, with GSoC around the corner, I believe is the perfect time for me to work towards this goal. I had a look at the list of projects, and found the following to be interesting, mentioned in decreasing order of preference: - Support Power9/Power8 in coreboot - Port edk2 or U-Boot payloads to ARM, AArch64 or RISC-V - Fix POST code handling I am completely new to coreboot, however, I do have experience with the Linux kernel compilation and patching process on Gentoo. I have familiarity with the Assembly language and have done various embedded projects for AVR microcontrollers. I would love to make contributions to the firmware side of coreboot, and on a personal level, it would be really fulfilling to use coreboot on my own machine once I become capable of adding support for it through this GSoC internship. I have mentioned my motivation and interests above, so please let me know if I might have misjudged a project or if some other project would be more fitting for me. Also, it would be really helpful if you could suggest some starter issues for which I could submit some patches. I have attached the serial output of the tutorial below as a plain text file, which you may check in any terminal using cat. Thank you for your time. Regards, Utkarsh Verma

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[coreboot - Bug #474] (New) X200s crashes after graphic init with 8GB RAM
by Bill XIE April 2, 2023

April 2, 2023

Issue #474 has been reported by Bill XIE. ---------------------------------------- Bug #474: X200s crashes after graphic init with 8GB RAM https://ticket.coreboot.org/issues/474 * Author: Bill XIE * Status: New * Priority: Normal * Category: board support * Target version: master * Start date: 2023-03-28 * Affected versions: master * Affected hardware: X200s ---------------------------------------- My X200s with panel LTD121EQ3B and 2x4GB identical RAM running a coreboot-4.19-937-g0b192d3238 built for X200, configured with the attached x200s.cfg, having the following contents, crashed with beeping after graphic init (screen lights), and before booting from the grub-based payload. ``` FMAP REGION: COREBOOT Name Offset Type Size Comp cbfs_master_header 0x0 cbfs header 32 none fallback/romstage 0x80 stage 69240 none cpu_microcode_blob.bin 0x10f80 microcode 49152 none fallback/ramstage 0x1cfc0 stage 130413 LZMA (297648 decompressed) config 0x3cdc0 raw 3019 LZMA (9596 decompressed) revision 0x3d9c0 raw 716 none build_info 0x3dcc0 raw 101 none fallback/dsdt.aml 0x3dd80 raw 14999 none cmos.default 0x41880 cmos_default 256 none cmos_layout.bin 0x419c0 cmos_layout 1696 none fallback/postcar 0x420c0 stage 33912 none data_ccfl.vbt 0x4a580 raw 1501 LZMA (3854 decompressed) data_led.vbt 0x4abc0 raw 1439 LZMA (3863 decompressed) (empty) 0x4b1c0 null 7140 none fallback/payload 0x4cdc0 simple elf 7123033 none (empty) 0x717e80 null 853028 none bootblock 0x7e82c0 bootblock 31488 none ``` This problem will disappear if I remove one DIMM, remove vbt files from CBFS, or enable EHCI debug with FT232H, which makes me unable to catch it. ---Files-------------------------------- x200s.cfg (9.36 KB) -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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Re: 440BX meminit changes testing
by Keith Hui April 2, 2023

April 2, 2023

Hi Branden, I think I know why 74034 is failing. Somehow the memory row sizes were messed up and the DRAM row boundaries were incorrectly set. I'm going back to my userspace test jig and see if I can get that going again, then go from there. I'll keep you guys (including anyone watching on the mailing list) posted. Regards Keith On Thu, 30 Mar 2023 at 19:05, Branden Waldner <scruffy99(a)gmail.com> wrote: > > I did some more testing of the patch train, but didn't manage to > figure out where it would boot but with an unstable config. > I skipped over 73887, since it was already merged (and master tests okay). > 73951, 73952, 74032, and 74033 booted and ran memtest for a few > minutes without errors > But 74034 would fail with or without debug raminit enabled. > > Most of this testing was done with the pair of 128mb capable of > 2-2-2-5 timings, but showing 3-3-3-6 as in use in memtest86.

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440BX meminit changes testing
by Branden Waldner April 1, 2023

April 1, 2023

Hi Keith So far I've only tested the complete patch train (73888) like previously mentioned and didn't have my serial console set up at the time. I dug out the cable from behind my desk and got it run to my work bench again, so that should help out. I'm assuming you would want logs with raminit debug enabled though and I didn't have that set last time. You had mentioned you wanted me to test 74036 specifically? I checked out the ram I was using with decode-dimms, but didn't check any other ram yet. It looks like they are both rated for CL3 @100mhz and the 133mhz stick seems to run at it's timings for 133 instead of 100? I'm running a 100mhz fsb coppermine cpu and the memory is supposed to run at the fsb speed right? It doesn't seem to use (or at least display it is using) the 100mhz timing on the oem bios either - though I haven't done enough testing to be confident of what's going on. I have some high density 256mb memory that runs at 128mb with this chipset, so I could check what the timings are on that yet. I really should have just tried to find a lot of 512mb high density to just fill out whatever sdram usage I could have. Branden

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