coreboot April 2023

coreboot@coreboot.org

31 participants
44 discussions

Supermicro X11SSH-LN4F PCI-e bifurcation?
by Tomas 13 Apr '23

13 Apr '23

Hi, I installed Coreboot with SeaBIOS on a Supermicro X11SSH-LN4F. The stock BIOS can read two NVMe drives in a Dual m.2 splitter card inserted in the middle slot 5 on the motherboard. But coreboot can not. In the coreboot nconfig menu there is no setting that will enable bifurcation of the x8 slot to x4x4. Is this something that is configurable in any way? /Tomas

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request for support new hardware from coreboot
by Artem 12 Apr '23

12 Apr '23

Hello Im Artem from Khadas https://www.khadas.com/ We developing new product our hardware based on: Alder Lake ULT 12th Gen Intel Core i7-1280P We have plans to use coreboot as alternative bootloader for our new product We need some information about: 1) coreboot possibilities for current hardware 2) estimated time to create some initial workable prototype 3) what information we need provide for your side at this moment we use BIOS from AMI: Vendor: Amerian Megatrends Core Verion: 5.27 Compiancy: UEFI 2.8; PI 1.7 etc... About us We are Shenzhen Wesion Technology Co., Ltd is the company that owns the brand "Khadas", our company was founded on 5 November 2014. We focus on developing, manufacturing and marketing single board computers (SBCs) ... more info https://www.khadas.com/about Best regards Artem

2 1

proposal for cross compilation: add Rust support
by ron minnich 07 Apr '23

07 Apr '23

https://review.coreboot.org/c/coreboot/+/74124 First step, which I almost certainly did incorrectly, is to add Rust toolchain support to the Makefile. Next, adding a rust payload was suggested. I'll look into that, probably rewriting linuxcheck in rust (since I'm the only user anyway :-)

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[coreboot - Bug #121] T520: Hangs in OS
by Evgeny Zinoviev 07 Apr '23

07 Apr '23

Issue #121 has been updated by Evgeny Zinoviev. On my x230 with gentoo, with recent kernel the situation has worsened significally. If on 5.x kernels it worked somewhat stable (I had crashes maybe once in a month or so and maybe it wasn't even coreboot related), now I after upgrade to 6.1.12-gentoo and it freezes like twice a day. This might be completely bug-121-unrelated, but limiting max cstate to c3 seems to fix the issue, so I decided to report here anyway... can anybody confirm the same? I mean that the newer kernel == more freezes/crashes ---------------------------------------- Bug #121: T520: Hangs in OS https://ticket.coreboot.org/issues/121#change-1466 * Author: Julz Buckton * Status: New * Priority: Normal * Start date: 2017-06-09 ---------------------------------------- I have been running coreboot since 2017.04.15 and have experienced hangs ever since then. It was suggested by folk on the IRC that I run memtest to check for incorrect raminit causing errors, however I have run memtest for 12 hours straight with no errors. Due to the ambiguous nature of the hangs (immediate freeze with no warning signs, audio gets stuck repeating the last 50ms or so of noise, not sure what this effect is called) I don't have much useful information other than the .config and dmesg. However one thing I can say with high confidence is that the hangs occur significantly more frequently in Linux (*buntu distros) than Windows 10. Within an hour of launching Linux a hang is likely, whereas Windows typically runs for many hours before a hang occurs. I considered this an insignificant anecdotal anomaly at first but over the course of the nearly 2 months I have been running coreboot it seems to be a solid trend. The hangs occur anywhere, typically during mere desktop usage or basic web browsing. Additionally there is another form of hang I experience where the screen goes black except for some sort of graphical corruption down the left side (http://i.imgur.com/4zWrlpX.jpg), whether this is related to the more common total freeze hangs I don't know but I figured I should include it nonetheless. These hangs only occur about 1:20 compared to the regular hangs. ---Files-------------------------------- config (20.7 KB) dmesg.txt (57.3 KB) cbmem-raminit.txt (62 KB) lspci.txt (29.6 KB) cpuinfo.txt (3.94 KB) defconfig (1023 Bytes) -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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[RFC] vboot recovery reason clearing
by Michał Żygowski 06 Apr '23

06 Apr '23

Hi coreboot folks, I have recently stumbled upon an issue that non-ChromeOS platforms, once entered into recovery mode, cannot leave this state, despite the RW partition being updated with correctly signed firmware copy. I.e. imagine situation where RW A (and B) is not valid, vboot logic causes to boot into recovery. Flash is updated with valid RW A (and B) but the vboot logic does not try to verify the RW partition, instead is stuck in recovery mode due to VBOOT NVRAM content. For ChromeOS platform the recovery reason is cleared in vb2api_kernel_phase2 but vb2api_kernel_phase2 is probably not used anywhere except depthcharge (or whatever is loading the ChromeOS kernel). So non-ChromeOS platform using vboot have no option to get out of recovery. Unless I am missing something, then please correct me. My suggestion would be to add vb2_clear_recovery to vb2api exposed to the coreboot and let the platform code decide when the recovery request should be cleared. Also coreboot can attempt to verify RW partition despite recovery reason, but it would probably be inefficient and lead to situations where recovery mode should be entered, but wasn't entered. Dear ChromeOS firmware experts, your opinion is highly appreciated. Best regards, -- Michał Żygowski Firmware Engineer GPG: 6B5BA214D21FCEB2 https://3mdeb.com | @3mdeb_com

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Coffeelake Graphics Problem
by cagatay bagci 05 Apr '23

05 Apr '23

Hello all,I have a custom CFL board. I used Tianocore UEFI payload. It boots without problem on console and I can enter BIOS menu. I put appropriate vbt.bin file and added that path to config file, so VBT exists. However, I cannot get display output. I inspected debug log and it says "graphics hand-off block not found" in one line. I understand that FSP does not build "gEfiGraphicsInfoHobGuid". Do you have an idea why FSP does not produce that HOB? In addition to that, by using FSP debug binary, I can see that FSP does not even enter PeiGraphicsEntryPoint. It somehow quits after "SerialIoInit() Start" and notifys Post PCI Enumeration. Thanks,

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How can I set up a userspace test for coreboot code in 2023?
by Keith Hui 04 Apr '23

04 Apr '23

Years ago when I first wrote the 440BX ram init code, I also wrote a test program that would read some SPD dump files and set up a simulated environment to run my ram init code in, without actually flashing a chip. I now have to do it again and I can't seem to get it to work again. Maybe the build system has changed since then. I am looking to just compile this program and nb/intel/i440bx/raminit.c (unmodified beyond patches I'm testing) and link them together for an executable to run from the command line. Here is the command line I figured would work, gathered with "make -n": gcc -Isrc -Isrc/include -Isrc/commonlib/include -Isrc/commonlib/bsd/include -Ibuild -I3rdparty/vboot/firmware/include -include src/include/kconfig.h -include src/include/rules.h -include src/commonlib/bsd/include/commonlib/bsd/compiler.h -I3rdparty -D__BUILD_DIR__=\"build\" -Isrc/arch/x86/include -D__ARCH_x86_32__ -Isrc/device/oprom/include -nostdinc -pipe -g -std=gnu11 -nostdlib -Wall -Wundef -Wstrict-prototypes -Wmissing-prototypes -Wwrite-strings -Wredundant-decls -Wno-trigraphs -Wimplicit-fallthrough -Wshadow -Wdate-time -Wtype-limits -Wvla -Wold-style-definition -Wdangling-else -Wmissing-include-dirs -fno-common -ffreestanding -fno-builtin -fomit-frame-pointer -fstrict-aliasing -ffunction-sections -fdata-sections -fno-pie -Wno-packed-not-aligned -fconserve-stack -Wnull-dereference -Wreturn-type -Wlogical-op -Wduplicated-cond -Wno-unused-but-set-variable -Werror -Os -Wno-address-of-packed-member -m32 -fuse-ld=bfd -fno-stack-protector -Wl,--build-id=none -fno-delete-null-pointer-checks -Wlogical-op -march=i686 -mno-mmx --param asan-globals=0 -D__RAMSTAGE__ -include build/config.h src/northbridge/intel/i440bx/raminit.c src/northbridge/intel/i440bx/raminittest.c -o raminittest2023 The C test code is attached. Any suggestions is appreciated. Thanks Keith

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introduction/potential GSoC Application
by Daniel Rosa Franzini 04 Apr '23

04 Apr '23

hello, all I'm Daniel, from São Paulo/Brazil. I'm a 40yr-old software engineer who just got back to school to finish my undergraduate degree in EE (after a couple of years working in the embedded software industry). I'm canditating myself to do this task: Fully support building coreboot with the Clang compiler There is no explicit mentor in the page, so I'm writing here. I will be a candidate for a GSoC project. Is someone willing to be my mentor? I know it is near dearline but, well, I think it is worth giving it a try anyway. Thanks in advance.

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Introduction as GSoC applicant
by Philipp Macher 04 Apr '23

04 Apr '23

Hi dear Coreboot@ list, my name is Philipp and a am applying for the Google Summer of Code to work at Coreboot. I first thought of working on Power8/9 support, but I think that it would take a while until I could help you at all with this, so maybe I will try to contribute there after the GSoC when I know the rest of Coreboot better. So I applied to work at supporting zlib as a compression algorithm and maybe update lz4 and lzma, if needed. Feel free to tell me if you have any comments/suggestions regarding this project. About myself, I am currently studying for my Bachelor's Degree in CS in Darmstadt, Germany, since 2020. If I'm not working or studying, I do some IoT and soldering things, because I like low-level microcontroller and blinky-blinky stuff. ESPecially on ESP32 boards. I also pushed a first commit, doing some linter fixing, if you want to check it out [0]. Regards, Philipp [0] https://review.coreboot.org/c/coreboot/+/74173

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[GSOC appplication] Contributor
by 이다영 03 Apr '23

03 Apr '23

My name is Dayoung Lee, and I am interested in becoming a contributor for the Coreboot project as a part of Google Summer of Code (GSoC). I am currently in my final year of university, majoring in Electronic Engineering. I have extensive project experience working with embedded systems. My background includes working with hardware in a Linux environment, as well as coding in Assembly and C languages. Additionally, I have hands-on experience with machine learning, specifically in object detection projects. My solid understanding of hardware concepts from my undergraduate studies will be a significant asset to this project. These experiences have led me to develop a strong interest in the Coreboot project. While browsing through potential projects, I found one that particularly caught my attention: Learn hardware behavior from I/O and memory access logs Although I am aware that it might be late in the application process, I am eager to seize this opportunity and contribute to the Coreboot project. I would be grateful if you could consider my application and give me a chance to participate. Thank you for considering my application, and I look forward to contributing to the Coreboot community. Best regards, Dayoung Lee

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coreboot April 2023