coreboot September 2020

coreboot@coreboot.org

31 participants
22 discussions

Coreboot on asus KGPE-D16 - Black screen
by Ale 16 Sep '20

16 Sep '20

Hello, I have an Asus kgpe-d16 with 2 AMD opteron 6282 SE installed; obviously, since I had the first stock bios version the screen was black and no boot occurs because CPUs are not supported. So I have ordered a coreboot bios DIP and I have installed it but nothing has changed, same behaviour (only black screen and no sound, only fans starts). Can someone have some idea? I even try to log with the serial port but no log is shown at all... P.S. Could it be that one of the CPUs is broken? Or that something went wrong during the flashing procedure over the DIP? Is there a way to check that the DIP is ok and with coreboot? Thank you very much!

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NVME is not detecting.
by techmindams04＠gmail.com 15 Sep '20

15 Sep '20

I have ported coreboot on Coffeelake architecture. Coreboot is up and during PCI scan M.2 NVME is not detecting in the scan. I have enabled the root port (Port 9) in the device tree and root port is shown in enumeration but not NVME device under it. Is there any configuration to be done in coreboot to detect NVME. Regards, SenK.

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Re: Thinkpad T410 flashing questions
by Stéphane Delaunay 14 Sep '20

14 Sep '20

Hey Peter, Thanks again for your elaboration, I've had a go at this last weekend, or at least, I tired to. On Tuesday, September 1, 2020 1:37 PM, Peter Stuge <peter(a)stuge.se> wrote: > I haven't used it myself because soldering is easy for me, but apparently > at least one person had success with the GPIO33 method. I wasn't able to locate those traces from the top. To get a full view of the board, you'd have to remove the CPU heatsink and take it out of the frame, so I don't really understand how you would do this while powering on the system, it would probably overheat immediately. Unfortunately, I don't have a heat gun at hand to desolder the chip either, so I'm considering just doing a dirty ISP and seeing where I can get. Unless there's some other way to disconnect the linked components? But I can't really think of one.

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coreboot Compiling Error
by Andrew Lee 13 Sep '20

13 Sep '20

Hello, when I tried to compile coreboot it gave me this error message. https://pastebin.com/raw/mK9jc5eX

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Haswell hang in cbmem_top_init_once
by sfsdfu sddfss 12 Sep '20

12 Sep '20

I'm trying to port coreboot to HP EliteDesk 800 G1 DM，using master branch with commit hash 70fea013c7ebd6d85a7806748233fcfd76802f5f，and mrc.bin from Chromebook peppy. Then I get the following boot log by EHCI debug serial，it hang in cbmem_top_init_once. Adding debug print shows cbmem_top points to 7f800000. LPC debug card also stop on 0x3b. I have no idea how to debug. Any help would be appreciated. @@ -55,8 +55,11 @@ static void cbmem_top_init_once(void) return; /* The test is only effective on X86 and when address hits UC memory. */ - if (ENV_X86) - quick_ram_check_or_die((uintptr_t)cbmem_top() - sizeof(u32)); + if (ENV_X86) { + uintptr_t cbmem_top_p = (uintptr_t)cbmem_top(); + printk(BIOS_DEBUG, "CBMEM top: %08lx ", cbmem_top_p); + quick_ram_check_or_die(cbmem_top_p - sizeof(u32)); + } } coreboot-4.12-2693-g0c1e8f44ec-dirty Sat Sep 12 11:15:18 UTC 2020 bootblock starting (log level: 8)... FMAP: area COREBOOT found @ e30200 (1900032 bytes) CBFS: Locating 'fallback/romstage' CBFS: Found @ offset 80 size 1827c BS: bootblock times (exec / console): total (unknown) / 8 ms coreboot-4.12-2693-g0c1e8f44ec-dirty Sat Sep 12 11:15:18 UTC 2020 romstage starting (log level: 8)... Disabling Watchdog reboot... done. SMBus controller enabled Setting up static northbridge registers... done. Started PEG10 link training. Temporarily hiding PEG10. Initializing IGD... Back from haswell_early_initialization() POST: 0x3a CPU id(306c3) ucode:00000028 Intel(R) Pentium(R) CPU G3240 @ 3.10GHz AES NOT supported, TXT NOT supported, VT supported PCH type: Q87, device id: 8c4e, rev id 5 Starting UEFI PEI System Agent FMAP: area RW_MRC_CACHE found @ e20000 (65536 bytes) MRC: no data in 'RW_MRC_CACHE' FMAP: area COREBOOT found @ e30200 (1900032 bytes) CBFS: Locating 'mrc.bin' CBFS: Found @ offset 16fdc0 size 2e6e4 System Agent: Starting up... System Agent: Initializing PCH install_ppi: overwrite GUID {ed097352-9041-445a-80b6-b29d509e8845} install_ppi: overwrite GUID {908c7f8b-5c48-47fb-8357-f5fd4e235276} System Agent: Initializing PCH (SMBUS) System Agent: Initializing PCH (USUSB System Agent Version 1.6.1 Build 2 memcfg DDR3 clock 1333 MHz memcfg channel assignment: A: 1, B 0, C 2 memcfg channel[0] config (00600000): ECC inactive enhanced interleave mode on rank interleave on DIMMA 0 MB width x8 or x32 single rank, selected DIMMB 0 MB width x8 or x32 single rank memcfg channel[1] config (00600010): ECC inactive enhanced interleave mode on rank interleave on DIMMA 4096 MB width x8 or x32 single rank, selected DIMMB 0 MB width x8 or x32 single rank POST: 0x3b ME: FW Partition Table : OK ME: Bringup Loader Failure : NO ME: Firmware Init Complete : NO ME: Manufacturing Mode : YES ME: Boot Options Present : NO ME: Update In Progress : NO ME: Current Working State : Initializing ME: Current Operation State : Bring up ME: Current Operation Mode : Debug ME: Error Code : No Error ME: Progress Phase : BUP Phase ME: Power Management Event : Pseudo-global reset ME: Progress Phase State : 0x4d CBMEM top: 7f800000

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Re: CoffeeLake RVP master: Code changed... How to enable SATA and LAN?
by techmindams04＠gmail.com 12 Sep '20

12 Sep '20

Hey Jose, I am facing the same issue on Coffeelake RVP. Have you resolved it. If so let me know how to do it. Regards, SenK

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[RFC] Proposal to move all FSP 1.x binaries to "legacy" branch
by Desimone, Nathaniel L 09 Sep '20

09 Sep '20

Hi Everyone, Given that the newest coreboot releases have not supported the FSP 1.x specification for years now, seems that the 1.x FSP binaries at https://github.com/intel/FSP have become increasingly limited in their usefulness. For this reason, I would like to move those older binaries off master branch and create a new “legacy” branch to store them. I'll be sure to mention the legacy branch in the readme.md file in master. Any concerns with this change? Thanks, Nate

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New Defects reported by Coverity Scan for coreboot
by scan-admin＠coverity.com 08 Sep '20

08 Sep '20

Hi, Please find the latest report on new defect(s) introduced to coreboot found with Coverity Scan. 1 new defect(s) introduced to coreboot found with Coverity Scan. New defect(s) Reported-by: Coverity Scan Showing 1 of 1 defect(s) ** CID 1432491: Error handling issues (CHECKED_RETURN) /src/mainboard/google/volteer/mainboard.c: 46 in mainboard_update_soc_chip_config() ________________________________________________________________________________________________________ *** CID 1432491: Error handling issues (CHECKED_RETURN) /src/mainboard/google/volteer/mainboard.c: 46 in mainboard_update_soc_chip_config() 40 dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; 41 dev->ops->get_smbios_strings = mainboard_smbios_strings; 42 } 43 44 void mainboard_update_soc_chip_config(struct soc_intel_tigerlake_config *cfg) 45 { >>> CID 1432491: Error handling issues (CHECKED_RETURN) >>> Calling "tlcl_lib_init" without checking return value (as is done elsewhere 10 out of 11 times). 46 tlcl_lib_init(); 47 if (cr50_is_long_interrupt_pulse_enabled()) { 48 printk(BIOS_INFO, "Enabling S0i3.4\n"); 49 } else { 50 /* 51 * Disable S0i3.4, preventing the GPIO block from switching to ________________________________________________________________________________________________________ To view the defects in Coverity Scan visit, https://u15810271.ct.sendgrid.net/ls/click?upn=HRESupC-2F2Czv4BOaCWWCy7my0P…

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Intel DCI-DbC on Skylake-U
by Benjamin Doron 07 Sep '20

07 Sep '20

Hi all, Does Skylake-U support DCI over USB3-DbC (standard USB 3.0 debug cable), or only with the SVT-CCA? I've seen conflicting information on this matter. In my attempts (using USB3-DbC), Intel System Debugger was able to successfully identify only the PCH as a "custom" configuration, but just once (perhaps due to an issue with the host, but now, the "Target Indicator" indicates an "access error"). Debugging the PCH is not very useful to me, but as far as I can tell, my board (an Acer Aspire VN7-572G laptop) should be compatible with DCI in general. I'm not certain what I'm looking to see on the schematics or boardview, but I think that the CPU and PCH JTAG lines are connected. The ME also permits CPU debugging (if it's relevant, Boot Guard is disabled). Thanks for any and all help, Benjamin Doron

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Re: [coreboot]: Help request with SMSC SCH3114 superio.
by Jose Trujillo 02 Sep '20

02 Sep '20

Dear Michal, I am sorry for the late reply but on Friday something went wrong with my coreboot installation and was unable to boot and I have to reinstall it again and I just resumed this morning on this issue. (you) don't think loading the watchdog module will help in any way, actually the opposite. (Me) I did the modprobe of the watchdog module just to ask linux to give me the base address of the runtime registers "0xa00" of the original bios. (you) I recommend using https://github.com/adurbin/iotools (you) Superiotool will simply dump all registers and may alternatively dump IO too. (Me) Thank you for your great advice I will go by the Superiotool route (patching it) but so far I am dumping using "ioports" in the following way: on root: for i in $(seq 0xa00 0xa7f); do echo -n "$i: "; inb $i; done; $i = $((++i)) (you) I assume you have configured runtime registers IOBASE right? (Me) I found out (because of your advise) that the runtime registers base address was wrong on my devicetree (0xe00 instead 0xa00) I set it correctly then linux was able to "see" this range and dumped the registers with the string shown above. Now I can compare both dumps and I can see the pins for the UART ports 2-4 are all GPIO inputs (1). (Me) I set manually the GPIOs from linux using ioport's function outb and all the 4 ports work correctly. Now I am trying to set from coreboot but I am still unsuccessful. Looking at you dell Optiplex 9010 you set the following runtime registers under romstage.c -> mainboard_early_init /* Disable SMIs and clear SMI status */ outb(0, SCH5545_RUNTIME_REG_BASE + SCH5545_RR_SMI_EN); outb(SCH5545_SMI_GLOBAL_STS, SCH5545_RUNTIME_REG_BASE + SCH5545_RR_SMI_STS); and I do similar to you under romstage.c -> mainboard_early_init: outb(0x55, 0x2e); outb(0x05, 0x0a3f); /* GP50= RI_2 : in */ outb(0x05, 0x0a40); /* GP51= DCD_2 : in */ outb(0x05, 0x0a41); /* GP52= RXD_2 : in */ outb(0x04, 0x0a42); /* GP53= TXD_2 : out */ outb(0x05, 0x0a43); /* GP54= DSR_2 : in */ outb(0x04, 0x0a44); /* GP55= RTS_2 : out */ outb(0x05, 0x0a45); /* GP56= CTS_2 : in */ outb(0x04, 0x0a46); /* GP57= DTR_2 : out */ outb(0xaa, 0x2e); but It doesn't work. Also I set the same code under mainboard.c -> mainboard_init but neither work. Any advice on this? because I cannot find any information on the datasheet on how to set those registers and I suppose I just have to set to the 0xa00 base address + register. Thank you, Jose Trujillo.

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coreboot September 2020