coreboot July 2020

coreboot@coreboot.org

46 participants
42 discussions

ThinkPad T420 and FireWire chip on Linux
by Alesandar Metodiev 09 Apr '22

09 Apr '22

Hello, Recently I have decided to give a try to coreboot for first time and flashed my ThinkPad T420, but a few weeks ago I have swapped the USB controller on the back, next to the battery, with a FireWire/USB controller (40GAB5809-G200) from another T420. Nothing special, since some models have been shipped like this. The controller is no longer accessible on my laptop. It seems like it may have been detected as an "SD Host Controller" or not detected at all. I will probably have to remove the chip and compare the output of lspci and lshw. If nothing has changed, I will probably have to return the stock BIOS and compare the results again. I have also tried to load some of the firewire kernel modules manually with modprobe. The operating systems I have tested so far are Arch Linux and Xubuntu. I am willing to provide more useful information, boot into a fresh Windows install, flash the chip again or whatever else. Correct me if I am wrong, but if I go back to the stock BIOS, the next time I flash, I will have to disassemble the laptop again and otherwise I must be fine with flashing internally, right? Thanks

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How to choose my ‘‘mainboard vendor’’ for Sony laptops?
by hd-scania＠users.sf.net 02 Aug '20

02 Aug '20

Laptop model: Sony VPCCB17FG Cores: Intel i7-2620M Coreboot release to be flashed: 4.12 RAM’s: 7.45GiB Graphics: AMD Radeon Old BIOS: By AMI, versioned R0242v2 (no longer receiving Sony’s BIOS upgrades since 2012) Mainboard vendor 1. 51NB (VENDOR_51NB) (NEW) 2. ADLINK (VENDOR_ADLINK) (NEW) 3. AMD (VENDOR_AMD) (NEW) 4. AOpen (VENDOR_AOPEN) (NEW) 5. Apple (VENDOR_APPLE) (NEW) 6. ASROCK (VENDOR_ASROCK) (NEW) 7. ASUS (VENDOR_ASUS) (NEW) 8. BAP (VENDOR_BAP) (NEW) 9. Biostar (VENDOR_BIOSTAR) (NEW) 10. Cavium (VENDOR_CAVIUM) (NEW) 11. CompuLab (VENDOR_COMPULAB) (NEW) 12. ELMEX (VENDOR_ELMEX) (NEW) > 13. Emulation (VENDOR_EMULATION) (NEW) 14. Facebook (VENDOR_FACEBOOK) (NEW) 15. Foxconn (VENDOR_FOXCONN) (NEW) 16. Getac (VENDOR_GETAC) (NEW) 17. GIGABYTE (VENDOR_GIGABYTE) (NEW) 18. GizmoSphere (VENDOR_GIZMOSPHERE) (NEW) 19. Google (VENDOR_GOOGLE) (NEW) 20. HP (VENDOR_HP) (NEW) 21. iBase (VENDOR_IBASE) (NEW) 22. Intel (VENDOR_INTEL) (NEW) 23. Jetway (VENDOR_JETWAY) (NEW) 24. Kontron (VENDOR_KONTRON) (NEW) 25. Lenovo (VENDOR_LENOVO) (NEW) 26. Libretrend (VENDOR_LIBRETREND) (NEW) 27. LiPPERT (VENDOR_LIPPERT) (NEW) 28. MSI (VENDOR_MSI) (NEW) 29. Open Compute Project (VENDOR_OCP) (NEW) 30. OpenCellular (VENDOR_OPENCELLULAR) (NEW) 31. Packard Bell (VENDOR_PACKARDBELL) (NEW) 32. PC Engines (VENDOR_PCENGINES) (NEW) 33. Portwell (VENDOR_PORTWELL) (NEW) 34. Protectli (VENDOR_PROTECTLI) (NEW) 35. Purism (VENDOR_PURISM) (NEW) 36. RAZER (VENDOR_RAZER) (NEW) 37. Roda (VENDOR_RODA) (NEW) 38. SAMSUNG (VENDOR_SAMSUNG) (NEW) 39. Sapphire (VENDOR_SAPPHIRE) (NEW) 40. Scaleway (VENDOR_SCALEWAY) (NEW) 41. Siemens (VENDOR_SIEMENS) (NEW) 42. SiFive (VENDOR_SIFIVE) (NEW) 43. Supermicro (VENDOR_SUPERMICRO) (NEW) 44. System76 (VENDOR_SYSTEM76) (NEW) 45. TI (VENDOR_TI) (NEW) 46. UP (VENDOR_UP) (NEW) choice[1-46]:

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New Defects reported by Coverity Scan for coreboot
by scan-admin＠coverity.com 31 Jul '20

31 Jul '20

Hi, Please find the latest report on new defect(s) introduced to coreboot found with Coverity Scan. 1 new defect(s) introduced to coreboot found with Coverity Scan. New defect(s) Reported-by: Coverity Scan Showing 1 of 1 defect(s) ** CID 1353302: (OVERRUN) /3rdparty/chromeec/chip/stm32/keyboard_raw.c: 74 in keyboard_raw_drive_column() /3rdparty/chromeec/chip/stm32/keyboard_raw.c: 83 in keyboard_raw_drive_column() /3rdparty/chromeec/chip/stm32/keyboard_raw.c: 71 in keyboard_raw_drive_column() /3rdparty/chromeec/chip/stm32/keyboard_raw.c: 66 in keyboard_raw_drive_column() ________________________________________________________________________________________________________ *** CID 1353302: (OVERRUN) /3rdparty/chromeec/chip/stm32/keyboard_raw.c: 74 in keyboard_raw_drive_column() 68 69 if (out == KEYBOARD_COLUMN_ALL) { 70 /* drive low (clear bit) */ 71 bsrr |= gpio_list[j].mask << 16; 72 } else if (out == KEYBOARD_COLUMN_NONE) { 73 /* put output in hi-Z state (set bit) */ >>> CID 1353302: (OVERRUN) >>> Overrunning array "gpio_list" of 41 16-byte elements at element index 47 (byte offset 767) using index "j" (which evaluates to 47). 74 bsrr |= gpio_list[j].mask; 75 } else if (j - GPIO_KB_OUT00 == out) { 76 /* 77 * Drive specified output low, others => hi-Z. 78 * 79 * To avoid conflict, tri-state all outputs /3rdparty/chromeec/chip/stm32/keyboard_raw.c: 83 in keyboard_raw_drive_column() 77 * Drive specified output low, others => hi-Z. 78 * 79 * To avoid conflict, tri-state all outputs 80 * first, then assert specified output. 81 */ 82 keyboard_raw_drive_column(KEYBOARD_COLUMN_NONE); >>> CID 1353302: (OVERRUN) >>> Overrunning array "gpio_list" of 41 16-byte elements at element index 47 (byte offset 767) using index "j" (which evaluates to 47). 83 bsrr |= gpio_list[j].mask << 16; 84 done = 1; 85 break; 86 } 87 } 88 /3rdparty/chromeec/chip/stm32/keyboard_raw.c: 71 in keyboard_raw_drive_column() 65 for (j = GPIO_KB_OUT00; j <= GPIO_KB_OUT12; j++) { 66 if (gpio_list[j].port != kb_out_ports[i]) 67 continue; 68 69 if (out == KEYBOARD_COLUMN_ALL) { 70 /* drive low (clear bit) */ >>> CID 1353302: (OVERRUN) >>> Overrunning array "gpio_list" of 41 16-byte elements at element index 47 (byte offset 767) using index "j" (which evaluates to 47). 71 bsrr |= gpio_list[j].mask << 16; 72 } else if (out == KEYBOARD_COLUMN_NONE) { 73 /* put output in hi-Z state (set bit) */ 74 bsrr |= gpio_list[j].mask; 75 } else if (j - GPIO_KB_OUT00 == out) { 76 /* /3rdparty/chromeec/chip/stm32/keyboard_raw.c: 66 in keyboard_raw_drive_column() 60 61 for (i = 0; i < ARRAY_SIZE(kb_out_ports); i++) { 62 uint32_t bsrr = 0; 63 int j; 64 65 for (j = GPIO_KB_OUT00; j <= GPIO_KB_OUT12; j++) { >>> CID 1353302: (OVERRUN) >>> Overrunning array "gpio_list" of 41 16-byte elements at element index 47 (byte offset 767) using index "j" (which evaluates to 47). 66 if (gpio_list[j].port != kb_out_ports[i]) 67 continue; 68 69 if (out == KEYBOARD_COLUMN_ALL) { 70 /* drive low (clear bit) */ 71 bsrr |= gpio_list[j].mask << 16; ________________________________________________________________________________________________________ To view the defects in Coverity Scan visit, https://u15810271.ct.sendgrid.net/ls/click?upn=HRESupC-2F2Czv4BOaCWWCy7my0P…

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will my machine support coreboot ?
by Nihar Khuntia 30 Jul '20

30 Jul '20

Hi Developers, my laptop has hardwares details as attached in this email. will it support coreboot ? regards nihar

4 3

Externally flashing Coreboot using microSD as external programmer
by HD Scania 30 Jul '20

30 Jul '20

As my title suggests, what to be prepared for _‘‘externally’’_ flashing Coreboot on a microSD? If external flash is done, *what* to be prepared to port Coreboot for my Sony VPCCB17FG laptop, with known supported Intel *HM65* chipsets, but even the vendor, Sony, is *unknown* to be supported or not? Are there any up-to-date wikies or docs on committing like this? > (Reference: https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/thread/62E6…)

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Porting Coreboot without Intel FSP
by Alif Ilhan 28 Jul '20

28 Jul '20

Pardon me for absurd questions, I am a noob. Is there any way to port coreboot to my netbook without Intel FSP. Or is there any way I could generate Intel FSP for my netbook? My netbook has Intel Atom N2600 CPU which doesn't seem to have any Intel FSP available. Please, if there is any guide to port coreboot to a new device WITHOUT Intel FSP, tell me about it. And can you tell me the difference between Coreboot and U-Boot and how each one is different from the other? Thanks Alif

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[RFC] Whether to drop Kconfig option TRACE
by Kyösti Mälkki 28 Jul '20

28 Jul '20

Hi Looks like option TRACE=y would need either someone to make it usable again or have it face removal. I did not really try the feature either, but it appears it would log function entry point addresses after relocation, which makes them not helpful at all. Having it enabled also blocks some functions from being inlined and evaluated to false at build time, this again makes some configurations fail due to unresolved symbols [1]. Regards, Kyösti [1] https://review.coreboot.org/c/coreboot/+/43870

1 0

FIT table contains microcode update files with size 0
by Paul Menzel 27 Jul '20

27 Jul '20

Dear coreboot folks, Making a Kaby Lake-U variant port [1], building an image, I notice the log say the microcode update files sizes in the FIT table are 0. > Platform is: sklkbl > File build/coreboot.pre is 16777216 bytes > IFDTOOL me.bin -> coreboot.pre > Platform is: sklkbl > File build/coreboot.pre is 16777216 bytes > File me.bin is 3141632 bytes > Adding me.bin as the Intel ME section of build/coreboot.pre > Writing new image to build/coreboot.pre > IFDTOOL Unlocking Management Engine > Platform is: sklkbl > File build/coreboot.pre is 16777216 bytes > Writing new image to build/coreboot.pre > IFDTOOL Setting EM100 mode > Platform is: sklkbl > File build/coreboot.pre is 16777216 bytes > Writing new image to build/coreboot.pre > CBFS coreboot.rom > UPDATE-FIT > > FIT table: > Index Type Addr Size > 0 Microcode 0xffb5b710 0x00000000 > 1 Microcode 0xffb73f10 0x00000000 > 2 Microcode 0xffb8c710 0x00000000 > > CBFSLAYOUT coreboot.rom Kind regards, Paul [1]: https://review.coreboot.org/c/coreboot/+/43760 "mb/clevo/kbl-u: Add Clevo N240BU as variant"

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New Defects reported by Coverity Scan for coreboot
by scan-admin＠coverity.com 24 Jul '20

24 Jul '20

Hi, Please find the latest report on new defect(s) introduced to coreboot found with Coverity Scan. 1 new defect(s) introduced to coreboot found with Coverity Scan. New defect(s) Reported-by: Coverity Scan Showing 1 of 1 defect(s) ** CID 1430578: Integer handling issues (CONSTANT_EXPRESSION_RESULT) /src/security/intel/stm/SmmStm.c: 359 in validate_resource() ________________________________________________________________________________________________________ *** CID 1430578: Integer handling issues (CONSTANT_EXPRESSION_RESULT) /src/security/intel/stm/SmmStm.c: 359 in validate_resource() 353 resource->mem.base, 354 resource->mem.length); 355 356 if (resource->header.length != sizeof(STM_RSC_MEM_DESC)) 357 return false; 358 >>> CID 1430578: Integer handling issues (CONSTANT_EXPRESSION_RESULT) >>> "resource->mem.rwx_attributes > 7" is always false regardless of the values of its operands. This occurs as the logical operand of "if". 359 if (resource->mem.rwx_attributes > FULL_ACCS) 360 return false; 361 break; 362 363 case IO_RANGE: 364 case TRAPPED_IO_RANGE: ________________________________________________________________________________________________________ To view the defects in Coverity Scan visit, https://u15810271.ct.sendgrid.net/ls/click?upn=HRESupC-2F2Czv4BOaCWWCy7my0P…

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Coreboot on Samsung Kevin
by r＠k-ze.ro 23 Jul '20

23 Jul '20

Hey guys, i'm stumped and getting not much ideas on #coreboot on this. I bought an ssd-bricked samsung kevin and want to compile coreboot for it to make it boot arch from sd without crossystem flags set. My image compiles fine with the following hacks: use latest vboot, pin chromeec to commit before kevin support was dropped. I got an ec.bin to put into coreboot and enabled ELOG because i miss UART. The image boots after 2-3 reboots with a red stripe (this happens even without included ec.bin): https://i.imgur.com/qXA4hvI.jpg I take from it that basic init works. ELOG paste in hex is here: https://bpa.st/MYPQ - i cannot make any sense out of it. My menuconfig options should be kinda fine, i used boardname kevin where applicable and copied config.gru to config.kevin for libpayload. kevin has a soldered on servo header, but i will not be able to get my hands on a servo board from google, so i might try basic UART (no idea what this means honestly). I like ARM architecture and would like to open similiar designs to https://github.com/SolidHal/PrawnOS Any ideas are appreciated! Thanks, R

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coreboot July 2020