coreboot June 2020

coreboot@coreboot.org

36 participants
38 discussions

Re: Query regarding coreboot
by Keith Hui 08 Jun '20

08 Jun '20

To answer the original question, I think not. Not on its own. macOS needs Clover. Clover needs UEFI. UEFI means Tianocore for payload. So coreboot+Tianocore+Clover, where Clover would be handled like any other bootloader eg. grub. I'm not sure if there porting Clover as a coreboot payload is necessary, practical, or even possible. At the very least it is a lot of work. Regards Keith > coreboot doesn't boot the OS, it performs hardware initialization and passes control to a payload (SeaBIOS, GRUB, Tianocore, etc. - these are payloads). So you would have to use something like clover anyway. > > On 6/8/20 6:22 PM, lol wrote: > > Hi, I wanted to ask if coreboot is capable of booting macOS. There are bootloaders like clover and opencore that does the job but does coreboot do this thing with more efficiency?

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Query regarding CoreBoot
by lol 08 Jun '20

08 Jun '20

Hi, I wanted to ask if coreboot is capable of booting macOS. There are bootloaders like clover and opencore that does the job but does coreboot do this thing with more efficiency?

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Status of Supermicro X11 series?
by Stéphane Delaunay 07 Jun '20

07 Jun '20

Hi all, I just wanted to ask about the current status of the Supermicro X11-series of boards. I read on a German magazine that it should be supported by joint efforts of 9elements and Mullvad. Link (auto-translated): https://translate.google.com/translate?hl=&sl=de&tl=en&u=https%3A%2F%2Fwww.… Apparently there was a presentation planned at the OSFC 2019, but I can't find anything on it and the boards-list still shows them as status "Unknown", which seems odd. Does somebody have any infos on the current development with these boards? Kind regards!

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win10: Interrupt number is minus?
by Zheng Bao 05 Jun '20

05 Jun '20

Maybe it is not a 100% suitable quesion. I assume big boys in coreboot know this. [cid:1fe4e7e2-ae0a-4631-8340-d284b41a2f9d] When I check the interrupt of network device in Windows 10, it says the IRQ is 0xFFFFFFDC(-36). I am confused about this minus. What does it mean? Is it MSI? Thanks. Zheng

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Self-describing CBFS features
by Jeremy Jackson 05 Jun '20

05 Jun '20

Hello Coreboot, I am looking at upgrading a Lenovo T60 that has a 4 year old Libreboot installed. Looking to try git master today, I find myself tracking down some details of how the old version was built. While the included .config is invaluable, I'm getting a few ideas for improvements. -CBFS total size, visible in bootblock. Some platforms do not have the entire flash chip address space decoded after power on reset. While this could be inferred from knowledge of make and model, a reliable and generic test would use a marker in the bootblock (and possibly something at the start of the flash part can be probed to confirm the mapping), at least for platforms where the reset vector it at top of (flash) memory. I haven't thought out the details but probably something can be made for low address reset vector platforms. Perhaps a flag in CBFS header to indicate which as a clue to cbfstool. Being size aware could also be used when swapping a flash chip to a different size. -the .config is overwritten when added to coreboot.rom via CBFS at the end of the build (if you choose that option)... should this be a separate file for each of fallback and normal? Since there can be two different versions and/or configurations, would fallback/config and normal/config make more sense? Also the "revision" file might benefit from similar treatment. Need to look into cmos* files also. -similarly, platforms with a top-swap like Intel, could have 2 different bootblock versions, so perhaps a subset of .config relevant to bootblock, and a version marker, could go in the same swap-block as each bootblock? -embed the top-swap feature presence, and block size. I haven't checked the code, but the cbfstool -j topswap-size and --ibb features are related, if they don't implement this already. CBFS files should optionally not span these block boundaries. -embed flash chip relative offset, in bootblock (of each top-swap area), to be able to probe if top-swap is active at any given moment. -flash erase block size could be indicated in CBFS header. This can have 2 uses, a) for alignment and padding when adding files, and b) when flashing for a different part, to detect when cbfs should be rebuilt with new padding and alignment. These may not be of use yet, but I can envision an enhanced "flashrom -i <layoutfile>" that uses a libcbfs to flash individual files, which would benefit knowing the erase size the supplied CBFS was build for. Perhaps each should be discussed in a separate thread, I'll leave that to others' discretion. Regards, Jeremy

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How to delete another me?
by Zheng Bao 05 Jun '20

05 Jun '20

Hi, admin of gerrit, I tried to add my working mail address zheng.bao(a)amd.com<mailto:zheng.bao@amd.com> to my gerrit account. But it says it is used by another account. I am pretty sure that is because I tried to use this mail address to create an account, but can not login by authorization. I have forgot the account name and other information. Is there any way to find out that account and delete it? Thanks. Zheng

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Custom Denverton Board: UART Initialization issue.
by Balaji Sivakumar 03 Jun '20

03 Jun '20

Hi Everyone, I am currently working on a custom Denverton board similar to the Intel Harcuvar board. CAR is working and the ROM stage is executing. There should be console output on UART0, but it does not appear to be initializing. There is a logic analyzer connected directly to the SOC UART pins and the internal pull up can be seen working during hard strap sampling, but after strap sampling TX goes low and stays low. I have tried configuring it as both HSUART and legacy UART with early console init both disabled and enabled and nothing has worked. Is there anything that could be preventing the UART from initializing? Thanks Balaji

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CoffeeLake - S RVP8 stop at post code 0x95
by fred.liao(廖千毅) 31 May '20

31 May '20

Hi, I am trying to use the coreboot code on Intel Coffeelake-S RVP8 CRB board, but system can not boot completely and stop at post code 0x95. First, system can boot to post code 0x94, and has a reboot, then stop at post code 0x95. Is there any idea about it? I have used FSP from git or from Intel, and has the same fail. Does anybody know what’s the meaning of post code 0x95? Thanks. BR Fred

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coreboot June 2020