coreboot June 2020

coreboot@coreboot.org

36 participants
38 discussions

And checkout works on WSL
by Gregg Levine 16 Jun '20

16 Jun '20

Hello! I'm not sure I understand this, checkout works on WSL which has a newer release of Git. I'm not sure I can build it on my Slackware-12.2 system who is an X86 not an X64 system. ----- Gregg C Levine gregg.drwho8(a)gmail.com "This signature fought the Time Wars, time and again."

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Kexec functions
by Gregg Levine 15 Jun '20

15 Jun '20

Hello! I'm digging through the pastiche of Coreboot and stuff from the LinuxBIOS days, and I came across my efforts to make the Kexec functions work. But the kernel chosen then was 2.2.18 and the selected one in the notes was 2.4.19. Can someone point me towards any known good patch for the 2.4 series? That system runs the 2.4.33.3 kernel. ----- Gregg C Levine gregg.drwho8(a)gmail.com "This signature fought the Time Wars, time and again."

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Is there a known working release of the git tool?
by Gregg Levine 14 Jun '20

14 Jun '20

Hello! For example on the WSL example I have inside this laptop it is 2.12.3 but the release number for Slackware 11.0 is much lower. And I am wondering what release of that tool will work to to properly understand the storage on the site and enable me to download from it, and even allow me to eventually contribute. But not for a long while. Let's just say it is blue sky reasoning. ----- Gregg C Levine gregg.drwho8(a)gmail.com "This signature fought the Time Wars, time and again."

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Asrock E350M1: Display regression in Linux
by HacKurx 13 Jun '20

13 Jun '20

Good morning, everyone, I hadn't updated my coreboot version for a long time on my Asrock E350M1 card because of lack of time and because this one was on a very stable version. While trying to test the current 4.12 version, I encountered problems in Debian 10. Indeed, there is a bad graphical detection, the resolution of my hdmi output went from 1360x768 to 720x400 pixels. Xorg indicates that the drm device cannot be opened : (EE) open /dev/dri/card0: No such file or directory I once had a Oops kernel message: https://pastebin.com/uZLZyYrq My coreboot graphical configuration is as follows: CONFIG_VGA_BIOS_ID="1002,9802" CONFIG_ONBOARD_VGA_IS_PRIMARY=y CONFIG_VGA_BIOS=y CONFIG_VGA_BIOS_FILE="vgabios.bin" I manage to restore normal working in coreboot 4.12-git by removing the commits: a5c2ac6256d0dae112b24c422d1270919acb6321 "x86/acpi: Add VFCT table" 6f978cfd1ab6a57e5729e19bed3df7702c4f09cb "x86/acpi: Use initialized VBIOS in VFCT table" Thank you. Best regards, Loic

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coreboot compatibility with my device
by Musicalbkwrm 12 Jun '20

12 Jun '20

Hello, the idea of FOSS BIOS firmware greatly appeals to me, and I would like to know if my computer is compatible with coreboot. Thank you in advance for your time and consideration. :-) Here are my specs: Motherboard Vendor: Lenovo Motherboard Make/Model: Lenovo Flex 3-1580 SDK0J40709WIN CPU: version: Intel(R) Core(TM) i5-6200U CPU @ 2.30 GHz, voltage: 0.6 V, external clock: 100 MHz, Max Speed: 2800MHz, Core Count: 2, Northbridge: product: Xeon E3-1200 v5/E3-1500 v5/6th Gen Core Processor Host Bridge/DRAM Registers vendor: Intel Corporation physical id: 100 bus info: pci@0000:00:00.0 version: 08 width:32 bits clock: 33MHz configuration: driver=sk1_uncore resources: irq:0 Southbridge: product: Sunrise Point-LP PMC vendor: Intel Corporation physical id: 1f .2 bus info: pci@0000:00:1f .2 version: 21 width: 32 bits clock: 33 MHz (30.3ns) configuration: latency=0 resources: memory:d1224000-d1227fff lspci -tvnn output: -[0000:00]-+-00.0 Intel Corporation Xeon E3-1200 v5/E3-1500 v5/6th Gen Core Processor Host Bridge/DRAM Registers [8086:1904] +-02.0 Intel Corporation Skylake GT2 [HD Graphics 520] [8086:1916] +-14.0 Intel Corporation Sunrise Point-LP USB 3.0 xHCI Controller [8086:9d2f] +-14.2 Intel Corporation Sunrise Point-LP Thermal subsystem [8086:9d31] +-15.0 Intel Corporation Sunrise Point-LP Serial IO I2C Controller #0 [8086:9d60] +-16.0 Intel Corporation Sunrise Point-LP CSME HECI #1 [8086:9d3a] +-17.0 Intel Corporation Sunrise Point-LP SATA Controller [AHCI mode] [8086:9d03] +-1c.0-[01]-- +-1c.4-[02]----00.0 Intel Corporation Dual Band Wireless-AC 3165 Plus Bluetooth [8086:3166] +-1c.5-[03]----00.0 Realtek Semiconductor Co., Ltd. RTL8111/8168/8411 PCI Express Gigabit Ethernet Controller [10ec:8168] +-1f.0 Intel Corporation Sunrise Point-LP LPC Controller [8086:9d48] +-1f.2 Intel Corporation Sunrise Point-LP PMC [8086:9d21] +-1f.3 Intel Corporation Sunrise Point-LP HD Audio [8086:9d70] \-1f.4 Intel Corporation Sunrise Point-LP SMBus [8086:9d23] Motherboard Super I/O Chip: Nuvoton WPCE775x/NPCE781x (id=0x00, rev=0x05) at 0x4e flashrom output: No coreboot table found. No DMI table found. W836xx enter config mode worked or we were already in config mode. W836xx leave config mode had no effect. Active config mode, unknown reg 0x20 ID: fc. Found chipset "Intel Sunrise Point (Skylake -U Premium)" with PCI ID 8086:9d48. ERROR: This chipset is not supported yet. Error: Programmer initialization failed. Sent with [ProtonMail](https://protonmail.com) Secure Email.

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Scaleway Tagada Board
by btech＠abcdn.qc.ca 12 Jun '20

12 Jun '20

We have a new project in-house and we want to use an Intel C3000 family with Coreboot. We cannot find Harcuvar board then we are looking for tagada one. Any help to find one will greatly appreciate, Thank Either one, (Harcuvar or tagada).

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Change Romsize and CBFS size.
by nitin.ramesh.singh＠gmail.com 12 Jun '20

12 Jun '20

Hi, I am trying to build a Coreboot for a Flash Size as 64 MB, with 32MB reserved for a BIOS region. I have modified the descriptor for a bios region: 02000000:03ffffff bios The fmap used for the given setting is as follows: FLASH@4227858432 0x4000000 { BIOS@33554432 0x2000000 { FMAP@0 0x200 RW_MRC_CACHE@65536 0x10000 COREBOOT(CBFS)@131072 33423360 } } Flash start -> 0xFC000000 (with-in 4GB space @4227858432) Flash Size -> 0x4000000 BIOS Start offset w.r.t Flash start -> 0x2000000 (@33554432) Bios region size -> 0x2000000 CBFS Size -> ‭0x1FE0000‬ Can any one please let me know what are the other changes required to incorporate the Coreboot image as per the given layout? Thanks, Nitin.

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Simple non-Linux payload for checking ARM devices (QEMU)
by Paul Menzel 11 Jun '20

11 Jun '20

Dear coreboot folks, Elyes is working on upgrading the coreboot crossgcc toolchain, especially to GCC 10.1.0, and wants to test the results with the QEMU emulation. Unfortunately, for ARM devices – and probably all other non-x86 one – there seems to no simple payload to test with. It was recommended to use a Linux payload, but as this of course should also be tested, is there an easy, maybe libpayload based, payload to test. Can depthcharge be built easily with some kind of test menu to display the CBMEM console and timestamps and some test image for the framebuffer? Has anybody looked, what makes coreinfo x86 specific? Kind regards, Paul

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4.12 Tags Release VBOOT_HOST_BUILD Issue
by Balaji Sivakumar 11 Jun '20

11 Jun '20

Hello Everybody, Could anyone face the build issue in 4.12 while compiling the CBFS VBOOT_HOST_BUILD? Is there option available to disable VBOOT_HOST_BUILD ? or Does the host machine has to have any specifics libraries installed? Please throw any insights. -- Thanks, Balaji

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Hands-on AMD Zork(Picasso)
by btech＠abcdn.qc.ca 11 Jun '20

11 Jun '20

I want to learn Coreboot and AMD Zork architecture. Do you have any suggestion on which board (and its manufacturer product name) to start with. I can see Trembyle, Dolbaz ... for Google Zork (mainboard) but I cannot figure out witch Google Chrome book is paired with a specific baseboard. Any suggestion are welcome.

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coreboot June 2020