coreboot January 2020

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44 participants
44 discussions

Re: F2A85-M - amdgpu fails, integrated GPU works fine
by Mike Banon 13 Jan '20

13 Jan '20

I solved a discrete AMD GPU problem for a similar A88XM-E board, and the same solution should apply to F2A85-M since these boards are very similar. However, the extra patches (which aren't in coreboot master) are required to get it working - more info at https://review.coreboot.org/c/coreboot/+/30987/ comments. On Sat, Oct 19, 2019 at 11:05 PM Mike Banon <mikebdp2(a)gmail.com> wrote: > > Do you still have this problem? Please try obtaining a "cbmem log" and > I'll try my best to help you > > On Sat, Oct 12, 2019 at 8:40 PM Mike Banon <mikebdp2(a)gmail.com> wrote: > > > > Maybe this "cbmem log" is disabled at your coreboot .config, probably > > this setting is at General section of menuconfig, can't check right > > now. Share your .config if there are problems in finding > > > > On Sat, Oct 12, 2019 at 12:21 PM Grzegorz Bogdał > > <bogdal.grzegorz(a)tutanota.com> wrote: > > > > > > "Table not found." > > > Is it the output, or did I do something wrong? I'm back on the vendor BIOS right now. > > > > > > > > > Oct 12, 2019, 08:30 by mikebdp2(a)gmail.com: > > > > > > Please could you share your coreboot boot log after applying this > > > patch? Available with ./coreboot/util/cbmem utility > > > > > > On Fri, Oct 11, 2019 at 6:11 PM Grzegorz Bogdał > > > <bogdal.grzegorz(a)tutanota.com> wrote: > > > > > > > > > I've tried the patch from csb_patcher. I've applied only the lenovog505s_dgpu patch. Unfortunately, nothing changed. > > > > > > > > > Sep 14, 2019, 14:04 by mikebdp2(a)gmail.com: > > > > > > Kinky, have you tried a patch mentioned in my previous message? If > > > yes, what are the results? > > > > > > On Thu, Sep 12, 2019 at 2:31 PM Kinky Nekoboi <kinky_nekoboi(a)nekoboi.moe> wrote: > > > > > > > > > Also user of said board. > > > > > > For me only Nvidia GPUs work correctly. > > > > > > But using an older Version from 2018, because S3 works there. > > > > > > > > > Am 10.09.19 um 11:05 schrieb Mike Banon: > > > > Indeed, this patch -- https://review.coreboot.org/c/coreboot/+/31448 ( > > > > src/device/pci: Add support for discrete VGA initialization and OpROM > > > > loading ) -- could help, because it will create the ACPI VFCT table > > > > for discrete RX 570 GPU instead of doing this for integrated HD 8670D. > > > > You could install it conveniently and securely with the help of > > > > csb_patcher.sh script ( > > > > http://dangerousprototypes.com/docs/Lenovo_G505S_hacking#NEWS or > > > > https://review.coreboot.org/c/coreboot/+/33509 ). > > > > > > > > Although there will not be a VFCT for your integrated GPU, it should > > > > be working fine even without it, maybe at cost of a slightly higher > > > > power consumption. We have discovered that > > > > > > > > " ACPI VFCT - it's a table where AMD stores the Radeon video BIOS when > > > > the system is booted up in UEFI mode." > > > > " Where the ACPI VFCT Table is missing, Power States may not work properly. " > > > > > > > > so it seems without VFCT the integrated GPU is going to be at its' max > > > > TDP even while not loaded. For example, knowing that a total TDP of > > > > our G505S laptop's A10-5750M APU (CPU+GPU) does not exceed 35W and > > > > looking at the values for similar APUs at this table > > > > https://www.eteknix.com/amd-kaveri-a10-7850k-overclocking-analysis/7/ > > > > (all values except Intel / RAM / OC), approximately for our A10-5750M > > > > it should be > > > > > > > > Idle | GPU load | CPU+GPU load > > > > 15.6W | 23.66W | 35W > > > > 44.5% | 67.6% | 100% > > > > > > > > We already knew that A10-5750M is 15W at idle, but have learned that > > > > GPU adds approximately 23.66W - 15.6W = about 8W while at its' max > > > > TDP. This G505S laptop comes with a 65W PSU, so with iGPU at it max > > > > TDP -- the laptop's battery life will be smaller in about 65/(65-8) = > > > > 1.12 times. However I've never compared the consumption difference of > > > > coreboot vs UEFI, would be nice if someone could test it in practice. > > > > > > > > Since this RX 570 discrete PCI-E card should have its' own flash chip > > > > for storing the AtomBIOS blob -- unlike our laptop's onboard discrete > > > > HD-8570M or R5-M230 -- I think in your case there should not be a need > > > > of storing the discrete GPU's AtomBIOS ROM at your coreboot BIOS in > > > > addition to the integrated one. However, if the advice above would not > > > > work, you could try extracting the discrete GPU's AtomBIOS , using > > > > either https://www.coreboot.org/VGA_support#How_to_retrieve_a_good_video_bios > > > > or https://github.com/g505s-opensource-researcher/g505s-atombios#description > > > > | https://mail.coreboot.org/pipermail/coreboot/2017-July/084660.html > > > > instruction. > > > > > > > > Best regards, > > > > Mike > > > > > > > > On Mon, Sep 9, 2019 at 10:04 PM awokd via coreboot > > > > <coreboot(a)coreboot.org> wrote: > > > >> Grzegorz Bogdał: > > > >>> Thank you. I'll check it out and report sometime in September whether the patches helped my case. > > > >> Please note, AFAIK they have only been tested on G505s's, so may need > > > >> some modification for your platform. > > > >> > > > >> _______________________________________________ > > > >> coreboot mailing list -- coreboot(a)coreboot.org > > > >> To unsubscribe send an email to coreboot-leave(a)coreboot.org > > > > _______________________________________________ > > > > coreboot mailing list -- coreboot(a)coreboot.org > > > > To unsubscribe send an email to coreboot-leave(a)coreboot.org > > > > > >

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Enable non-NVME devices in M.2 slot?
by Rafael Send 11 Jan '20

11 Jan '20

Hi, I know a couple folks here are active on Thinkpads.com / familiar with the X210 port by Matthew. The stock BIOS doesn't appear to support non-NVME devices in the M.2 slot; I'm attempting to get a Sunix UPD2018 card working to add USB-C. With stock BIOS, the card works just fine in the WiFi slot, and an NVME drive works just fine in the M.2 slot so nothing appears physically broken. However, so far nothing I've done lets me detect the Sunix card if I try to put it in the NVME slot using this adapter <https://www.adt.link/product/R42.html>. I would think it should just show up under "lspci" like it does in the WiFi slot, but it does not. I have not tried the latest Coreboot / port yet, but I figured I might as well get some opinions on the subject. What do you guys think, can this be done with Coreboot? Cheers, Rafael

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Re: Error 404 , can't open change 38107 on Gerrit
by ehaouas＠noos.fr 09 Jan '20

09 Jan '20

<span style="font-family:arial,helvetica,sans-serif; font-size:12px">See  </span><a href="https://review.coreboot.org/q/owner:ehaouas%2540noos.fr+Switch+away+from+RO…">https://review.coreboot.org/q/owner:ehaouas%2540noos.fr+Switch+away+from+RO… </a><span style="font-family:arial,helvetica,sans-serif; font-size:12px">‌</span> <div class="gl_quote" style="margin-top: 20px; padding-top: 5px;"> <div class="gl_quoted"> <div class="gl_quote" style="margin-top: 20px; padding-top: 5px;">De : "Carl-Daniel Hailfinger"<br> A : "Mike Banon" ,"HAOUAS Elyes" ,jonzhang@fb.com,acidburn0@live.be,andycuiyj@gmail.com,"Martin Roth" ,"Michal Zygowski" ,no-reply(a)coreboot.org,"Patrick Georgi" ,darkkerman99@gmail.com,coreboot-gerrit@coreboot.org,ionela.voinescu@imgtec.com,"Paul Menzel" ,"coreboot"<br> Envoyé: mercredi 8 janvier 2020 17:13<br> Objet : Re: [coreboot] Re: Error 404 , can't open change 38107 on Gerrit<br>   <div class="gl_quoted">Hi Mike,<br> <br> maybe the archives contain some salvageable info:<br> https://mail.coreboot.org/hyperkitty/list/coreboot-gerrit@coreboot.org/<br> <br> On 08.01.20 08:36, Mike Banon wrote:<br> > Same problem with many other "Drop boards with ROMCC_BOOTBLOCK"<br> > changes. So much work has been lost...<br> ><br> > On Wed, Jan 8, 2020 at 10:25 AM Mike Banon wrote:<br> >> For some reason I couldn't open change 38107 - it gives me a 404 :<br> >><br> >> https://review.coreboot.org/c/coreboot/+/38107<br> >> coreboot[master]: mb/gizmosphere/gizmo2: Drop boards with ROMCC_BOOTBLOCK<br> >><br> >> Error 404 (Not Found): Not found: coreboot~38107<br> >><br> >> This change is vitally important for preserving a Gizmo2 board, so I<br> >> hope you could fix this Gerrit problem.<br> >><br> >> Best regards,<br> >> Mike Banon<br> <br> Regards,<br> Carl-Daniel</div> <div class="gl_quoted"> </div> </div> </div> <div class="gl_quoted"> </div> </div>

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libgxfinit + latest master gives "static noise" bootscreen (Windows)
by Rafael Send 08 Jan '20

08 Jan '20

Hi, For the past month or two (I'm not actually sure WHEN it stopped working) I haven't been able to successfully boot (any) Windows installations using libgfxinit. Mid-October I had created some builds that worked, but I'm not sure they were using master or something else at that point (only kept the binaries unfortunately). The symptom is that when I select the Windows boot manager from Grub, I get a very regular-looking, TV-static like screen, then black. From the HDD activity, I can tell the boot is continuing but the graphics don't recover. Interestingly, if I then force-powercycle the machine, the Windows bootloader does successfully enter its "Recovery Environment" or whatever that is. I can try to choose an OS to boot, but after that the same thing happens. Is this a known bug / issue? I'm building the latest master for the X210 using mgj59's port. Cheers, R

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Error 404 , can't open change 38107 on Gerrit
by Mike Banon 08 Jan '20

08 Jan '20

For some reason I couldn't open change 38107 - it gives me a 404 : https://review.coreboot.org/c/coreboot/+/38107 coreboot[master]: mb/gizmosphere/gizmo2: Drop boards with ROMCC_BOOTBLOCK Error 404 (Not Found): Not found: coreboot~38107 This change is vitally important for preserving a Gizmo2 board, so I hope you could fix this Gerrit problem. Best regards, Mike Banon

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AGESA MMIO Allocation
by awokd 08 Jan '20

08 Jan '20

Am attempting to resolve one of the last listed High Impact Outstanding AGESA Coverity issues (1376956), but am struggling to determine the programmer's intent. In /src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15MmioMap.c line 236, Coverity complains about the 12 element MmioRange array getting overrun in MmioRange[MmioPair + i].Base when MmioPair == 11. I see it will also get overrun when lower values of MmioPair combine with higher values of i. Thus my question: what are they trying to accomplish with that for loop? If I could figure that out, I could figure out how to fix the code. I've spent 8+ hours on this and consulted the BKDG, but it did not go into detail on how MMIO registers get allocated. PS Thanks to Jacob Garber for his assistance getting started with Git and putting up with my beginner questions. -- - don't top post Mailing list etiquette: - trim quoted reply to only relevant portions - when possible, copy and paste text instead of screenshots

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Re: [fam16h AM1I-A] ehci-pci: can't derive routing for PCI INT B. USB 3.0 doesn't work even as USB 2.0
by Mike Banon 08 Jan '20

08 Jan '20

> I think something is messed up with those USB ports on G505s too, > because I have to use irqpoll on them in Qubes. I have the BKDG for AMD > 15h. Where can I find the appropriate IRQ routings for the G505s's chipset? Build a coreboot for G505S with CONFIG_DEBUG_PIRQ and see the warning/error messages. To me, it seems that - to fix the interrupts - first of all we need to convert the stuff like irq_tables.c from a G505S "legacy style" ( i.e. pirq_info function ) to AM1I-A "new style" ( i.e. intel_irq_routing_table structure ). On another fam15h board (A88XM-E) and most likely on G505S too, if CONFIG_DEBUG_PIRQ is enabled, this "legacy style" code is giving bad warning like "Can't write PCI IRQ assignments because mainboard_pirq_data structure does not exist" and i.e. KolibriOS can't see the interrupt numbers at all. While, on fam16h AM1I-A board, "new style" code seems to work fine - "Finished writing PCI config space IRQ assignments" - and KolibriOS sees the interrupt numbers OK. Maybe using KolibriOS as an indicator seems irrelevant, however to me its' a sign that "new style" code for interrupt routing is better quality, and maybe simply converting G505S interrupts code from "legacy style" to "new style" alone should fix them. Sadly no fam15h boards have a "new style" interrupt routing code: if to search like " find . -type f -name "irq_tables.c" -print0 | xargs -0 grep -n "intel_irq_routing_table" ", only fam14h and fam16h boards appear. But I don't expect it to be too difficult: i.e. AM1I-A fam16h code is based on ASRock IMB-A180 according to d777c78 commit message, and the conversion went OK, also fam15h and 16h are similar enough except the vendorcode. I suggest doing " git reset --hard d777c78 " , " kdiff3 ./src/mainboard/asrock/imb-a180/ ./src/mainboard/biostar/am1ml/ & " , and applying the same logic while converting a G505S code. I don't have the time to do this conversion myself (spent all holidays working on coreboot and they ran out), but if you succeed in this I will happily review your change. Best regards, Mike Banon

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Asus P2B-LS board status upload after C environment bootblock conversion
by Paul Menzel 07 Jan '20

07 Jan '20

Dear Keith, Thank you for uploading the logs of the Asus P2B-LS to coreboot’s board status repository [1]. asus/p2b-ls/4.11-711-gd913036e18/2020-01-05T00_12_56Z Two notes: 1. The version in the logs unfortunately contain the *dirty* tag. Could you run `git status` or `git diff` to see what the differences are and maybe upload “clean” logs? 2. Please rebuild CBMEM, so it knows about all time stamp names. 3. With C environment bootblock CBMEM timestamp collection seems to work now. > 25 entries total: > > 0:1st timestamp 980 > 11:start of bootblock 6,307 (5,326) > 12:end of bootblock 6,590 (283) > 13:starting to load romstage 8,231 (1,641) > 14:finished loading romstage 8,373 (141) > 1:start of rom stage 8,930 (556) > 4:end of romstage 3,166,633 (3,157,703) romstage seems to take 3 seconds, which seems a lot. Do you have serial logs with timestamps, for example, `readserial.py` in SeaBIOS’ repository, for comparison with romcc bootblock? (Or you can enable to have timestamps printed to the console, so they > 100:<unknown> 3,331,673 (165,039) > 101:<unknown> 3,331,674 (0) Please rebuild cbmem. > 8:starting to load ramstage 3,348,277 (16,603) > 15:starting LZMA decompress (ignore for x86) 3,353,834 (5,557) > 16:finished LZMA decompress (ignore for x86) 3,400,159 (46,324) > 9:finished loading ramstage 3,411,813 (11,654) > 10:start of ramstage 3,427,503 (15,689) > 30:device enumeration 3,427,508 (4) > 40:device configuration 3,648,839 (221,330) > 50:device enable 4,926,610 (1,277,771) That is probably due to having the serial console enabled. Could you please do one upload with the serial console disabled? > 60:device initialization 4,952,646 (26,036) > 70:device setup done 5,347,654 (395,007) > 75:cbmem post 5,352,364 (4,710) > 80:write tables 5,352,366 (2) > 85:finalize chips 5,564,523 (212,156) > 90:load payload 5,569,481 (4,957) > 15:starting LZMA decompress (ignore for x86) 5,614,901 (45,419) > 16:finished LZMA decompress (ignore for x86) 5,684,112 (69,211) > 99:selfboot jump 5,704,387 (20,274) > > Total Time: 5,703,393 Is the boot time really that long, and was it the same with romcc bootblock? Kind regards, Paul [1]: https://review.coreboot.org/cgit/board-status.git/tree/asus/p2b-ls/4.11-711…

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[fam16h AM1I-A] ehci-pci: can't derive routing for PCI INT B. USB 3.0 doesn't work even as USB 2.0
by Mike Banon 07 Jan '20

07 Jan '20

My AM1I-A config is similar to G505S in this relation: # CONFIG_HUDSON_XHCI_FWM is not set # CONFIG_HUDSON_XHCI_ENABLE is not set Since XHCI is disabled, I expect its' USB 3.0 ports to work as USB 2.0, just like they are working on G505S. However, on AM1I-A they don't work at all, and I see this at dmesg kernel log: ehci-pci 0000:00:16.2: can't derive routing for PCI INT B ehci-pci 0000:00:16:2: PCI INT B: no GSI ehci-pci 0000:00:16.2: Found HC with no IRQ. Check BIOS/PCI 0000:00:16.2 setup! ehci-pci 0000:00:16:2: init 0000:00:16:2 fail, -19 ehci-platform: EHCI generic platform driver ohci-pci 0000:00:16.0: can't derive routing for PCI INT A ohci-pci 0000:00:16:0: PCI INT A: no GSI ohci-pci 0000:00:16.0: Found HC with no IRQ. Check BIOS/PCI 0000:00:16.0 setup! ohci-pci 0000:00:16:0: init 0000:00:16:0 fail, -19 ohci-platform: OHCI generic platform driver I tried explicitly enabling 16.0 and 16.2 at devicetree.cb (they weren't mentioned here), but it doesn't help. What are my next steps? Best regards, Mike Banon

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07 Jan '20

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coreboot January 2020