coreboot January 2020

coreboot@coreboot.org

44 participants
44 discussions

Activity for implementing Intel Security Advisories
by Naveen Chaudhary 17 Jan '20

17 Jan '20

Hi, I am trying to understand what is the activity corresponding to the fixes suggested by Intel security advisories relating to the processor/controller flaws. I took a glance at commit history and did grep "CVE" but there is nothing there. Once the advisories are released by Intel, on average, what is the timeline to get them implemented on a general note. I understand coreboot is an open community project, but while working on one feature of coreboot, I would want to be sure that some of my friend in the community is taking of security issues. Regards, Naveen

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Boot Guard availability on Kaby Lake
by Michal Zygowski 15 Jan '20

15 Jan '20

Hi coreboot community, Is anybody aware if Boot Guard feature is supported on following processors: Intel Celeron 3865U, Intel Core i3-7100U, Intel Core i5-7200U? Are ACMs different across processor variants (mobile/desktop/U/Y/H/etc.)? If I would take Boot GuardACM from another 6th or 7th Gen platform to one of these processors, would it work? Regards, -- Michał Żygowski Firmware Engineer http://3mdeb.com | @3mdeb_com

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Optiplex 790 now has preliminary support by coreboot
by Taiidan＠gmx.com 15 Jan '20

15 Jan '20

https://review.coreboot.org/21774 In case anyone else didn't notice - It is a sandy/ivy system with IOMMU. This is great and should help get coreboot in to the corporate user world.

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Increasing chip size - check my modifications please?
by Rafael Send 14 Jan '20

14 Jan '20

Hi there- I'd like to increase the size of my flash chip from 8MB to 16MB. From poking at stuff and asking dumb questions in the #coreboot channel, I've gathered I need to make the following changes, but I'm not 100% sure these are correct. If anyone could look this over and point me in the right direction before I flash a broken image, I would appreciate that. *1)* descriptor.ifd: Use ifdtool on descriptor.bin to increase the density from 8M to 16M. This appears to work. *2)* Modify fmap - currently looks like this: FLASH@0xff800000 0x800000 { BIOS@0x200000 0x600000 { EC@0x0 0x10000 RW_MRC_CACHE@0x10000 0x10000 SMMSTORE@0x20000 0x40000 FMAP@0x60000 0x200 CONSOLE@0x60200 0x20000 COREBOOT(CBFS)@0x80200 0x57FE00 } } and it should become: FLASH@0xff800000 0x1000000 { <- new chip size BIOS@0x200000 0xE00000 { <-new BIOS region size EC@0x0 0x10000 RW_MRC_CACHE@0x10000 0x10000 SMMSTORE@0x20000 0x40000 FMAP@0x60000 0x200 CONSOLE@0x60200 0x20000 COREBOOT(CBFS)@0x80200 0xD7FE00 <- new CBFS size } } Question: I read that an FMAP file overrides CBFS_SIZE, if such is provided.Since the coreboot .config still says CBFS_SIZE=0x200000, but an FMAP has always been provided, is it true that 0x200000 was never the result / used? *4) *Adjust ROM size to 16MB in menuconfig *5)* Provide new FMAP and descriptor to menuconfig *6) *Use an external flasher to flash this new image Am I missing any steps, and are the above modifications correct? Thanks, Rafael

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how can I using lpc decode/enable com A and com B on Denverton?
by cooljason0404＠gmail.com 14 Jan '20

14 Jan '20

Hi all, I using intel denvertonNS Soc setting register lpc decode/enable com A and comB, but coreboot no console message on lpc. I check hard strap pin is setting LPC Decode Select . Best Regards, Jason

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"Delete change" Gerrit feature does more harm than good
by Mike Banon 13 Jan '20

13 Jan '20

"Delete change" Gerrit feature was available for a limited time, and I've successfully deleted some 3 year old changes (don't worry, their work has been merged at newer changes - I've double checked it well before proceeding - so nothing lost). However, someone used the same feature to remove the valuable "Switch away from ROMCC_BOOTBLOCK" changes by HAOUAS Elyes - to which I've spent a huge amount of time contributing the minor fixes and reviewing. This "switch away from ROMCC_BOOTBLOCK" work has been declared as a mandatory condition of preserving a range of AMD boards, so it's really sad to see it gone. Gogol burning Dead Souls volume 2 comes to mind... Please, restore the changes deleted since Jan 5 2020, and make sure this anti-feature "delete change" can't be used such easily in the future. Best regards, Mike Banon

3 3

Coreboot + ASUS P5K-E???
by Aaron Garza 13 Jan '20

13 Jan '20

Does Coreboot work on every motherboard or does it have to be certain motherboards/PCs? I have an old Intel Core 2 Quad and an ASUS P5K-E motherboard that I would love to set up with a coreboot BIOS replacement. Is it even possible? Let me know. Thanks!

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Re: Asus P2B-LS board status upload after C environment bootblock conversion
by Paul Menzel 13 Jan '20

13 Jan '20

Dear Keith, Am 11.01.20 um 06:35 schrieb Keith Hui: > As I am still chasing how to enable SCSI termination on the board, Due to the conversion, please always write if that worked with romcc, that means, a regression with C environment bootblock. > I've recompiled a few more times. Therefore I was able to upload two > more clean board statuses, one with serial enabled and one without > as you asked. Thank you. Though I only see one more upload after the one I referred to. $ git log --oneline -2 asus/p2b-ls dde01d781 asus/p2b-ls/4.11-839-g11c5b3b180/2020-01-10T21_51_08Z 5550a954e asus/p2b-ls/4.11-711-gd913036e18/2020-01-05T00_12_56Z Without serial (`CONFIG_CONSOLE_SERIAL is not set`) has a total time of 2.9 seconds compared to 5.7 before. > Unfortunately without serial it still takes 2.5s in the romstage, and > I can visually see the serial output going much slower than in > ramstage. We should check the serial enabling code in romstage or > even bootblock. Is that a regression compared to romcc bootblock? > Also PS/2 keyboard init and sometimes video init is still finicky. Ditto. Regression or not. > There are times when keyboard does not respond before the linux > kernel is completely done, Maybe that can be debugged in SeaBIOS, which you use as payload. Please increase the debug level for SeaBIOS, and post the logs from the working and non-working cases. (Please start a separate mailing list thread for that.) > and that could also be preventing my SCSI > BIOS (extracted as is from factory image) from running through as it > watches for a key combo to enter its setup interface. Did that work with romcc. Please paste verbose SeaBIOS logs. > What is the commit that I should branch off of to get my romcc > romstage back? I assume it is the parent of commit 1fa240a3 (cpu/intel/slot_1: Move to C_ENVIRONMENT_BOOTBLOCK) [1], so commit df0c731e (mb/Kconfig: Add a warning on boards with a ROMCC_BOOTLOCK). Please test df0c731e, and upload the logs to the board status repository too. Kind regards, Paul [1]: https://review.coreboot.org/c/coreboot/+/36774

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Please guys repair coreboot to support my laptop motherboard. https://github.com/coreboot/coreboot/pull/18
by 王一凡 13 Jan '20

13 Jan '20

Please guys repair coreboot to support my laptop motherboard. https://github.com/coreboot/coreboot/pull/18

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How to add support for PCIe bridge to coreboot on Baytrial SoC
by zahra rahimkhani 13 Jan '20

13 Jan '20

I Compiled Coreboot with Seabios and Tianocore payload on Baytrail SoC. I want to use a [PCIe bridge][3] to convert a PCIE-x1 to 2 PCIE-X1 connectors but booting FreeBSD won't show any active bridge. The [Baytrail SoC documentation][1] states that a register called [SLCTL_SLSTS][2] should be set in order to activate the bridge support but I don't know how to set such flag on coreboot. - Is it possible to use PCIe bridge on Baytrail SoCs? - How one can add bridge support to coreboot if possible? [1]: https://www.mouser.com/datasheet/2/612/atom-e3800-family-datasheet-1522396.… [2]: https://github.com/coreboot/coreboot/blob/master/src/soc/intel/baytrail/inc… [3]: https://www.amazon.co.uk/IOCrest-Ports-Extension-Switch-Multiplier/dp/B075K…

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coreboot January 2020