coreboot September 2019

coreboot@coreboot.org

52 participants
37 discussions

OpenBSD won't install on an x220 Thinkpad with Coreboot
by Robert Milton 12 Apr '20

12 Apr '20

I'm trying to get OpenBSD to install on an x220 Thinkpad with Coreboot/SeaBIOS but I'm running into two problems: the ethernet device doesn't work and OpenBSD doesn't detect my HDD. dmesg said em0 wouldn't load because the EEPROM had an invalid signature. I have no idea why OpenBSD doesn't see my HDD though. It's strange because everything works fine under Linux. And I cannot seem to mount a usb drive under the OpenBSD installer to attach dmesg errors. I originally posted this as a bug report to bug report mailing list but Theo said it would be better suited for Coreboot's and wasn't a bug in OpenBSD.

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Mainboard porting assistance
by Benjamin Doron 10 Apr '20

10 Apr '20

Hi all, I own an Acer Aspire VN7-572G and have not been impressed with its OEM firmware. After discovering that it does not utilise Intel's Boot Guard technology, that several Skylake and Kabylake laptops (it has a Skylake chip, but I read that the platforms are similar) have received successful coreboot ports and reading the porting guide on the wiki, I figured that I could give porting coreboot to my laptop a shot. When I was done, I figured that I had an image that might boot so I flashed it to my laptop with a Raspberry Pi and a SOIC clip. However, here's what it does: a) It powers on quietly, as expected; b) The backlight and power LED light up; c) The fans spin up to high and then it stays that way. It does nothing else. The display is dark too. After 15 minutes and a second attempt, I figured that I could no longer blame anything on a long first boot-up and gave up and flashed back to stock. Now, in all honesty I should have tried first without cleaning Intel ME but I find it so much more likely that I did something wrong than that cleaning ME was the sole problem. Can anyone advise me on how to continue? My code is here: https://github.com/benjamindoron/coreboot

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Optiplex 790 now has preliminary support by coreboot
by Taiidan＠gmx.com 15 Jan '20

15 Jan '20

https://review.coreboot.org/21774 In case anyone else didn't notice - It is a sandy/ivy system with IOMMU. This is great and should help get coreboot in to the corporate user world.

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[AMD 16h / ASUS AM1I-A] 1866MHz CL9 RAM runs only as 1333MHz CL9 - how to fix?
by Mike Banon 17 Nov '19

17 Nov '19

A pair of 1866MHz CL9 RAM modules* runs only as 1333MHz CL9 on 16h AM1I-A with coreboot is installed, but worked faster when a proprietary UEFI was installed. To fix this "turtle RAM" coreboot problem I tried to play with buildOpts.c - https://review.coreboot.org/c/coreboot/+/33920 , but the things like "#define BLDCFG_MEMORY_CLOCK_SELECT DDR1866_FREQUENCY" sadly did not help. Any ideas how to improve the RAM speeds? How I can force this RAM to run faster? Best regards, Mike Banon [*] Crucial Ballistix Tactical Series DDR3 1866MHz CL9 (PC3-14900 9-9-9-24) UDIMM 240-Pin modules, part number BLT8G3D1869DT1TX0

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FOSDEM 2020 CfP
by Carl-Daniel Hailfinger 26 Oct '19

26 Oct '19

Hi, we want to participate again in FOSDEM 2020. Location: Brussels. Date: 1&2 February. Deadlines: Own developer room: Expired... Stand: 1 November Main track talk: first batch 11 October, second batch 8 November Lightning talk: 22 November Talk/Demo in foreign devroom: probably end of October If you want me to submit a stand request for a combine coreboot/flashrom/LinuxBoot stand, please have someone volunteer as backup organizer. We also need stand volunteers. Side note: Should we reach out to the OpenBMC/u-bmc communities? https://fosdem.org/2020/news/2019-08-13-call-for-participation/ Regards, Carl-Daniel

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AMD AGESA maintenance and/or deprecation
by Patrick Georgi 16 Oct '19

16 Oct '19

Hi everybody, coreboot is shipping AMD's open sourced AGESA for a few generations as part of its tree. Some people advocate dropping the code due to its quality and lack of maintenance while others are happy with using the code. So: to help keep this code alive, we'd need maintainers - people willing to work through issues, improve the code quality and generally act as a point of contact if any questions arise. One item to start with could be to work through Coverity issues, where the largest proportion is now AGESA based after Jacob cleaned up most of the rest of the tree. See https://scan.coverity.com/projects/coreboot Drivers needs support to not get in the way of later development, and AGESA is sorely lacking in that department. If you see value in that code, please step up now, not only when we're looking into removing that code for good. Regards, Patrick -- Google Germany GmbH, ABC-Str. 19, 20354 Hamburg Registergericht und -nummer: Hamburg, HRB 86891, Sitz der Gesellschaft: Hamburg Geschäftsführer: Paul Manicle, Halimah DeLaine Prado

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Apollolake: SATA issues
by Christian Gmeiner 08 Oct '19

08 Oct '19

Hi all I have ported coreboot to a custom design based on APL and have random SATA problems with CFast cards. I am using the latest public APL FSP from github with the latest coreboot master. From time to time the SATA link 'dies' during runtime or I it is not possible to establish the SATA link at all (in the used u-boot payload). At the moment I am running out of ideas and I hope someone can point me in the right direction. Btw. with the vendor blob SATA works with out any problems :/ -- greets -- Christian Gmeiner, MSc https://christian-gmeiner.info/privacypolicy

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KGPE-D16 maintainership
by Piotr Król 02 Oct '19

02 Oct '19

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA512 Hi all, we see a lot of attention around KGPE-D16 maintainership problems. After discussion with Thierry Laurion (Insurgo) at OSFC2019 3mdeb decided to help in maintaining that platform by organizing crowd founding campaign or getting founds in other ways (direct sponsors). Since we are based in Poland there is chance that even with small contribution from community we would be able to cover the costs. Ideal plan would be to have structure similar to what we maintain for PC Engines: https://pcengines.github.io/ Where we providing signed and reproducible binaries every month and keep as close to mainline as possible. Of course if development will be active, then there always would be delta of patches held in review. Unfortunately we don't have hardware. During OSFC 2019 Stefan left one board, but it was too late (and probably too expensive) for us to organize any shipment to Poland. We looking to have 2 mainboards one for development and one in our automated regression testing environment. Of course we will start even with just one. If anyone is willing to help in founding, sponsoring hardware or by code development and testing we would be very grateful. Please copy other people and share this post wherever is necessary to keep this platform alive. Positive feedback will help things rolling. Best Regards, - -- Piotr Król Embedded Systems Consultant GPG: B2EE71E967AA9E4C https://3mdeb.com | @3mdeb_com -----BEGIN PGP SIGNATURE----- iQIzBAEBCgAdFiEE4DCbLYWmfoRjKeNLsu5x6WeqnkwFAl2ApSoACgkQsu5x6Weq nkw0XQ//WeO+U6VFcr6wsfCkv5qXnKVHb6XDXyEknhu7Q82HZ9Hx+0IiZ0+ikzVZ oLU36euPwlHoRFh3HPm34DHeeYAZYzzsdc41+0MZJao152CGZJQwe+pqD/JeymOU Jky+PhULeGKXt22ftbxte1ac82tRDFt//0Yc07qxP9G/CboZ8sjckKjfyfoy5PFm 9jRFwdZUMbU42mU+NYLn/iXGWM/+mxC+ghncQBYwwGX1npr1r5gSiZS9ImoHFpgj DQaaUQq2v8vS1uvYZ84vVEXeOljTkzFg7UyUZq3sSob8bA/a42rsgFMPVI6Bpc5R lAEdhBZgMaD4jjO2GK+3zFSy32pBvK71tzwrdLjhb/bjjN1phHy2zbwTebFWlyiu HQJ/+iu4uoTQj69GT9i7HLyngorh37GWFHKScDDzEASnSO868ELhlrt+yHwyY284 EAe7dTOhOtfdxJOKcfdyUez5nwPZON4AXEVSvLWLUv4r+f82CG89f+LLg7rbZH5n C0HnUOJas89xEvRhXChTBHnM9NBKSWpch5uZ5SbZHb/JCWBb26yT6Ua46H0STFRh y+pWHc8AN76FQnWvpYer5F3hyVEX1+wAsi+RJMROFUejCn3lCl5ogAnT4ZRCqzo3 61Ao6dYmtYhaQ3JjZ+5bv3926ZwRjvr7i5t9bHf9THXCn1UobjY= =wYUt -----END PGP SIGNATURE-----

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[PATCH] x86_64 support needs testing
by Patrick Rudolph 01 Oct '19

01 Oct '19

Dear coreboot community, Please test and review the patch series [1]. It adds support for x86 long mode on qemu and allows to build test most of coreboot's common code using the x86_64 toolchain. It serves as reference implementation to migrate real hardware to long mode. Here some technical details, that can also be found in the Documentation/ folder: A new tool called pgtblgen create static page tables for a known physical memory address. The page tables are placed in CBFS at the given address. Due to the fixed and known address, they can easily be loaded in assembly code. It only works on platforms that memory map the SPI flash, which are almost all modern x86 platforms. The advantage of page tables in ROM are: * No runtime (assembly) code to generate page tables * No need to find a (4K aligned) place in heap to store them * Improved security for SMM, as page tables are always immutable The page tables are loaded in bootblock and SMM and persist until control is handed over to the payload. For the Proof-of-Concept only 4GiB are identity mapped, thus no stage can't access memory over 4GiB. That's not a problem for now as no coreboot code make use of memory above 4GiB yet. I haven't done further tests on long mode. It will be interesting to see if there are improvements on boot speed, code size or faster firmware decompression speeds. Regards, Patrick 1: https://review.coreboot.org/q/topic:%22x86_64_support2%22+(status:open%20OR…

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graphic preallocated memory
by jief 30 Sep '19

30 Sep '19

Hi, I'm new to coreboot and this list, so please forgive and tell me if I'm doing something wrong. I've successfully compile coreboot and flash it to a Lenovo x220. I tried seabios and tianocore as a payload and it works. So strange compile errors as I'm used to when I compile an opensource project. So, _bravo_. What I need now is to be able to set the graphic preallocated memory. Usually in bios, it's "DVMT pre alloc" or something. I know it's possible on this platform because the unlocked bios can do it. Could anyone point me in the direction ? Thanks, Jief Mainboard : x220, i7-2640M(a)2.80GHz

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coreboot September 2019