December 2019 - coreboot - mail.coreboot.org

Jenkins doesn't send emails anymore?
by Julius Werner Dec. 3, 2019

Dec. 3, 2019

I recently noticed that I never get Gerrit notification emails when Jenkins sets a CL Verified+1 or Verified-1 anymore. It used to do that. Does anyone know if this is some accidental/intentional change on the server side (either with Gerrit or with Jenkins), or is that something wrong in my configuration? I can't find any setting for Gerrit on this and I'm pretty sure I don't have an email filter affecting it either. Not getting the Verified-1s is really annoying because then I never notice my patches still need work and forget about them.

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System hangs when booting into UEFI shell as secondary payload
by Jagriti Dixit Dec. 2, 2019

Dec. 2, 2019

Hi, I am trying to boot into UEFI shell from SeaBIOS using UEFIPAYLOAD.fd on a Broadwell-DE board generated from building UefiPayloadPkg from EDK-II source tree. Any help would be appreciated. The last part of the log is attached as follows: *CBFS: 'Master Header Locator' located CBFS at [200200:800000)CBFS: Locating 'pci10de,128b.rom'CBFS: 'pci10de,128b.rom' not found.Option ROM address for PCI: 04:00.0 = fb000000Incorrect expansion ROM header signature beefPCI: 04:00.0: Missing PCI Option ROMACPI: added table 2/32, length now 44ACPI: * MCFGACPI: added table 3/32, length now 48ACPI: * MADTIOAPIC: Initializing IOAPIC at 0xfec00000IOAPIC: Bootstrap Processor Local APIC = 0x00IOAPIC: ID = 0x08IOAPIC: Initializing IOAPIC at 0xfec01000IOAPIC: Bootstrap Processor Local APIC = 0x00IOAPIC: ID = 0x09ACPI: added table 4/32, length now 52current = 7ed42290ACPI: * DMARACPI: added table 5/32, length now 56pci_rom_write_acpi_tablesACPI: done.ACPI tables: 21264 bytes.smbios_write_tables: 7ed3c000SMBIOS: Unknown CPUSMBIOS tables: 424 bytes.Writing table forward entry at 0x00000500Wrote coreboot table at: 00000500, 0x10 bytes, checksum 7108Writing coreboot table at 0x7ed61000 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES 1. 0000000000001000-000000000009ffff: RAM 2. 00000000000a0000-00000000000fffff: RESERVED 3. 0000000000100000-000000007ed3bfff: RAM 4. 000000007ed3c000-000000007eeb3fff: CONFIGURATION TABLES 5. 000000007eeb4000-000000007effdfff: RAMSTAGE 6. 000000007effe000-000000007effffff: CONFIGURATION TABLES 7. 000000007f000000-000000008fffffff: RESERVED 8. 00000000fbffc000-00000000fbffdfff: RESERVED 9. 00000000feb00000-00000000feb0ffff: RESERVED10. 00000000feb80000-00000000feefffff: RESERVED11. 00000000ff000000-00000000ffffffff: RESERVED12. 0000000100000000-000000017fffffff: RAMManufacturer: efSF: Detected W25Q128_V with sector size 0x1000, total 0x1000000SF size 0x1000000 does not correspond to CONFIG_ROM_SIZE 0x800000!!CBFS: 'Master Header Locator' located CBFS at [200200:800000)FMAP: Found "FLASH" version 1.1 at 200000.FMAP: base = ff800000 size = 800000 #areas = 3Wrote coreboot table at: 7ed61000, 0x2dc bytes, checksum 8e02coreboot table: 756 bytes.IMD ROOT 0. 7efff000 00001000IMD SMALL 1. 7effe000 00001000RAMSTAGE 2. 7eeb3000 0014b00057a9e100 3. 7ed69000 00149958COREBOOT 4. 7ed61000 00008000ACPI 5. 7ed3d000 00024000SMBIOS 6. 7ed3c000 00000800IMD small region: IMD ROOT 0. 7effec00 00000400 HOB 1. 7effebe0 00000001 57a9e000 2. 7effebc0 00000018 COREBOOTFWD 3. 7effeb80 00000028BS: BS_WRITE_TABLES times (us): entry 548230 run 1517156 exit 6302CBFS: 'Master Header Locator' located CBFS at [200200:800000)CBFS: Locating 'fallback/payload'CBFS: Found @ offset 113340 size 109ccChecking segment from ROM address 0xffb13578Payload being loaded at below 1MiB without region being marked as RAM usable.Checking segment from ROM address 0xffb13594Loading segment from ROM address 0xffb13578 code (compression=1) New segment dstaddr 0x000e0700 memsize 0x1f900 srcaddr 0xffb135b0 filesize 0x10994Loading Segment: addr: 0x000e0700 memsz: 0x000000000001f900 filesz: 0x0000000000010994using LZMALoading segment from ROM address 0xffb13594 Entry Point 0x000fd258BS: BS_PAYLOAD_LOAD times (us): entry 6301 run 124327 exit 6302FspNotify(EnumInitPhaseReadyToBoot)FSP Header Version: 1FSP Revision: 3.3Returned from FspNotify(EnumInitPhaseReadyToBoot)Jumping to boot code at 000fd258(7ed61000)SeaBIOS (version rel-1.12.1-0-ga5cab58)BUILD: gcc: (coreboot toolchain v ) 8.3.0 binutils: (GNU Binutils) 2.32Found mainboard Intel Camelback Mountain CRBRelocating init from 0x000e1d60 to 0x7ecef560 (size 51712)Found CBFS header at 0xffa00238multiboot: eax=7eed3a40, ebx=7eed39f4Found 22 PCI devices (max PCI bus is 04)Copying SMBIOS entry point from 0x7ed3c000 to 0x000f6280Copying ACPI RSDP from 0x7ed3d000 to 0x000f6250Using pmtimer, ioport 0x408Scan for VGA option romTurning on vga text mode consoleSeaBIOS (version rel-1.12.1-0-ga5cab58)XHCI init on dev 00:14.0: regs @ 0xfb900000, 21 ports, 32 slots, 32 byte contextsXHCI protocol USB 2.00, 8 ports (offset 1), def 3001XHCI protocol USB 3.00, 6 ports (offset 16), def 1000XHCI extcap 0xc1 @ 0xfb908040XHCI extcap 0xc0 @ 0xfb908070XHCI extcap 0x1 @ 0xfb90846cWARNING - Timeout at i8042_flush:71!AHCI controller at 00:1f.2, iobase 0xfb913000, irq 5Found 0 lpt portsFound 1 serial portsSearching bootorder for: /rom@img/uefiXHCI no devices foundAll threads complete.Scan for option romsPress ESC for boot menu.Searching bootorder for: HALTSpace available for UMB: c0000-ed000, f5aa0-f6230Returned 192512 bytes of ZoneHighe820 map has 10 items: 0: 0000000000000000 - 000000000009fc00 = 1 RAM 1: 000000000009fc00 - 00000000000a0000 = 2 RESERVED 2: 00000000000f0000 - 0000000000100000 = 2 RESERVED 3: 0000000000100000 - 000000007ed2b000 = 1 RAM 4: 000000007ed2b000 - 0000000090000000 = 2 RESERVED 5: 00000000fbffc000 - 00000000fbffe000 = 2 RESERVED 6: 00000000feb00000 - 00000000feb10000 = 2 RESERVED 7: 00000000feb80000 - 00000000fef00000 = 2 RESERVED 8: 00000000ff000000 - 0000000100000000 = 2 RESERVED 9: 0000000100000000 - 0000000180000000 = 1 RAMenter handle_19: NULLBooting from CBFS...Run img/uefi*

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Intel CPU C2000(Rangeley)/C3000(Denverton)/D-1500(Broadwell-DE) supported in coreboot?
by ivan_yang 楊益昌 Dec. 2, 2019

Dec. 2, 2019

Hi Sir, As you listed that motherboards supported in coreboot. https://coreboot.org/status/board-status.html May we know that when can support Intel CPU C2000(Rangeley)/C3000(Denverton)/D-1500(Broadwell-DE) in coreboot? Thanks. BR, Ivan Yang [Accton] Senior BIOS Engineer Tel: +886 3 5770270 ext.3145 Mobile: +886-936611768 Fax:+886 3 578-7550 Email: ivan_yang(a)accton.com<mailto:ivan_yang@accton.com> Address: 1, Creation Road 3, Hsinchu Science Park, Hsinchu 30077, Taiwan, R.O.C.

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x86_64 support needs review
by Patrick Rudolph Dec. 2, 2019

Dec. 2, 2019

Hi folks, While working on x86_64 support for the qemu mainboard target I gave it a try on real hardware and I got my machine booting with only 3 additional patches. The current solution seems to work without problems with the following specs: * All stages are compiled in x86_64 * page tables are static and reside in ROM * Memory above 4GiB isn't accessible yet Tested on: * Intel Nehalem * Intel Ibexpeak * EHCI debug enabled Please test and review: https://review.coreboot.org/q/topic:%22x86_64_support2%22+(status:open) https://review.coreboot.org/q/topic:"x86_64_support_real_hardware"+(status:open) Kind Regards, Patrick

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msr
by daniel.kouba＠live.com Dec. 1, 2019

Dec. 1, 2019

Hello all, I am newbie to this topic so be patient with me. I am struggling with my old H61 board to change few MSRs for Multiplier unlock attempt. The installed Cpu i7-3770s has hidden 400 Mhz potencial into itself, so I like give it to try. I tried modding BIOS on MSR 0x194 to remove Lock bit 20, but without access. The reason is because platform info MSR 0xCE bit 28 is set to 0, so I cant unlocked those 0x194 or multiplier MSR 0x1AD according to the Intel docs. I am not educated at programing at all, so I dont know how to modding that 0xCE bit 28 in BIOS, particulary this is R/O status register. My point is - could I assume that coreboot firmware is setting that MSR 0xCE bit 28 to 1, because of customer friendly firmware and if so, can I running coreboot on my Lenovo B320 (H61, IVB cpu, ME transplanted to 8 version), Win 7? Also I can flashing at the Windows, with R/W access to all SPI sections Thanks for your replay guys!

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