coreboot December 2019

coreboot@coreboot.org

50 participants
45 discussions

Call to FSP_FSP_INIT never returns back
by Naveen Chaudhary 13 Dec '19

13 Dec '19

Hi All, Need some guidance. Please read. I am porting coreboot for a "Broadwell D 1519" based motherboard which has both Memory Down as well as 2 DIMM slots. Hence, I built an image for Facebook Watson since its the closest mainboard with no code changes. The call from FSP_FSP_INIT never returns to the ChipsetFspReturnPoint( ). Probably something crashed inside the FSP or something else. This is possibly happening because I have passed no information regarding the RAM chips (down or DIMM) from romstage_fsp_rt_buffer_callback(). I have following 2 questions : 1. How can I see the default values for FSP UDP structure, so that I get to know what I need to modify? BCT tool does not dump that info. 2. In intel/soc/fsp_broadwell/ , the save_dimm_info() is done after FSP_FSP_INIT returns. Shouldn't the SPD details have been fetched before and passed to the FSP_FSP_INIT, as it is this API that handles the memory init. Regards, Naveen

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Re: coreboot with seabios as payload
by Ashmita Chakraborty 11 Dec '19

11 Dec '19

Hi, I have some problem in SeaBIOS. USB keyboard and USB mouse are not detected. EHCI and OHCI are enabled. I cannot use my keyboard in my SeaBIOS. USB keyboard and USB mouse are enabled in SeaBIOS .config . The Linux kernel does detect them and I can use them in Linux. Some timeout is happening. Following is the part of the debug message where only keyboard is attached: Searching bootorder for: /pci@i0cf8/*@1f,2/drive@0/disk@0 AHCI/0: Set transfer mode to UDMA-6 AHCI/0: registering: "AHCI/0: WDC WD5000AZLX-00CL5A0 ATA-9 Hard-Disk (465 GiBytes)" Found 0 lpt ports Found 1 serial ports Searching bootorder for: /rom@img/uefi XHCI no devices found USB keyboard initialized WARNING - Timeout at ehci_wait_td:517! ehci pipe=0x7ecec300 cur=7eccfdc0 tok=00000c00 next=7ecced40 td=0x7ecced40 status=80e80 WARNING - Timeout at ehci_waittick:178! Failure on hub port 3 reset WARNING - Timeout at ehci_wait_td:517! ehci pipe=0x7ecec300 cur=7eccfdc0 tok=00000000 next=7ecced40 td=0x7ecced40 status=80e80 WARNING - Timeout at ehci_waittick:165! Failure on hub port 3 disconnect WARNING - Timeout at ehci_wait_td:517! ehci pipe=0x7ecec300 cur=7eccfdc0 tok=00000000 next=7eccfd40 td=0x7eccfd40 status=80e80 WARNING - Timeout at ehci_waittick:165! Failure on hub port 2 detect WARNING - Timeout at ehci_wait_td:517! ehci pipe=0x7ecec300 cur=7eccfdc0 tok=00000000 next=7ecd0d40 td=0x7ecd0d40 status=80e80 WARNING - Timeout at ehci_waittick:165! Failure on hub port 1 detect Initialized USB HUB (1 ports used) WARNING - Timeout at ehci_waittick:165! All threads complete. Scan for option roms Press ESC for boot menu. I have attached the debug log.txt file as reference. Regards, AC L&T Technology Services Ltd www.LTTS.com L&T Technology Services Limited (LTTS) is committed to safeguard your data privacy. For more information to view our commitment towards data privacy under GDPR, please visit the privacy policy on our website www.Ltts.com. This Email may contain confidential or privileged information for the intended recipient (s). If you are not the intended recipient, please do not use or disseminate the information, notify the sender and delete it from your system.

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AMD Agesa Bettong board support
by Jorge Fernandez Monteagudo 11 Dec '19

11 Dec '19

Hi, I'm trying to generate a coreboot.rom for this AMD development board and update a board status report in order to avoid deprecation this board. I'm using the commit f77f2c79c2bb898c123ffe89a0bd1acb5362afc5 (just one before a0a50775) and I get some compilation errors. The first is from iasl compiling the dsdt.asl file: Intel ACPI Component Architecture ASL+ Optimizing Compiler/Disassembler version 20191018 Copyright (c) 2000 - 2019 Intel Corporation coreboot toolchain v547de69 2019-10-18 Error 6154 - Warnings detected during compilation (reporting warnings as errors) dsdt.asl 403: Device(PCI0) { Warning 3073 - ^ Multiple types (Device object requires either a _HID or _ADR, but not both) dsdt.asl 1061: Method (_CRS, 0x0, NotSerialized) { Remark 2120 - ^ Control Method should be made Serialized (due to creation of named objects within) ASL Input: dsdt.asl - 22455 bytes 598 keywords 1154 source lines Compilation failed. 1 Errors, 1 Warnings, 1 Remarks No AML files were generated due to compiler error(s) The same file with the iasl tool generated by the 4.10 release toolchain works ok. The second one is from src/commonlib/include/commonlib/helpers.h. I get the next error: HOSTCC cbfstool/cbfstool.o In file included from <command-line>:0:0: /mnt/develop/bettong/coreboot/develop/coreboot/util/cbfstool/cbfstool.c: In function 'cbfs_add_component': /mnt/develop/bettong/coreboot/develop/coreboot/src/commonlib/include/commonlib/compiler.h:57:2: error: first argument to '__builtin_choose_expr' not a constant __builtin_choose_expr(__builtin_constant_p(expr), fallback_expr, expr)) ^ /mnt/develop/bettong/coreboot/develop/coreboot/src/commonlib/include/commonlib/helpers.h:39:2: note: in expansion of macro '__TYPEOF_UNLESS_CONST' __TYPEOF_UNLESS_CONST(a, b) var_a = (a); \ ^ /mnt/develop/bettong/coreboot/develop/coreboot/src/commonlib/include/commonlib/helpers.h:49:26: note: in expansion of macro '__CMP_SAFE' __CMP_UNSAFE(a, b, op), __CMP_SAFE(a, b, op, __TMPNAME, __TMPNAME)) ^ /mnt/develop/bettong/coreboot/develop/coreboot/src/commonlib/include/commonlib/helpers.h:56:19: note: in expansion of macro '__CMP' #define MAX(a, b) __CMP(a, b, >) ^ /mnt/develop/bettong/coreboot/develop/coreboot/util/cbfstool/cbfstool.c:560:19: note: in expansion of macro 'MAX' uint32_t size = MAX(hs, param.padding); ^ /mnt/develop/bettong/coreboot/develop/coreboot/src/commonlib/include/commonlib/compiler.h:57:2: error: first argument to '__builtin_choose_expr' not a constant __builtin_choose_expr(__builtin_constant_p(expr), fallback_expr, expr)) ^ /mnt/develop/bettong/coreboot/develop/coreboot/src/commonlib/include/commonlib/helpers.h:40:2: note: in expansion of macro '__TYPEOF_UNLESS_CONST' __TYPEOF_UNLESS_CONST(b, a) var_b = (b); \ ^ /mnt/develop/bettong/coreboot/develop/coreboot/src/commonlib/include/commonlib/helpers.h:49:26: note: in expansion of macro '__CMP_SAFE' __CMP_UNSAFE(a, b, op), __CMP_SAFE(a, b, op, __TMPNAME, __TMPNAME)) ^ /mnt/develop/bettong/coreboot/develop/coreboot/src/commonlib/include/commonlib/helpers.h:56:19: note: in expansion of macro '__CMP' #define MAX(a, b) __CMP(a, b, >) ^ /mnt/develop/bettong/coreboot/develop/coreboot/util/cbfstool/cbfstool.c:560:19: note: in expansion of macro 'MAX' uint32_t size = MAX(hs, param.padding); ^ In file included from /mnt/develop/bettong/coreboot/develop/coreboot/util/cbfstool/common.h:25:0, from /mnt/develop/bettong/coreboot/develop/coreboot/util/cbfstool/cbfstool.c:28: /mnt/develop/bettong/coreboot/develop/coreboot/src/commonlib/include/commonlib/helpers.h:47:25: error: first argument to '__builtin_choose_expr' not a constant #define __CMP(a, b, op) __builtin_choose_expr( \ ^ /mnt/develop/bettong/coreboot/develop/coreboot/src/commonlib/include/commonlib/helpers.h:56:19: note: in expansion of macro '__CMP' #define MAX(a, b) __CMP(a, b, >) ^ /mnt/develop/bettong/coreboot/develop/coreboot/util/cbfstool/cbfstool.c:560:19: note: in expansion of macro 'MAX' uint32_t size = MAX(hs, param.padding); ^ In file included from <command-line>:0:0: /mnt/develop/bettong/coreboot/develop/coreboot/util/cbfstool/cbfstool.c: In function 'cbfs_create': /mnt/develop/bettong/coreboot/develop/coreboot/src/commonlib/include/commonlib/compiler.h:57:2: error: first argument to '__builtin_choose_expr' not a constant __builtin_choose_expr(__builtin_constant_p(expr), fallback_expr, expr)) ^ /mnt/develop/bettong/coreboot/develop/coreboot/src/commonlib/include/commonlib/helpers.h:39:2: note: in expansion of macro '__TYPEOF_UNLESS_CONST' __TYPEOF_UNLESS_CONST(a, b) var_a = (a); \ ^ /mnt/develop/bettong/coreboot/develop/coreboot/src/commonlib/include/commonlib/helpers.h:49:26: note: in expansion of macro '__CMP_SAFE' __CMP_UNSAFE(a, b, op), __CMP_SAFE(a, b, op, __TMPNAME, __TMPNAME)) ^ /mnt/develop/bettong/coreboot/develop/coreboot/src/commonlib/include/commonlib/helpers.h:56:19: note: in expansion of macro '__CMP' #define MAX(a, b) __CMP(a, b, >) ^ /mnt/develop/bettong/coreboot/develop/coreboot/util/cbfstool/cbfstool.c:971:6: note: in expansion of macro 'MAX' MAX(bootblock.size, sizeof(int32_t)); ^ In file included from /mnt/develop/bettong/coreboot/develop/coreboot/util/cbfstool/common.h:25:0, from /mnt/develop/bettong/coreboot/develop/coreboot/util/cbfstool/cbfstool.c:28: /mnt/develop/bettong/coreboot/develop/coreboot/src/commonlib/include/commonlib/helpers.h:47:25: error: first argument to '__builtin_choose_expr' not a constant #define __CMP(a, b, op) __builtin_choose_expr( \ ^ /mnt/develop/bettong/coreboot/develop/coreboot/src/commonlib/include/commonlib/helpers.h:56:19: note: in expansion of macro '__CMP' #define MAX(a, b) __CMP(a, b, >) ^ /mnt/develop/bettong/coreboot/develop/coreboot/util/cbfstool/cbfstool.c:971:6: note: in expansion of macro 'MAX' MAX(bootblock.size, sizeof(int32_t)); ^ make: *** [build/util/cbfstool/cbfstool.o] Error 1 I can generate the coreboot.rom using the old iasl tool and patching helpers.h with: @@ -50,10 +50,10 @@ #endif #ifndef MIN -#define MIN(a, b) __CMP(a, b, <) +#define MIN(a, b) ((a) < (b) ? (a) : (b)) #endif #ifndef MAX -#define MAX(a, b) __CMP(a, b, >) +#define MAX(a, b) ((a) > (b) ? (a) : (b)) #endif #ifndef ABS but the board_status.sh script then complains $ ./util/board_status/board_status.sh Extracting config.txt from build/coreboot.rom Extracting payload_config from build/coreboot.rom The repository is in a dirty state. Please see the output of 'git status' below. HEAD detached at f77f2c7 Changes not staged for commit: (use "git add <file>..." to update what will be committed) (use "git checkout -- <file>..." to discard changes in working directory) modified: src/commonlib/include/commonlib/helpers.h no changes added to commit (use "git add" and/or "git commit -a") How to proceed? Thanks! Jorge

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Comment on story about bootloader security?
by Seth Rosenblatt 11 Dec '19

11 Dec '19

Hello Coreboot community, I'm writing a story on new research by Ilja van Sprundel and Joseph Tartaro demonstrating vulnerabilities in bootloaders, including some in Coreboot. Would love to chat with someone involved in the project - is that possible? -- Seth Rosenblatt Editor-in-Chief, The Parallax <http://www.the-parallax.com/> Phone/Signal/WhatsApp: 415-730-3194 Follow me: Twitter <https://twitter.com/sethr> | Facebook <https://www.facebook.com/Seth.E.Rosenblatt> | Instagram <https://instagram.com/sethr/> | LinkedIn <https://www.linkedin.com/in/rosenblattseth> | Google+ <https://plus.google.com/u/0/+SethRosenblatt> Follow The Parallax: Twitter <https://twitter.com/theparallax> | Facebook <https://www.facebook.com/TheParallaxNews> | Instagram <https://instagram.com/parallax/> | LinkedIn <https://www.linkedin.com/company/the-parallax> | Google+ <https://plus.google.com/+theparallax>

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FOSDEM Hardware Enablement Devroom: call for speakers.
by Luc Verhaegen 10 Dec '19

10 Dec '19

Hi, At FOSDEM on sunday the 2nd of february 2020, there will be another hardware enablement DevRoom. URL: https://fosdem.org/2020/ This devroom covers topics related to hardware support and enablement with free software. It includes the following topics: * peripheral/controller firmwares * hw support and drivers in bootloaders * kernel drivers and hardware interfaces * hardware-related adaptation in operating systems * tools for firmware flashing * tools for low-level development FOSDEM is very much an open source community event, please refrain from turning in a talk that is meant to be purely corporate or a product commercial. Also, this is a highly technical devroom on a conference aimed at developers and advanced users, so only submit a talk on a subject you actually are involved with. Finally, this devrooms focus is the technical aspects of the hardware and its enablement in free projects, rather than the specific applications and use cases that benefit from it. With the return of the Embedded and Automotive DevRoom, we have the ability to schedule full hour talks again, and to go in-depth. If you however only need half an hour, then this is of course also possible. Talk Submission: The venerable pentabarf system will once again be used for talk submission. https://penta.fosdem.org/submission/FOSDEM20 When in pentabarf, spend some time on the abstract and description, for both the event and the speaker. The abstract should be a shortened description, and the event abstract will sometimes even be printed directly in the booklet. BUT, on the website the abstract is immediately followed by the full description. If your abstract is fully descriptive, while terse, you might get away with just the abstract. As soon as your talk is scheduled by the devroom managers, you can see the result of your handiwork on the main website. Please re-use your old pentabarf account instead of creating a new one: lost password: https://penta.fosdem.org/user/forgot_password Talks are either 50 minutes or 20 minutes long, plus 5 minutes for questions. All talks will be recorded, and will be streamed out live, and will later be made available as CC-BY, sometimes minutes after your talk has finished. As for deadlines, the fosdem organizers want to have a finished schedule by the 15th of december, but do not count on that deadline, there are only a limited number of slots available. Given my belatedness in sending out this CFP, i might get a few more days if i am really really nice to the core FOSDEM organizers, but again, do not count on that (extra hugs only go so far when you're built like i am). On your personal page: * General: * First and last name * Nickname * Image * Contact: * email address * mobile number (this is a very hard requirement as there will be no other reliable form of emergency communication on the day) * Description: * Abstract * Description Create an event: * On the General page: * Event title * Event subtitle. * Track: Hardware Enablement Devroom * Event type: Lecture (talk) or Meeting (BoF) * Persons: * Add yourself as speaker. * Description: * Abstract: * Full Description * Schedule: * select your preferred talk length, either 55 or 25 minutes. * Links: * Add relevant links. The mobile phone number is the hardest requirement, so you can be contacted on-the-day when something comes up. Speakers will all receive my mobile number in return. Neither email nor phonenumber are publicy visible, nor will this information be used for anything outside of devroom organization. After your talk has been scheduled, i usually only send out a single email with some organizational details in the days before the event. Everything else can be ignored or will be filled in by me or the FOSDEM organizers. I will be keeping a keen eye on your submissions and will come back with further questions or make small fixes as needed. Feel free to poke me with any questions or anything, both on irc (libv@freenode) and on email (hardware-devroom-manager(a)fosdem.org). That's about it. Hope to see you all at FOSDEM :) Luc Verhaegen.

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Re: [coreboot-gerrit] Change in coreboot[master]: Add Kyösti Mälkki <kyosti.malkki@gmail.com> patch files:
by Дмитрий Понаморев 10 Dec '19

10 Dec '19

Abandon all? I abandoned 4 last commit... вт, 10 дек. 2019 г. в 16:47, Дмитрий Понаморев (Code Review) < gerrit(a)coreboot.org>: > Дмитрий Понаморев *abandoned* this change. > > View Change <https://review.coreboot.org/c/coreboot/+/37636> > Abandoned > > To view, visit change 37636 > <https://review.coreboot.org/c/coreboot/+/37636>. To unsubscribe, or for > help writing mail filters, visit settings > <https://review.coreboot.org/settings>. > Gerrit-Project: coreboot > Gerrit-Branch: master > Gerrit-Change-Id: I1c96a6ee86b0d01e9059558f754d001acdb3ed6a > Gerrit-Change-Number: 37636 > Gerrit-PatchSet: 1 > Gerrit-Owner: Дмитрий Понаморев <dponamorev(a)gmail.com> > Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> > Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> > Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> > Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> > Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> > Gerrit-Reviewer: Дмитрий Понаморев <dponamorev(a)gmail.com> > Gerrit-MessageType: abandon > _______________________________________________ > coreboot-gerrit mailing list -- coreboot-gerrit(a)coreboot.org > To unsubscribe send an email to coreboot-gerrit-leave(a)coreboot.org >

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Tianocore: Long time to boot / Menu.
by Jose Trujillo 10 Dec '19

10 Dec '19

Hello All: I am using the default Tianocore stable (Mr. Chromebox Matt version?) but is taking: 2minutes 30seconds from the appearance of the logo to the Tiano menu / grub bootloader. After entering the payload there is no more serial debug output. Anyone had this issue and knows the fix. Anyone of you know how to enable the serial debug output to Tiano. Any help will be very much appreciated. Thank you, Jose Trujillo.

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[ANNOUNCE] SeaBIOS 1.13.0
by Kevin O'Connor 09 Dec '19

09 Dec '19

The 1.13.0 version of SeaBIOS has now been released. For more information on the release, please see: http://seabios.org/Releases New in this release: * Support for reading logical CHS drive information from QEMU * Workaround added for misbehaving optionroms that grab "int19" * The TPM 2 "PCR bank" option can now be set from the TPM menu * SeaVGABIOS support for QEMU "atiext" display * Several bug fixes and code cleanups For information on obtaining SeaBIOS, please see: http://seabios.org/Download ===== git shortlog -n rel-1.12.0..rel-1.13.0 ===== Gerd Hoffmann (25): vga: move modelist from bochsvga.c to new svgamodes.c vga: make memcpy_high() public vga: add atiext driver vga: add ati bios tables vbe: add edid support. ati: add edid support. bochsvga: add edid support. bochsdisplay: add edid support. bochsdisplay: parse resolution from edid. add get_keystroke_full() helper bootmenu: add support for more than 9 entries optionrom: disallow int19 redirect for pnp roms. ati-vga: make less verbose ati-vga: fix ati_read() ati-vga: make i2c register and bits configurable ati-vga: try vga ddc first ati-vga: add rage128 edid support bochsdisplay: add copyright and license to bochsdisplay.c ramfb: add copyright and license to ramfb.c cp437: add license to cp437.c ahci: zero-initialize port struct Revert "geometry: Apply LCHS values for boot devices" Revert "config: Add toggle for bootdevice information" Revert "geometry: Add boot_lchs_find_*() utility functions" Revert "geometry: Read LCHS from fw_cfg" Kevin O'Connor (11): output: Avoid thunking to 16bit mode in printf() if no vgabios docs: Update mailing list archive links docs: Fix cut-and-paste error in Mailinglist.md archive link usb-ehci: Clear pipe token on pipe reallocate pciinit: Use %pP shorthand for printing device ids in intel_igd_setup() virtio-pci: Use %pP format in dprintf() calls Makefile: Build with -Wno-address-of-packed-member svgamodes: Add copyright notice to vgasrc/svgamodes.c docs: Add developer-certificate-of-origin docs: Note release date for v1.12.1 docs: Note v1.13.0 release Sam Eiderman (10): smbios: Add missing zero byte to Type 0 geometry: Read LCHS from fw_cfg boot: Reorder functions in boot.c geometry: Add boot_lchs_find_*() utility functions config: Add toggle for bootdevice information geometry: Apply LCHS values for boot devices geometry: Read LCHS from fw_cfg boot: Build ata and scsi paths in function geometry: Add boot_lchs_find_*() utility functions geometry: Apply LCHS values for boot devices Stefan Berger (4): tcgbios: Use table to convert hash to buffer size tcgbios: Implement TPM 2.0 menu item to activate and deactivate PCR banks tpm: Require a response to have minimum size of a valid response header tcgbios: Check for enough bytes returned from TPM2_GetCapability Uwe Kleine-König (3): cbvga: reuse svga modes definitions from svgamodes.c Add additional resolutions for 16:9 displays: 1600x900 and 2560x1440 Remove dos line endings introduced in the last two commits David Woodhouse (2): csm: Sanitise alignment constraint in Legacy16GetTableAddress csm: Fix boot priority translation Denis Plotnikov (1): virtio: extend virtio queue size to 256 Joseph Pacheco-Corwin (1): bootsplash: Added support for 16/24/32bpp in one function Liran Alon (1): pvscsi: ring_desc do not have to be page aligned Stefano Garzarella (1): qemu: avoid debug prints if debugcon is not enabled Stephen Douthit (1): tpm: Check for TPM related ACPI tables before attempting hw probe

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Re: How to push to board_status repo?
by Mike Banon 09 Dec '19

09 Dec '19

My guess is that maybe you've configured this repo incorrectly. After logging in to review coreboot org , go to https://review.coreboot.org/admin/repos/board-status and copy a HTTP command for cloning, like " git clone "https://mikebdp@review.coreboot.org/a/board-status" && (cd "board-status" && mkdir -p .git/hooks && curl -Lo `git rev-parse --git-dir`/hooks/commit-msg https://mikebdp@review.coreboot.org/tools/hooks/commit-msg; chmod +x `git rev-parse --git-dir`/hooks/commit-msg) " , with mikebdp replaced by your username there (but better to copy it from HTTP tab to avoid accidental mistakes). Then copy the files you would like to commit to this repository, commit and push, and it should only ask your password, without a username. On Sun, Dec 8, 2019 at 11:37 AM Mike Banon <mikebdp2(a)gmail.com> wrote: > > My guess is that maybe you've configured this repo incorrectly. After > logging in to review coreboot org , go to > https://review.coreboot.org/admin/repos/board-status and copy a HTTP > command for cloning, like " git clone > "https://mikebdp@review.coreboot.org/a/board-status" && (cd > "board-status" && mkdir -p .git/hooks && curl -Lo `git rev-parse > --git-dir`/hooks/commit-msg > https://mikebdp@review.coreboot.org/tools/hooks/commit-msg; chmod +x > `git rev-parse --git-dir`/hooks/commit-msg) " , with mikebdp replaced > by your username there (but better to copy it from HTTP tab to avoid > accidental mistakes). Then copy the files you would like to commit to > this repository, commit and push, and it should only ask your > password, without a username. > > On Wed, Dec 4, 2019 at 5:17 PM Jorge Fernandez Monteagudo > <jorgefm(a)cirsa.com> wrote: > > > > Hi all, > > > > I've generated a new entry in util/board_status/board-status/amd/bettong/4.10-6-g12ec481/2019-12-04T13_27_01Z/ > > but I'm not able to push the changes. > > > > I'm able to entry in to https://review.coreboot.org/settings/ and I can see my HTTP credentials with my github user name > > and I've generated a new password pushing the button but then I try to do a push and always get: > > > > $ cd util/board_status/board-status > > $ git push > > Username for 'https://review.coreboot.org': jorgefm1900 > > Password for 'https://jorgefm1900@review.coreboot.org': > > fatal: Authentication failed for 'https://review.coreboot.org/board-status.git/' > > > > Any resource to configure a review.coreboot.org repo user? I've tried to change the password through Github creating a > > personal access token without luck... > > > > Thanks! > > _______________________________________________ > > coreboot mailing list -- coreboot(a)coreboot.org > > To unsubscribe send an email to coreboot-leave(a)coreboot.org

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Intel Atom C2000 SOC - Do they lack Intel ME?
by Kinky Nekoboi 09 Dec '19

09 Dec '19

Hello folks i sadly had to replace KGPE-d16 board for my fileserver to a Supermicro A1SRi-C2558 because of electric pill .... investigating a bit with intelmetool and mecleaner non of them could found any sign for an ME-region in this board.. so i asking myself if there is no ME/SPS on the intel C2000 socs, what would make them a DAMN SEXY platform to port coreboot too. Here my investigations: root@lain:~# /speedy/foo/Downloads/coreboot/util/intelmetool/intelmetool -m -d ME PCI device is hidden RCBA addr: 0xfed1c000 MEI was hidden on PCI, now unlocked Re-hiding MEI device...done Can't find ME PCI device ./me_cleaner/me_cleaner.py -c Supermicro_Firmware/A1SAi18_118/A1SAi18.118 Full image detected The ME region in this image has already been disabled The HAP bit is NOT SET Checking the FTPR RSA signature... Traceback (most recent call last): File "./me_cleaner/me_cleaner.py", line 955, in <module> print_check_partition_signature(mef, ftpr_offset + ftpr_mn2_offset) NameError: name 'mef' is not defined binwalk Supermicro_Firmware/A1SAi18_118/A1SAi18.118 DECIMAL HEXADECIMAL DESCRIPTION -------------------------------------------------------------------------------- 2097152 0x200000 UEFI PI Firmware Volume, volume size: 131072, header size: 0, revision: 0, EFI Firmware File System v2, GUID: 8C8CE578-8A3D-4F1C-3599-896185C32DD3 2555904 0x270000 UEFI PI Firmware Volume, volume size: 3932160, header size: 96, revision: 0, EFI Firmware File System v2, GUID: 8C8CE578-8A3D-4F1C-3599-896185C32DD3 2629664 0x282020 Microsoft executable, portable (PE) 4325602 0x4200E2 Copyright string: "Copyright (C) %04x American Megatrends, Inc. " 6488064 0x630000 UEFI PI Firmware Volume, volume size: 262144, header size: 0, revision: 0, EFI Firmware File System v2, GUID: 8C8CE578-8A3D-4F1C-3599-896185C32DD3 6946816 0x6A0000 UEFI PI Firmware Volume, volume size: 1441792, header size: 96, revision: 0, EFI Firmware File System v2, GUID: 8C8CE578-8A3D-4F1C-3599-896185C32DD3 6947360 0x6A0220 Microsoft executable, portable (PE) 6971232 0x6A5F60 Microsoft executable, portable (PE) 6981408 0x6A8720 Microsoft executable, portable (PE) 6983616 0x6A8FC0 Microsoft executable, portable (PE) 6985504 0x6A9720 Microsoft executable, portable (PE) 6986144 0x6A99A0 Microsoft executable, portable (PE) 6988896 0x6AA460 Microsoft executable, portable (PE) 6991360 0x6AAE00 Microsoft executable, portable (PE) 6995264 0x6ABD40 Microsoft executable, portable (PE) 6997056 0x6AC440 Microsoft executable, portable (PE) 6998816 0x6ACB20 Microsoft executable, portable (PE) 7000553 0x6AD1E9 gzip compressed data, ASCII, has header CRC, has original file name: "", last modified: 2104-12-22 18:41:23 (bogus date) 7001792 0x6AD6C0 Microsoft executable, portable (PE) 7004576 0x6AE1A0 Microsoft executable, portable (PE) 7152192 0x6D2240 Microsoft executable, portable (PE) 7156928 0x6D34C0 Microsoft executable, portable (PE) 7164096 0x6D50C0 Microsoft executable, portable (PE) 7171040 0x6D6BE0 Microsoft executable, portable (PE) 7175872 0x6D7EC0 Microsoft executable, portable (PE) 7177536 0x6D8540 Microsoft executable, portable (PE) 7178688 0x6D89C0 Microsoft executable, portable (PE) 7182144 0x6D9740 Microsoft executable, portable (PE) 7188576 0x6DB060 Microsoft executable, portable (PE) 7203776 0x6DEBC0 Microsoft executable, portable (PE) 7253696 0x6EAEC0 Microsoft executable, portable (PE) 7263136 0x6ED3A0 Microsoft executable, portable (PE) 7263871 0x6ED67F mcrypt 2.2 encrypted data, algorithm: blowfish-448, mode: CBC, keymode: 8bit 7270688 0x6EF120 Microsoft executable, portable (PE) 7272480 0x6EF820 Microsoft executable, portable (PE) 7279008 0x6F11A0 Microsoft executable, portable (PE) 7304768 0x6F7640 Microsoft executable, portable (PE) 7307968 0x6F82C0 Microsoft executable, portable (PE) 7313952 0x6F9A20 Microsoft executable, portable (PE) 7317152 0x6FA6A0 Microsoft executable, portable (PE) 7318048 0x6FAA20 Microsoft executable, portable (PE) 7322016 0x6FB9A0 Microsoft executable, portable (PE) 8384152 0x7FEE98 Microsoft executable, portable (PE)

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coreboot December 2019