coreboot December 2019

coreboot@coreboot.org

50 participants
45 discussions

fundraising for laptop drivers & firmware?
by abmwinter＠gmail.com 08 Dec '19

08 Dec '19

Hi, I'm researching an article about funding drivers & firmware for linux on mainstream hardware. I'm a huge fan of coreboot/seabios & feel both excited for life after binary blobs and frustrated at how difficult it is to ship OSS firmware. Looking for any and all feedback but tag in especially if you know about: * what skill-sets the community needs to develop these without industry support * $$ figures for driver development in-house at major shops * are OSS firmware projects trying to support mainstream laptops on launch? are manufacturers interested? Have had a series of linux laptops as my daily drivers for ~ 4 years -- am grateful for the work the community is doing.

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Build seems to have broken for asus/p2b-*
by Keith Hui 08 Dec '19

08 Dec '19

Hi guys, I finally have a chance to sit down and update my local coreboot repo. To make sure it works I tried to build for asus/p2b-ls,p2b-d,p2b-ds... my usual i440bx boards. But my build is now failing. I'd get: CREATE build/mainboard/asus/p2b-ls/cbfs-file.kMfK0Y.out (from /usr/src/coreboot/.config) make: *** [src/cpu/Makefile.inc:44: build/cpu_microcode_blob.bin] Error 1 That makefile line seems to indicate that some CPU microcode file is not there. Just want ask somebody else to also try building for these boards and confirm if it is just me, as some people have been able to boot test some recent i440bx changes and one has to be able to build to be able to test. Thanks Keith

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Porting Asrock P67 pro
by Robin C 07 Dec '19

07 Dec '19

Hi everyone, I'm trying to port my P67 pro (as others but due to lack of time this one at least) on coreboot. Here is the repo I use for my tests: https://github.com/skollrc/Asrock-P67-Pro-port . I'm also trying to port GA-G33M-DS2R and H81M-ITX boards but the P67 Pro is my priority. The DS2R board will require more time to be fully functional and I don't have a heavy use of the ITX board. Is there anyone interested in helping me to test or work on the port? I have a newborn child and a time consumer job so I have not as much time as I would like to finish the job... best regard Robin

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Sandybridge-M help request in setting up LVDS panel.
by Jose Trujillo 05 Dec '19

05 Dec '19

Hello All! This is my first try in booting coreboot on a LVDS panel. This is a Sandybridge-M system using video option ROM and VBT extracted from the original FW. The coreboot source was created using autoport. This same project boots to the OS using regular external DVI display. The panel doesn't have i2c ROM (DDC). Using the LCD LVDS panel shows the following in the screen and halts with post code 75 "Intel(R)Sandybridge Mobile PCI Accelerated SVGA BIOS" "DECOMPILATION OR DISASSEMBLY PROHIBITED" On the serial console shows the following: ---------------------------------------------------------------------------------------- CBFS: 'Master Header Locator' located CBFS at [610200:800000) CBFS: Locating 'pci8086,0116.rom' CBFS: Found @ offset 2d440 size 10000 In CBFS, ROM address for PCI: 00:02.0 = ffe3d688 Copying VGA ROM Image from ffe3d688 to 0xc0000, 0xf200 bytes Calling Option ROM... intel_vga_int15_handler: AX=5f34 BX=c000 CX=0002 DX=03da intel_vga_int15_handler: AX=5f52 BX=0000 CX=0002 DX=0008 Unknown INT15 function 5f52! int15 call returned error. intel_vga_int15_handler: AX=5f14 BX=078f CX=000a DX=fde8 Unknown INT15 function 5f14! int15 call returned error. intel_vga_int15_handler: AX=5f35 BX=c000 CX=0002 DX=03da intel_vga_int15_handler: AX=5f70 BX=c003 CX=0002 DX=0303 ... Option ROM returned. VBE: Getting information about VESA mode 4116 VBE: Function call failed! Error: In vbe_get_mode_info function -------------------------------------------------------------------------- Attached is the full serial debug dump. Any advise on what to do next? Any additional information do I need to provide? Thank you, any help will be very much appreciated. JT

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PCIe Hotplug for Thunderbolt and U.2
by Jeremy Soller 04 Dec '19

04 Dec '19

This is to continue the discussion from the coreboot leadership meeting. Thunderbolt devices are not correctly initialized by Coreboot such that the OS can boot without kernel parameters and allow for Thunderbolt hotplugging. Additional bus numbers and memory must be allocated. I will be working on support for this for our System76 mainboards. Here were the notes taken about it during the meeting, see 9 October 2019, PCIe Hotplug on newer Intel socs: https://docs.google.com/document/d/1NRXqXcLBp5pFkHiJbrLdv3Spqh1Hu086HYkKrgK… -- Jeremy Soller System76 Engineering Manager jeremy(a)system76.com

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AMD binaryPI board removals
by Kyösti Mälkki 04 Dec '19

04 Dec '19

Hi As of 27th November and commit [1] platforms using AMD binaryPI blobs have been disabled from automatic build testing. The following are affected: * amd/bettong * amd/db-ft3b-lc * amd/lamar * amd/olivehillplus * bap/ode_e21XX This is inline with CAR_GLOBAL_MIGRATION deprecation as mandated by 4.11 release requirements. You should expect that the board sources and platform support will disappear by 14th December, at latest, unless you show interest *and* are able to provide bootlogs for the boards above. PCEngines APU2 and variants are an exception to this, they were converted to POSTCAR_STAGE and work away from ROMCC_BOOTBLOCK shows promising results. [1] https://review.coreboot.org/c/coreboot/+/37170 Regards, Kyösti Mälkki

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Getting help to improve our documentation
by Patrick Georgi 04 Dec '19

04 Dec '19

Hi everybody, in today's leadership meeting we discussed whether we should hire technical writers to improve our documentation. While the situation already got a lot better since we moved to the Documentation/ directory instead of the wiki, it's still painfully obvious (at least to me) that we're a hacker oriented project with not so much focus (and/or skills) on documentation. Philipp and Arthur stepped up to collect ideas about the scope of such work, but we also decided to create an issue where ideas can be proposed. Therefore, if you've always thought that _this_ part of coreboot is woefully underdocumented (or that our documentation sucks because of _that_), please contribute to https://ticket.coreboot.org/issues/245. Patrick -- Google Germany GmbH, ABC-Str. 19, 20354 Hamburg Registergericht und -nummer: Hamburg, HRB 86891, Sitz der Gesellschaft: Hamburg Geschäftsführer: Paul Manicle, Halimah DeLaine Prado

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Community event in Germany
by Patrick Rudolph 04 Dec '19

04 Dec '19

Dear Open Source community, We will have an assembly at the 36C3 congress in Leipzig, Germany taking place from 27th Dec to 30th Dec in 2019. We will have 30 seats to hack on open source firmware. There will be workshops for beginners and tools for experts who want to flash their devices. Looking forward to seeing you there to chat about open source firmware or related projects, the Open Source Firmware Conference (OSFC) or how to flash firmware in general. You can find the assembly at "Chaos West" cluster. More information here: https://events.ccc.de/congress/2019/wiki/index.php/Main_Page https://signup.c3assemblies.de/assembly/ecc631c2-c723-448f-af16-313d3fc4f4e7 https://osfc.io Kind regards, Patrick Rudolph 9elements GmbH, Kortumstraße 19-21, 44787 Bochum, Germany Email: patrick.rudolph(a)9elements.com Phone: +49 234 / 68 94 188 Sitz der Gesellschaft: Bochum Handelsregister: Amtsgericht Bochum, HRB 13207 Geschäftsführung: Eray Basar, Sebastian Deutsch

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How to push to board_status repo?
by Jorge Fernandez Monteagudo 04 Dec '19

04 Dec '19

Hi all, I've generated a new entry in util/board_status/board-status/amd/bettong/4.10-6-g12ec481/2019-12-04T13_27_01Z/ but I'm not able to push the changes. I'm able to entry in to https://review.coreboot.org/settings/ and I can see my HTTP credentials with my github user name and I've generated a new password pushing the button but then I try to do a push and always get: $ cd util/board_status/board-status $ git push Username for 'https://review.coreboot.org': jorgefm1900 Password for 'https://jorgefm1900@review.coreboot.org': fatal: Authentication failed for 'https://review.coreboot.org/board-status.git/' Any resource to configure a review.coreboot.org repo user? I've tried to change the password through Github creating a personal access token without luck... Thanks!

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Re: Sandybridge-M help request in setting up LVDS panel.
by Jose Trujillo 04 Dec '19

04 Dec '19

I have no idea bro.... may be I am doing something wrong. This original FW of this embedded system is FULL OF BUGS... even the latest release. I can guess many of you don't have problems doing it this way. Maybe I have an early release of VBIOS which doesn't work with coreboot as expected. The libgfxinit solution given by our friend Nico today works. Later I will try another panel and variant of embedded system. Thank you, Jose Trujillo. > [Got it.] > > Does that mean coreboot+tianocore where it has to install GOP protocol and can’t really working with VBIOS/OpRom? > > Thanks, > > Subrata > > From: Jose Trujillo [mailto:ce.autom@protonmail.com] > Sent: Wednesday, December 4, 2019 5:27 PM > To: Banik, Subrata <subrata.banik(a)intel.com> > Subject: RE: [coreboot] Sandybridge-M help request in setting up LVDS panel. > > Dear Subrata: > > I got the pdf. > > I already tested all modes and even video mode 105 is showing only vertical lines. > > 101 = 640x480 256 colors = vertical lines. > > 103 = 800x600 256 colors = vertical lines. > > 105 = 1024x768 256 colors = vertical lines. > > 111 = 640x480 64k colors = vertical lines. > > 112 = 640x480 16M colors = vertical lines. > > 114 = 800x600 64k colors = vertical lines. > > 115 = 800x600 16M colors = vertical lines. > > 117 = 1024x768 64k colors = vertical lines. > > 118 = 1024x768 16M colors = vertical lines. > > But in some modes when the system boots to linux it does with good video on the panel. > > Just never good video on coreboot-tianocore. > > Jose. > >> >> >> FYI >> >> https://pdos.csail.mit.edu/6.828/2018/readings/hardware/vbe3.pdf >> >> Thanks, >> >> Subrata >> >> -----Original Message----- >> From: Banik, Subrata >> Sent: Wednesday, December 4, 2019 2:13 PM >> To: 'Jose Trujillo' <ce.autom(a)protonmail.com> >> Subject: RE: [coreboot] Sandybridge-M help request in setting up LVDS panel. >> >> HI Jose, >> >> I believe first you should try one off below mode to see if your display is working proper. >> >> Supported Video Mode list for OpRom: >> >> 105 >> >> 117 >> >> 118 >> >> 112 >> >> 114 >> >> 115 >> >> 101 >> >> 103 >> >> 111 >> >> I guess if you download VESA spec you might know about all those mode more and know what is supported X, Y and bit width. >> >> Thanks, >> >> Subrata >> >> -----Original Message----- >> >> From: Jose Trujillo [mailto:ce.autom@protonmail.com] >> >> Sent: Wednesday, December 4, 2019 2:10 PM >> >> To: Banik, Subrata <subrata.banik(a)intel.com> >> >> Subject: RE: [coreboot] Sandybridge-M help request in setting up LVDS panel. >> >> Good morning Subrata: >> >> You were right! >> >> #116 doesn't appear on the list. >> >> Then how the original FW support it? >> >> I am even working (building and flashing) on this panel. >> >> Also remember even at video mode #118 the system halts with vertical lines. >> >> Any workaround for this? >> >> This panel is 1024x768@18bit and I will test another one 1024x768@24bit to see... >> >> CBFS: Locating 'pci8086,0116.rom' >> >> CBFS: Found @ offset 2d440 size 10000 >> >> In CBFS, ROM address for PCI: 00:02.0 = ffe3d688 Copying VGA ROM Image from ffe3d688 to 0xc0000, 0xf200 bytes Calling Option ROM... >> >> intel_vga_int15_handler: AX=5f34 BX=c000 CX=0002 DX=03da >> >> intel_vga_int15_handler: AX=5f52 BX=0000 CX=0002 DX=0008 Unknown INT15 function 5f52! >> >> int15 call returned error. >> >> intel_vga_int15_handler: AX=5f14 BX=078f CX=000a DX=fde8 Unknown INT15 function 5f14! >> >> int15 call returned error. >> >> intel_vga_int15_handler: AX=5f35 BX=c000 CX=0002 DX=03da >> >> intel_vga_int15_handler: AX=5f70 BX=c003 CX=0002 DX=0303 ... Option ROM returned. >> >> Supported Video Mode list for OpRom: >> >> 105 >> >> 117 >> >> 118 >> >> 112 >> >> 114 >> >> 115 >> >> 101 >> >> 103 >> >> 111 >> >> VBE: Getting information about VESA mode 4116 >> >> VBE: Function call failed! >> >> Error: In vbe_get_mode_info function >> >> Thank you, >> >> Jose Trujillo. >> >>> Hi Jose, >> >>> >> >>> Can you please try below code changes ? >> >>> >> >>> diff --git a/src/device/oprom/realmode/x86.c >> >>> b/src/device/oprom/realmode/x86.c index 0a5ede3..12c70cb 100644 >> >>> --- a/src/device/oprom/realmode/x86.c >> >>> +++ b/src/device/oprom/realmode/x86.c >> >>> @@ -437,6 +437,7 @@ void run_bios(struct device *dev, unsigned long >> >>> addr) realmode_call(addr + 0x0003, num_dev, 0xffff, 0x0000, 0xffff, >> >>> 0x0, 0x0); printk(BIOS_DEBUG, "... Option ROM returned.\n"); >> >>> >> >>> - vbe_oprom_supported_mode_list(); >> >>> >> >>> >> >>> >> >>> #if CONFIG(FRAMEBUFFER_SET_VESA_MODE) >> >>> if ((dev->class >> 8)== PCI_CLASS_DISPLAY_VGA) >> >>> >> >>> vbe_set_graphics(); >> >>> >> >>> >> >>> Thanks, >> >>> Subrata >> >>>

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coreboot December 2019