coreboot March 2018

coreboot@coreboot.org

62 participants
103 discussions

by Nico Huber

On 29.03.2018 20:25, ron minnich wrote: > I have the following code: > > movl $0x12345678, %eax > movl $0xaaaabbbb, %ebx > movb $0x10, %cl > shrdw %ebx, %eax If I had to assemble it, I would have refuse it... *w with 32-bit registers? how should that work? Though, after reading a little about AT&T, I found this: "In AT&T syntax, the size of memory operands is determined from the last character of the opcode name." [1] Memory operands, heh, no memory operands here... but the GNU as manual talks about operands in general and that it may infer the suffix from register operands, hmmm, no word about what happens if register operands don't match the suffix. I've also tried to find a quote about the third operand. Is it %cl implicitly? I would think so, but is it written anywhere? Could also be implicitly $0, ok that would never make sense. > quiz: what's the value of %ax after this instruction? I guess it depends on the assembler you use. non-zero? TIL, you can't shift by 32 bits this way. Nico [1] https://web.archive.org/web/20131003180256/http://www.ibm.com/developerwork…

2 years, 11 months

Re: [coreboot] shrdw question

by Andriy Gapon

On 29/03/2018 21:25, ron minnich wrote: > I have the following code: > > movl $0x12345678, %eax > movl $0xaaaabbbb, %ebx > movb $0x10, %cl > shrdw %ebx, %eax > > quiz: what's the value of %ax after this instruction? Given 'w', correct notation for the last instruction should be shrdw %bx, %ax ? I believe that the original value of %ax would be shifted out and replaced with the value of %bx. So, 0xbbbb. Same as %bx. -- Andriy Gapon

2 years, 11 months

shrdw question

by ron minnich

I have the following code: movl $0x12345678, %eax movl $0xaaaabbbb, %ebx movb $0x10, %cl shrdw %ebx, %eax quiz: what's the value of %ax after this instruction?

2 years, 11 months

Re: [coreboot] Missing ACPI ASL code for Denverton GPIO controller

by Julien Viard de Galbert

Hi Sumo, It was more to get some motivation to clean some of the code. The branch is here: https://review.coreboot.org/c/coreboot/+/25446 <https://review.coreboot.org/c/coreboot/+/25446> I’ve really not looked on GPIO on ACPI (cause I don’t need it) but I really think it should be a better base for your work. So if you can test in on your board, please report your results and help reviewing the code ;-) Best Regards, Julien > Le 28 mars 2018 à 14:10, Sumo <kingsumos(a)gmail.com> a écrit : > > Hi Julien, > > Yes, I'm interested. But no need to hurry up, do it in your own time. ;) > > Thanks, > Sumo > > 2018-03-27 6:54 GMT-03:00 Julien Viard de Galbert <jviarddegalbert(a)online.net <mailto:jviarddegalbert@online.net>>: > > >> Le 26 mars 2018 à 21:24, Sumo <kingsumos(a)gmail.com <mailto:kingsumos@gmail.com>> a écrit : >> >> Hi all, > > Hi Sumo, > >> >> We have a kernel patch which adds pinctrl/GPIO support for Intel Denverton SoC (https://patchwork.kernel.org/patch/9879473/ <https://patchwork.kernel.org/patch/9879473/>) to make possible to access the GPIO from user space (via sysfs, i.e. /sys/kernel/debug/pinctrl/), however this patch is expects a "INTC3000" GPIO controller definition in the ACPI tables. >> I want to add/implement the INTC3000 in the ASL code, but since I don´t want to reinvent the wheel I´m asking if such ASL code is already available somewhere (at least in the Intel Pine Lake CRB there´s no such reference to INTC3000 in the ACPI tables). >> > > I have a set of patches that still need some work (https://review.coreboot.org/c/coreboot/+/24928 <https://review.coreboot.org/c/coreboot/+/24928>) that enable some shared code for GPIO; following I also have more patches to use the ACPI code from common block too (not published yet). I didn’t check but probably apollolake or cannonlake has the ACPI code for GPIO (using common block). > If you are interested I can probably work on adding the ACPI implementation to Gerrit sooner. > > Best Regards, > > Julien > >> Thanks, >> Sumo >> -- >> coreboot mailing list: coreboot(a)coreboot.org <mailto:coreboot@coreboot.org> >> https://mail.coreboot.org/mailman/listinfo/coreboot <https://mail.coreboot.org/mailman/listinfo/coreboot> > -- > Julien Viard de Galbert - jviarddegalbert(a)online.net <mailto:jviarddegalbert@online.net> > Online / Scaleway > Looking for an amazing job? Join us NOW ! https://careers.scaleway.com/ <https://careers.scaleway.com/> > > > > > > -- > coreboot mailing list: coreboot(a)coreboot.org > https://mail.coreboot.org/mailman/listinfo/coreboot -- Julien Viard de Galbert - jviarddegalbert(a)online.net Online / Scaleway Looking for an amazing job? Join us NOW ! https://careers.scaleway.com/

2 years, 11 months

SATA init on FSP 2.0 for Skylake

by roman perepelitsin

Hi! I got a little problem with SATA controller in H110 Skylake PCH (desktop). SATA device geographical address - 0:17h:0 on PCI, and it enabled via devicetree.cb. This params correctly send in FspSiliconInit. After this coreboot run PCI bus scan. And my SATA device return 0xffffffff on PCI read config cycles. I search in Intel datasheet for specific SATA disable pin or something else, but there is no methods that can make SATA inactive. Maybe somebody advice about it? -- regards, Perepelitsin Roman

2 years, 11 months

Re: [coreboot] Missing ACPI ASL code for Denverton GPIO controller

by Julien Viard de Galbert

> Le 26 mars 2018 à 21:24, Sumo <kingsumos(a)gmail.com> a écrit : > > Hi all, Hi Sumo, > > We have a kernel patch which adds pinctrl/GPIO support for Intel Denverton SoC (https://patchwork.kernel.org/patch/9879473/ <https://patchwork.kernel.org/patch/9879473/>) to make possible to access the GPIO from user space (via sysfs, i.e. /sys/kernel/debug/pinctrl/), however this patch is expects a "INTC3000" GPIO controller definition in the ACPI tables. > I want to add/implement the INTC3000 in the ASL code, but since I don´t want to reinvent the wheel I´m asking if such ASL code is already available somewhere (at least in the Intel Pine Lake CRB there´s no such reference to INTC3000 in the ACPI tables). > I have a set of patches that still need some work (https://review.coreboot.org/c/coreboot/+/24928) that enable some shared code for GPIO; following I also have more patches to use the ACPI code from common block too (not published yet). I didn’t check but probably apollolake or cannonlake has the ACPI code for GPIO (using common block). If you are interested I can probably work on adding the ACPI implementation to Gerrit sooner. Best Regards, Julien > Thanks, > Sumo > -- > coreboot mailing list: coreboot(a)coreboot.org > https://mail.coreboot.org/mailman/listinfo/coreboot -- Julien Viard de Galbert - jviarddegalbert(a)online.net Online / Scaleway Looking for an amazing job? Join us NOW ! https://careers.scaleway.com/

2 years, 11 months

Re: [coreboot] Coreboot build unstable?

by Julius Werner

[repost to list with the right sender address] > I just had the following CL fail in Jenkins: > https://review.coreboot.org/c/coreboot/+/25393 > > It fails for GOOGLE_CHELL but the one file it touches doesn't even get > compiled for that board. I'm not quite sure that to make of the error but > it seems to be a problem with building the Chrome EC code in 3rdparty. (I > guess we don't log the full build output for subinvocations of make in > Jenkins?) > > I've rebased the CL so let's hope it works on the next attempt... but in > the meantime, can anybody figure out what's wrong here and how we can fix > it? (Maybe a flaky build failure related to parallel builds?) >

2 years, 11 months

Missing ACPI ASL code for Denverton GPIO controller

by Sumo

Hi all, We have a kernel patch which adds pinctrl/GPIO support for Intel Denverton SoC (https://patchwork.kernel.org/patch/9879473/) to make possible to access the GPIO from user space (via sysfs, i.e. /sys/kernel/debug/pinctrl/), however this patch is expects a "INTC3000" GPIO controller definition in the ACPI tables. I want to add/implement the INTC3000 in the ASL code, but since I don´t want to reinvent the wheel I´m asking if such ASL code is already available somewhere (at least in the Intel Pine Lake CRB there´s no such reference to INTC3000 in the ACPI tables). Thanks, Sumo

2 years, 11 months

Re: [coreboot] Server systems shipped with coreboot

by Taiidan＠gmx.com

Please also keep in mind that it is impossible to disable ME. *I am not a lawyer* In america the first sale law means you are allowed to do as you please with a device you purchased as long as you are not violating any EULA but if you somehow did the impossible and figured out how to execute code on the ME core you would be breaking the law as it is also a DRM mechanism (PAVP, HDCP, intel insider etc) which is illegal to bypass.

2 years, 11 months

Re: [coreboot] Server systems shipped with coreboot

by Piotr Kubaj

There's no "pure coreboot" systems. You need some payload. Also, while Talos is truly awesome, the OP asked about coreboot specifically and Talos doesn't run coreboot :) At the moment, the best coreboot-supported server motherboard is ASUS KGPE-D16. You can also get libre BMC with OpenBMC port for it. If you just want a libre motherboard, Talos is the best you can get. On 18-01-17 12:00:01, coreboot-request(a)coreboot.org wrote: >Message: 2 >Date: Tue, 16 Jan 2018 19:29:18 +0100 >From: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> >To: Coreboot <coreboot(a)coreboot.org> >Subject: [coreboot] Server systems shipped with coreboot >Message-ID: <d5d6d8ee-77ee-4232-a89a-e5158140b065(a)gmx.net> >Content-Type: text/plain; charset=UTF-8 > >Hi, > >does anyone have a list of server systems which are shipped with >coreboot? I'm interested in coreboot+UEFI systems, coreboot+Linux >systems, coreboot+SeaBIOS systems, pure coreboot systems. > >At 34C3 I was told by someone that a major vendor has been shipping >servers with coreboot without announcing this, and I unfortunately >neither remember the server model nor who told me about this. If said >person could remind contact me, I'd be thankful. > >Regards, >Carl-Daniel > > > >------------------------------ > >Message: 3 >Date: Wed, 17 Jan 2018 00:28:23 +0300 >From: Mike Banon <mikebdp2(a)gmail.com> >To: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net>, > coreboot(a)coreboot.org >Subject: Re: [coreboot] Server systems shipped with coreboot >Message-ID: > <CAK7947nVZptQEhiRzfPQpt_KqVFERXzFNrppeb_NTVhEGxSLQQ(a)mail.gmail.com> >Content-Type: text/plain; charset="UTF-8" > >Hi friend ! I just googled "coreboot servers" and found this: > >https://store.vikings.net/the-server-1u , and >https://www.siliconmechanics.com/i7045/opteron-server.php >(Installation of coreboot is available with certain configurations; >contact Sales for details.) > >And, of course, Talos II POWER9 servers which are already available >for pre-orders. >They are the future of libre server computing : >https://www.raptorcs.com/TALOSII/prerelease.php > >So basically there are two options: >1) use one of a few coreboot-supported boards with AMD Opterons (which >are also a bit outdated) >you can even build such a server by yourself, just get the supported >hardware and flash coreboot to it >2) preorder Talos II and wait for shiny new server to come ;) > >Mike > > >On Tue, Jan 16, 2018 at 9:29 PM, Carl-Daniel Hailfinger ><c-d.hailfinger.devel.2006(a)gmx.net> wrote: >> Hi, >> >> does anyone have a list of server systems which are shipped with >> coreboot? I'm interested in coreboot+UEFI systems, coreboot+Linux >> systems, coreboot+SeaBIOS systems, pure coreboot systems. >> >> At 34C3 I was told by someone that a major vendor has been shipping >> servers with coreboot without announcing this, and I unfortunately >> neither remember the server model nor who told me about this. If said >> person could remind contact me, I'd be thankful. >> >> Regards, >> Carl-Daniel >> >> -- >> coreboot mailing list: coreboot(a)coreboot.org >> https://mail.coreboot.org/mailman/listinfo/coreboot > > > >------------------------------ > >Subject: Digest Footer > >_______________________________________________ >coreboot mailing list >coreboot(a)coreboot.org >https://mail.coreboot.org/mailman/listinfo/coreboot > >------------------------------ > >End of coreboot Digest, Vol 155, Issue 24 >***************************************** > >-- >This message has been scanned for viruses and >dangerous content by MailScanner, and is >believed to be clean. >

2 years, 11 months

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coreboot March 2018