coreboot August 2017

coreboot@coreboot.org

59 participants
132 discussions

Re: [coreboot] Why I don't like links in commit messages and comments ...
by Felipe Sanches 15 Aug '17

15 Aug '17

There's a rather simple solution to that: stipulate that any link in commit messages must be first saved on the Internet Archive's Wayback Machine. That is as easy as pasting the original URL into a text field in this page and clicking the "Save Page Now" button: https://archive.org/web/ 2017-08-14 21:44 GMT-03:00 ron minnich <rminnich(a)gmail.com>: > This is an interesting headline: > > "I Bought a Book About the Internet From 1994 and None of the Links Worked" > > What's interesting? That's only 5 years before linuxbios started. I can > make the totally unwarranted claim that the half life of a link is around > 12 years. I justify this claim with one bogus data point, namely, this > headline :-) > > But still, what's amazing is when I did a check, about 15 years after > linuxbios began, about 25% of the links were in fact dead. So the 12 year > number may not be great, but ... maybe it's not that bad either. > > And now you know why I don't like links in commit messages :-) > > ron > > -- > coreboot mailing list: coreboot(a)coreboot.org > https://mail.coreboot.org/mailman/listinfo/coreboot >

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Why I don't like links in commit messages and comments ...
by ron minnich 15 Aug '17

15 Aug '17

This is an interesting headline: "I Bought a Book About the Internet From 1994 and None of the Links Worked" What's interesting? That's only 5 years before linuxbios started. I can make the totally unwarranted claim that the half life of a link is around 12 years. I justify this claim with one bogus data point, namely, this headline :-) But still, what's amazing is when I did a check, about 15 years after linuxbios began, about 25% of the links were in fact dead. So the 12 year number may not be great, but ... maybe it's not that bad either. And now you know why I don't like links in commit messages :-) ron

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Some updated instructions to flash coreboot to the Thinkpad X60 from vendor bios
by Arthur Heymans 14 Aug '17

14 Aug '17

Hi With some new code and methods the process of flashing a thinkpad x60 from vendor bios (and to some extend a thinkpad t60) can be eased a bit and wrote down a hopefully useful guide: Here is the link: https://gist.github.com/ArthurHeymans/c5ef494ada01af372735f237f6c6adbe Feedback is of course very welcome. (I'll try to put on the wiki some time later) Kind regards Arthur

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ASUS KGPE-D16 Automated Test Failure [master]
by Raptor Engineering Automated Coreboot Test Stand 14 Aug '17

14 Aug '17

The ASUS KGPE-D16 fails verification for branch master as of commit 4b7b18d14ac99d2337796facd3028647799b4f66 The following tests failed: BOOT_FAILURE Commits since last successful test: 4b7b18d console: Add weak method to notify about death c3cbe94 nb/intel/x4x/gma.c: Probe VGA EDID on DVI-I ports ccdef19 driver/intel/gma: Allow use of GFX_GMA_ANALOG_I2C_HDMI_x in C NGI 0f6187a ec/google: update ec_commands.h b4411d3 mb/google/poppy: Update PL2 settings <5 commits skipped> b58366a soc/intel/cannonlake: Add missing _PCH_DEV definitions 285f9f2 payloads/external/tianocore: Add and apply patches for tianocore 6c9c196 copy & update test routines from what-jenkins-does e624e27 Make: Move testing into a subdirectory fea9216 Documentation: Add binary extraction documentation See attached log for details This message was automatically generated from Raptor Engineering's ASUS KGPE-D16 test stand Want to test on your own equipment? Check out https://www.raptorengineering.com/content/REACTS/intro.html Raptor Engineering also offers coreboot consulting services! Please visit https://www.raptorengineering.com for more information Please contact Timothy Pearson at Raptor Engineering <tpearson(a)raptorengineering.com> regarding any issues stemming from this notification

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Need help implementing romstage CBMEM
by Keith Hui 13 Aug '17

13 Aug '17

Hi all, After reading the code for more recent Intel northbridges I think I have an idea on what needs to be added, so here is my attempt to bring 440BX to coreboot 4.7 standards: https://review.coreboot.org/20977 The problem is it could not boot. The console log is attached. In short, I think I have the top of RAM value correct, but it could not find a place for the payload to load and the boot process is stuck. What am I missing? By the way, I think an unintended update for my two earlier patches were also pushed along with this change. How to I get them sorted out? [1] [2] Thanks Keith [1] https://review.coreboot.org/c/20868/ [2] https://review.coreboot.org/c/20952/

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Trying out tianocore payload build from the coreboot build system: Succes!
by arthur＠aheymans.xyz 12 Aug '17

12 Aug '17

Hi I tried out tianocore build from the coreboot build system which was very recently merged. [1] [2] I tested it on my thinkpad X200 with native graphic init enabled (tianocore CorebootPayloadPkg can reuse the framebuffer set up by coreboot). Upon booting I'm greeted with a small line somewhere around the left upper side of the sceen which quickly becomes a timeout screen (small tianocore logo in the middle and at the bottom a bar that get's filled up as time increases, there is also a mention that my 6G of memory tested fine). After the timeout expired it loaded my EFI bootloader (grub2) on my EFI partition and booted my OS. Pressing the ESC key before the timeout puts you in a rather limited configuration menu that allows you to select the bootdevice (USB by default iirc) amongsth other things. Some issues: * it thrashes coreboot tables which is fixed in [3] * it does not store the setting in it's menu since it has no way of persistently storing things. Anyway, kudos to those having worked on this! ---- [1] https://review.coreboot.org/#/c/15057/ "payloads/external/tianocore: build UEFI payload" [2] https://review.coreboot.org/#/c/20639/ "payloads/external/tianocore: Add and apply patches for tianocore" [3] https://review.coreboot.org/#/c/20968/ "payload/tianocore: Add patch to preserve coreboot table" ---- Arthur Heymans

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ASUS KGPE-D16 Automated Test Failure [master]
by Raptor Engineering Automated Coreboot Test Stand 12 Aug '17

12 Aug '17

The ASUS KGPE-D16 fails verification for branch master as of commit c3cbe9433c22b5ac3bd616c858fb87b0de3ebab8 The following tests failed: BOOT_FAILURE Commits since last successful test: c3cbe94 nb/intel/x4x/gma.c: Probe VGA EDID on DVI-I ports ccdef19 driver/intel/gma: Allow use of GFX_GMA_ANALOG_I2C_HDMI_x in C NGI 0f6187a ec/google: update ec_commands.h b4411d3 mb/google/poppy: Update PL2 settings 6dc3492 util/cbmem, util/cbfstool: resolve macro errors on FreeBSD <4 commits skipped> b58366a soc/intel/cannonlake: Add missing _PCH_DEV definitions 285f9f2 payloads/external/tianocore: Add and apply patches for tianocore 6c9c196 copy & update test routines from what-jenkins-does e624e27 Make: Move testing into a subdirectory fea9216 Documentation: Add binary extraction documentation See attached log for details This message was automatically generated from Raptor Engineering's ASUS KGPE-D16 test stand Want to test on your own equipment? Check out https://www.raptorengineering.com/content/REACTS/intro.html Raptor Engineering also offers coreboot consulting services! Please visit https://www.raptorengineering.com for more information Please contact Timothy Pearson at Raptor Engineering <tpearson(a)raptorengineering.com> regarding any issues stemming from this notification

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Abandoning patches older than 18 months
by Martin Roth 11 Aug '17

11 Aug '17

It's patch cleanup time again. Next week I'm going to abandon all of the open patches that haven't been touched in over 18 months. The list of 35 patches to be abandoned is here: https://review.coreboot.org/#/q/status:open+before:2016-02-15 As always, if there's anything that is still useful and shouldn't be abandoned, a comment in the patch is enough to keep it alive in gerrit. Martin

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seeking help with installing libreboot. any libreboot install event in Berlin?
by njolk 11 Aug '17

11 Aug '17

sorry for having overlooked the wrong/missing title!..here's my post again; Hello! I'd like to ask if there will be any libreboot install event soon in Berlin (or any in the planning). I'm looking for help to install libreboot on my computer. thank you all!

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Re: [coreboot] How to improve the boot time of the Asus KGPE-D16?
by Daniel Kulesz 11 Aug '17

11 Aug '17

Hi, I wanted to try caching of the MRC training data. As described in Timothy's post, I commented the following line: > allow_config_restore = 0; However, I was not able to measure any effects regarding boot time. Does this setting only work with cbfs enabled? And if so, is it necessary to set additionally any cbfs variables? Cheers, Daniel P.S. Hope this time I've set the Reply-To header correctly. > On 03/02/2017 02:17 PM, Paul Menzel wrote: > > Dear Arthur, dear Timothy, > > > > > > Am Donnerstag, den 02.03.2017, 13:38 -0600 schrieb Timothy Pearson: > >> On 03/02/2017 01:30 PM, Arthur Heymans wrote: > >>> Paul Menzel writes: > >>> > >>>> I think most of the time is spent in RAM initialization. > >>>> > >>>> 1. Do board owners with similar amount of memory (independent of the > >>>> board) have similar numbers? > >>>> 2. What are the ways to improve that? Is it possible? For example, can > >>>> the modules be probed in parallel (if that isn?t done already)? > >>>> > >>> > >>> I'm not the right person to answer this since I don't know this > >>> code/hardware that well, but on modern Intel hardware native code uses > >>> the MRC cache to store dram training results and restore those on > >>> next boots (and resume from suspend) if no change in dimm configuration > >>> was detected. > >>> > >>> Maybe something like this could also be applied here (or maybe it's already > >>> the case since it includes code to access spi flash)? > >> > >> Yes, this is already implemented as an option, and it does a fairly > >> decent job of reducing training overhead to almost nothing, > > > > Interesting. What option is that? > > > > Also, besides the file `s3nv` I don?t see anything else in CBFS. Where > > is the training data cached? > > That's it. The cache is mandatory for S3 resume, and optional at boot. > > That being said, the pathways are present but are deactivated due to > historical instability and are not tied in to an nvram variable at this > time. If you want to test, you'll need to edit the source file > "src/northbridge/amd/amdmct/mct_ddr3/mct_d.c"; near line 2730 you'll see > a FIXME comment and this line: > > allow_config_restore = 0; > > Comment that line out and recompile to test. I strongly suggest running > memtest across multiple warm and cold boots (and reboots) before > determining the functionality is stable enough for use.

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coreboot August 2017