August 2017 - coreboot - mail.coreboot.org

[Broadwell-U]How the eDP, DDI1, DDI2 are enabled?
by Zheng Bao Aug. 2, 2017

Aug. 2, 2017

--------------------------------- # Enable eDP Hotplug with 6ms pulse register "gpu_dp_d_hotplug" = "0x06" # Enable DDI1 Hotplug with 6ms pulse register "gpu_dp_b_hotplug" = "0x06" # Enable DDI2 Hotplug with 6ms pulse register "gpu_dp_c_hotplug" = "0x06" # Set backlight PWM values for eDP register "gpu_cpu_backlight" = "0x00000200" register "gpu_pch_backlight" = "0x04000200" # Enable Panel and configure power delays register "gpu_panel_port_select" = "1" # eDP register "gpu_panel_power_cycle_delay" = "6" # 500ms register "gpu_panel_power_up_delay" = "2000" # 200ms register "gpu_panel_power_down_delay" = "500" # 50ms register "gpu_panel_power_backlight_on_delay" = "2000" # 200ms register "gpu_panel_power_backlight_off_delay" = "2000" # 200ms --------------------------------------- I assume SOC has 3 display port, called eDP, DDI1 and DDI2. The code above enable eDP only. How are the DDI1 and DDI2 enabled? Zheng

1 0

Re: [coreboot] Fwd: [FWD: Request for Chromebook Authentication Module Development]
by David Hendricks Aug. 2, 2017

Aug. 2, 2017

On Tue, Aug 1, 2017 at 10:54 PM, David Hendricks <david.hendricks(a)gmail.com> wrote: > Hi Victor, > IMO this is really more of a feature for the Out Of Box Experience (OOBE) > rather than coreboot or seabios. > Just to clarify, OOBE refers to a specific set of routines - I believe within the login manager - that are executed when the user starts the computer for the first time and guides them thru things such as language selection, wifi setup, etc.

1 0

Re: [coreboot] Fwd: [FWD: Request for Chromebook Authentication Module Development]
by David Hendricks Aug. 2, 2017

Aug. 2, 2017

Hi Victor, IMO this is really more of a feature for the Out Of Box Experience (OOBE) rather than coreboot or seabios. If your organization uses the ChromeOS Management Console then you should already be able to assign specific assets to users ( https://www.google.com/intl/en/chrome/business/devices/features-management-… ). Regardless, if you want to add a PIN or code for first-time login, I would suggest adding it via the login screen. Something like: 1. Program the PIN/code into the Read-Only Vital Product Data (RO_VPD), which is a read-only region in the firmware ROM. 2. Modify the login manager to check if the machine is booting for the first time since it was last installed. 3. If so, the login manager can read the code from the RO_VPD (using the `vpd` tool in ChromeOS) and prompt the user to enter it. Once the user enters the code, the check is disabled (until the OS is re-installed or power washed). Supporting firmware changes will be a very large task since there are long-term support implications. It will be much easier for you to support a change to the login screen I think. The chromium-os-discuss mailing list might also be a good resource to find people who can help with this sort of thing: https://groups.google.com/a/chromium.org/forum/#!forum/chromium-os-discuss Good luck! On Tue, Aug 1, 2017 at 8:31 AM, ron minnich <rminnich(a)gmail.com> wrote: > This doesn't make sense to me. By putting the PIN in memory you expose its > value at all steps in the delivery process. Chromebooks have a very good > mechanism for keys that can be personalized to an individual, see my talk > at last year's linuxconf in berlin where I showed how you can make a > chromebook boot only a chromeos you have signed personally. > > Security is really hard to get right. I think you need to build on what's > in the chromebook, not design your own addon, because that's almost > certainly going to weaken security. > > What are you trying to do here? Is the target software stack chromeos? Why > the PIN? > > We may want to drop coreboot list off this discussion but there are so > many smart people on the coreboot list I wanted to give them a chance to > respond too. > > -- > coreboot mailing list: coreboot(a)coreboot.org > https://mail.coreboot.org/mailman/listinfo/coreboot >

1 0

Re: [coreboot] Broadwell-U hangs at VGA init (update)
by Zheng Bao Aug. 2, 2017

Aug. 2, 2017

src/soc/intel/broadwell/lpc.c /* Initialize power management */ // pch_power_options(dev); // pch_pm_init(dev); printk(BIOS_INFO, "%s,%d.\n", __func__, __LINE__); // pch_cg_init(dev); printk(BIOS_INFO, "%s,%d.\n", __func__, __LINE__); // pch_set_acpi_mode(); I need to skip all these 4 functions to run through, otherwise it hangs. What causes this? or what setting is not right? Zheng ________________________________ From: coreboot <coreboot-bounces(a)coreboot.org> on behalf of Zheng Bao <fishbaoz(a)hotmail.com> Sent: Tuesday, August 1, 2017 1:51 PM To: Matt DeVillier Cc: Nico Huber; stefan.reinauer(a)coreboot.org; coreboot(a)coreboot.org Subject: Re: [coreboot] Broadwell-U hangs at VGA init (update) Refcode is added and VGA BIOS passes. hangs at "Set power off after power failure. " It seems that the ME is not 100% right. Zheng coreboot-4.6-891-gca74434-dirty Fri Jul 28 06:45:02 UTC 2017 romstage starting... PM1_STS: 0000 PM1_EN: 0000 PM1_CNT: 00000000 TCO_STS: 0000 0000 GPE0_STS: 08fe08fc 10000f35 6005e200 00000000 GPE0_EN: 00000000 00000000 00000000 00000000 GEN_PMCON: 0200 2024 4206 Previous Sleep State: S5 CPU: Intel(R) Core(TM) i7-5650U CPU @ 2.20GHz CPU: ID 306d4, Broadwell E0 or F0, ucode: 0000001f CPU: AES supported, TXT supported, VT supported MCH: device id 1604 (rev 09) is Broadwell F0 PCH: device id 9cc3 (rev 03) is Broadwell U Premium IGD: device id 1626 (rev 09) is Broadwell U GT3 (15W) CPU: frequency set to 2200 MHz SPD: index 0 (GPIO65=0 GPIO67=0 GPIO68=0 GPIO69=0) CBFS: 'Master Header Locator' located CBFS at [300100:3fffc0) CBFS: Locating 'spd.bin' CBFS: Found @ offset 6b080 size 1000 SPD: module type is DDR3 SPD: module part is 99U5469-011.A01LF SPD: banks 8, ranks 1, rows 16, columns 10, density 8192 Mb SPD: device width 16 bits, bus width 64 bits SPD: module size is 4096 MB (per channel) ME: FW Partition Table : OK ME: Bringup Loader Failure : NO ME: Firmware Init Complete : NO ME: Manufacturing Mode : YES ME: Boot Options Present : NO ME: Update In Progress : NO ME: Current Working State : Initializing ME: Current Operation State : Bring up ME: Current Operation Mode : Security Override via Jumper ME: Error Code : Debug Failure ME: Progress Phase : BUP Phase ME: Power Management Event : Pseudo-global reset ME: Progress Phase State : 0x7b ERROR: ME failed to respond FMAP: Found "FLASH" version 1.1 at 300000. FMAP: base = ffc00000 size = 400000 #areas = 3 MRC: no data in 'RW_MRC_CACHE' No MRC cache found. CBFS: 'Master Header Locator' located CBFS at [300100:3fffc0) CBFS: Locating 'mrc.bin' CBFS: Found @ offset 9fec0 size 36998 Starting Memory Reference Code Initializing Policy Installing common PPI MRC: Starting... Initializing Memory MRC: Done. MRC Version 2.6.0 Build 0 memcfg DDR3 clock 1600 MHz memcfg channel assignment: A: 0, B 1, C 2 memcfg channel[0] config (00780010): enhanced interleave mode on rank interleave on DIMMA 4096 MB width x16 single rank, selected DIMMB 0 MB width x16 single rank memcfg channel[1] config (00780010): enhanced interleave mode on rank interleave on DIMMA 4096 MB width x16 single rank, selected DIMMB 0 MB width x16 single rank CBMEM: IMD: root @ 7cfff000 254 entries. IMD: root @ 7cffec00 62 entries. External stage cache: IMD: root @ 7d3ff000 254 entries. IMD: root @ 7d3fec00 62 entries. MRC data at ff7d0d9c 6246 bytes create cbmem for dimm information MLB: board version Unknown CBFS: 'Master Header Locator' located CBFS at [300100:3fffc0) CBFS: Locating 'fallback/ramstage' CBFS: Found @ offset 1c400 size 144b9 Decompressing stage fallback/ramstage @ 0x7cf97fc0 (257104 bytes) Loading module at 7cf98000 with entry 7cf98000. filesize: 0x2c380 memsize: 0x3ec10 Processing 2817 relocs. Offset value of 0x7ce98000 coreboot-4.6-891-gca74434-dirty Fri Jul 28 06:45:02 UTC 2017 ramstage starting... Normal boot. BS: BS_PRE_DEVICE times (us): entry 5 run 7 exit 5 CBFS: 'Master Header Locator' located CBFS at [300100:3fffc0) CBFS: Locating 'fallback/refcode' CBFS: Found @ offset 30900 size 1274b Decompressing stage fallback/refcode @ 0x7cf62fc0 (201528 bytes) Loading module at 7cf63000 with entry 7cf63000. filesize: 0x29b38 memsize: 0x312f8 Processing 1695 relocs. Offset value of 0x7cf63000 Initializing Policy Installing common PPI PEI: Starting... Initializing System Agent Initializing PCH PEI: Done. BS: BS_DEV_INIT_CHIPS times (us): entry 5 run 94299 exit 5 Enumerating buses... Show all devs... Before device enumeration. Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 DOMAIN: 0000: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:02.0: enabled 1 PCI: 00:03.0: enabled 1 PCI: 00:13.0: enabled 1 PCI: 00:14.0: enabled 1 PCI: 00:15.0: enabled 1 PCI: 00:15.1: enabled 1 PCI: 00:15.2: enabled 1 PCI: 00:15.3: enabled 1 PCI: 00:15.4: enabled 0 PCI: 00:15.5: enabled 0 PCI: 00:15.6: enabled 0 PCI: 00:16.0: enabled 1 PCI: 00:16.1: enabled 0 PCI: 00:16.2: enabled 0 PCI: 00:16.3: enabled 0 PCI: 00:17.0: enabled 0 PCI: 00:19.0: enabled 0 PCI: 00:1b.0: enabled 0 PCI: 00:1c.0: enabled 0 PCI: 00:1c.1: enabled 0 PCI: 00:1c.2: enabled 1 PCI: 00:1c.3: enabled 0 PCI: 00:1c.4: enabled 0 PCI: 00:1c.5: enabled 0 PCI: 00:1d.0: enabled 0 PCI: 00:1e.0: enabled 0 PCI: 00:1f.0: enabled 1 PNP: 0c31.0: enabled 1 PCI: 00:1f.2: enabled 1 PCI: 00:1f.3: enabled 0 PCI: 00:1f.6: enabled 1 Compare with tree... Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 DOMAIN: 0000: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:02.0: enabled 1 PCI: 00:03.0: enabled 1 PCI: 00:13.0: enabled 1 PCI: 00:14.0: enabled 1 PCI: 00:15.0: enabled 1 PCI: 00:15.1: enabled 1 PCI: 00:15.2: enabled 1 PCI: 00:15.3: enabled 1 PCI: 00:15.4: enabled 0 PCI: 00:15.5: enabled 0 PCI: 00:15.6: enabled 0 PCI: 00:16.0: enabled 1 PCI: 00:16.1: enabled 0 PCI: 00:16.2: enabled 0 PCI: 00:16.3: enabled 0 PCI: 00:17.0: enabled 0 PCI: 00:19.0: enabled 0 PCI: 00:1b.0: enabled 0 PCI: 00:1c.0: enabled 0 PCI: 00:1c.1: enabled 0 PCI: 00:1c.2: enabled 1 PCI: 00:1c.3: enabled 0 PCI: 00:1c.4: enabled 0 PCI: 00:1c.5: enabled 0 PCI: 00:1d.0: enabled 0 PCI: 00:1e.0: enabled 0 PCI: 00:1f.0: enabled 1 PNP: 0c31.0: enabled 1 PCI: 00:1f.2: enabled 1 PCI: 00:1f.3: enabled 0 PCI: 00:1f.6: enabled 1 Root Device scanning... root_dev_scan_bus for Root Device CPU_CLUSTER: 0 enabled DOMAIN: 0000 enabled DOMAIN: 0000 scanning... PCI: pci_scan_bus for bus 00 PCI: 00:00.0 [8086/0000] ops PCI: 00:00.0 [8086/1604] enabled PCI: 00:02.0 [8086/0000] ops PCI: 00:02.0 [8086/1626] enabled PCI: 00:03.0 [8086/0000] ops PCI: 00:03.0 [8086/160c] enabled PCI: 00:13.0 [8086/0000] ops PCI: 00:13.0 [8086/9cb6] enabled PCI: 00:14.0 [8086/0000] ops PCI: 00:14.0 [8086/9cb1] enabled PCI: 00:15.0 [8086/0000] ops PCI: 00:15.0 [8086/9ce0] enabled PCI: 00:15.1 [8086/0000] ops PCI: 00:15.1 [8086/9ce1] enabled PCI: 00:15.2 [8086/0000] ops PCI: 00:15.2 [8086/9ce2] enabled PCI: 00:15.3 [8086/0000] ops PCI: 00:15.3 [8086/9ce5] enabled PCI: 00:15.4: Disabling device PCI: 00:15.5: Disabling device PCI: 00:15.6: Disabling device PCI: 00:16.0 [8086/0000] ops PCI: 00:16.0 [8086/9cba] enabled PCI: 00:16.1: Disabling device PCI: 00:16.2: Disabling device PCI: 00:16.3: Disabling device PCI: 00:17.0: Disabling device PCI: 00:19.0: Disabling device PCI: 00:1b.0 [8086/0000] ops HDA disabled, I/O buffers routed to ADSP PCI: 00:1b.0 [8086/9ca0] disabled PCI: 00:1c.0 [8086/0000] bus ops PCI: 00:1c.0 [8086/9c90] disabled PCI: 00:1c.1 [8086/0000] bus ops PCI: 00:1c.1 [8086/9c92] disabled PCI: 00:1c.2 [8086/0000] bus ops PCIe Root Port 3 ASPM is enabled PCI: 00:1c.2 [8086/9c94] enabled PCI: 00:1c.3 [8086/0000] bus ops PCI: 00:1c.3 [8086/9c96] disabled PCI: 00:1c.4 [8086/0000] bus ops PCI: 00:1c.4 [8086/9c98] disabled PCI: 00:1c.5 [8086/0000] bus ops PCI: 00:1c.0: Disabling device PCI: 00:1c.1: Disabling device PCI: 00:1c.3: Disabling device PCI: 00:1c.4: Disabling device PCI: 00:1c.4: Timeout waiting for 328h PCI: 00:1c.5: Disabling device PCI: 00:1c.5: Timeout waiting for 328h PCH: PCIe map 1c.2 -> 1c.0 PCH: PCIe map 1c.0 -> 1c.1 PCH: PCIe map 1c.1 -> 1c.2 PCH: RPFN 0x00543210 -> 0x00dcb0a9 PCI: 00:1c.5 [8086/9c9a] disabled PCI: 00:1e.0: Disabling device PCI: 00:1f.0 [8086/0000] bus ops PCI: 00:1f.0 [8086/9cc3] enabled PCI: 00:1f.2 [8086/0000] ops PCI: 00:1f.2 [8086/9c83] enabled PCI: 00:1f.3: Disabling device PCI: 00:1f.6 [8086/9ca4] enabled PCI: 00:1c.0 scanning... do_pci_scan_bridge for PCI: 00:1c.0 PCI: pci_scan_bus for bus 01 scan_bus: scanning of bus PCI: 00:1c.0 took 8121 usecs PCI: 00:1f.0 scanning... scan_lpc_bus for PCI: 00:1f.0 PNP: 0c31.0 enabled scan_lpc_bus for PCI: 00:1f.0 done scan_bus: scanning of bus PCI: 00:1f.0 took 9898 usecs scan_bus: scanning of bus DOMAIN: 0000 took 220433 usecs root_dev_scan_bus for Root Device done scan_bus: scanning of bus Root Device took 238194 usecs done BS: BS_DEV_ENUMERATE times (us): entry 5 run 412960 exit 4 found VGA at PCI: 00:02.0 Setting up VGA for PCI: 00:02.0 Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device Allocating resources... Reading resources... Root Device read_resources bus 0 link: 0 CPU_CLUSTER: 0 read_resources bus 0 link: 0 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done DOMAIN: 0000 read_resources bus 0 link: 0 mc_add_fixed_mmio_resources: Adding PCIEXBAR @ 60 0xe0000000-0xe3ffffff. mc_add_fixed_mmio_resources: Adding MCHBAR @ 48 0xfed10000-0xfed17fff. mc_add_fixed_mmio_resources: Adding DMIBAR @ 68 0xfed18000-0xfed18fff. mc_add_fixed_mmio_resources: Adding EPBAR @ 40 0xfed19000-0xfed19fff. mc_add_fixed_mmio_resources: Adding GDXCBAR @ 5420 0xfed84000-0xfed84fff. mc_add_fixed_mmio_resources: Adding EDRAMBAR @ 5408 0xfed80000-0xfed83fff. MC MAP: TOM: 0x200000000 MC MAP: TOUUD: 0x280000000 MC MAP: MESEG_BASE: 0x7ffff00000 MC MAP: MESEG_LIMIT: 0xfffff MC MAP: REMAP_BASE: 0x200000000 MC MAP: REMAP_LIMIT: 0x27fffffff MC MAP: TOLUD: 0x80000000 MC MAP: BGSM: 0x7d800000 MC MAP: BDSM: 0x7e000000 MC MAP: TESGMB: 0x7d000000 MC MAP: GGC: 0x1c1 PCI: 00:1c.0 read_resources bus 1 link: 0 PCI: 00:1c.0 read_resources bus 1 link: 0 done PCI: 00:1f.0 read_resources bus 0 link: 0 PNP: 0c31.0 missing read_resources PCI: 00:1f.0 read_resources bus 0 link: 0 done DOMAIN: 0000 read_resources bus 0 link: 0 done Root Device read_resources bus 0 link: 0 done Done reading resources. Show resources in subtree (Root Device)...After reading. Root Device child on link 0 CPU_CLUSTER: 0 CPU_CLUSTER: 0 child on link 0 APIC: 00 APIC: 00 DOMAIN: 0000 child on link 0 PCI: 00:00.0 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100 PCI: 00:00.0 PCI: 00:00.0 resource base e0000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index 60 PCI: 00:00.0 resource base fed10000 size 8000 align 0 gran 0 limit 0 flags f0000200 index 48 PCI: 00:00.0 resource base fed18000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 68 PCI: 00:00.0 resource base fed19000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 40 PCI: 00:00.0 resource base fed84000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 5420 PCI: 00:00.0 resource base fed80000 size 4000 align 0 gran 0 limit 0 flags f0000200 index 5408 PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 0 PCI: 00:00.0 resource base c0000 size 7cf40000 align 0 gran 0 limit 0 flags e0004200 index 1 PCI: 00:00.0 resource base 7d000000 size 800000 align 0 gran 0 limit 0 flags f0004200 index 2 PCI: 00:00.0 resource base 7d800000 size 2800000 align 0 gran 0 limit 0 flags f0000200 index 3 PCI: 00:00.0 resource base 100000000 size 180000000 align 0 gran 0 limit 0 flags e0004200 index 4 PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 5 PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 6 PCI: 00:02.0 PCI: 00:02.0 resource base 0 size 1000000 align 24 gran 24 limit ffffffffffffffff flags 201 index 10 PCI: 00:02.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffffffffffff flags 1201 index 18 PCI: 00:02.0 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 index 20 PCI: 00:03.0 PCI: 00:03.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10 PCI: 00:13.0 PCI: 00:13.0 resource base 0 size 100000 align 20 gran 20 limit ffffffff flags 200 index 10 PCI: 00:13.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 14 PCI: 00:14.0 PCI: 00:14.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10 PCI: 00:15.0 PCI: 00:15.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 PCI: 00:15.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 14 PCI: 00:15.1 PCI: 00:15.1 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 PCI: 00:15.1 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 14 PCI: 00:15.2 PCI: 00:15.2 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 PCI: 00:15.2 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 14 PCI: 00:15.3 PCI: 00:15.3 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 PCI: 00:15.3 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 14 PCI: 00:15.4 PCI: 00:15.5 PCI: 00:15.6 PCI: 00:16.0 PCI: 00:16.0 resource base 0 size 20 align 12 gran 5 limit ffffffffffffffff flags 201 index 10 PCI: 00:16.1 PCI: 00:16.2 PCI: 00:16.3 PCI: 00:17.0 PCI: 00:19.0 PCI: 00:1b.0 PCI: 00:1c.1 PCI: 00:1c.2 PCI: 00:1c.0 PCI: 00:1c.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 00:1c.3 PCI: 00:1c.4 PCI: 00:1c.5 PCI: 00:1d.0 PCI: 00:1e.0 PCI: 00:1f.0 child on link 0 PNP: 0c31.0 PCI: 00:1f.0 resource base fec00000 size 1400000 align 0 gran 0 limit 0 flags c0000200 index 31fe PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0000100 index 0 PCI: 00:1f.0 resource base 1400 size 400 align 0 gran 0 limit 0 flags c0000100 index 48 PCI: 00:1f.0 resource base 1000 size 100 align 0 gran 0 limit 0 flags c0000100 index 40 PNP: 0c31.0 PNP: 0c31.0 resource base a size 0 align 0 gran 0 limit 0 flags c0000400 index 70 PCI: 00:1f.2 PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10 PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14 PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18 PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c PCI: 00:1f.2 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 PCI: 00:1f.2 resource base 0 size 8000 align 15 gran 15 limit ffffffff flags 200 index 24 PCI: 00:1f.3 PCI: 00:1f.6 PCI: 00:1f.6 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10 DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff PCI: 00:1c.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff PCI: 00:1c.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done PCI: 00:02.0 20 * [0x0 - 0x3f] io PCI: 00:1f.2 20 * [0x40 - 0x5f] io PCI: 00:1f.2 10 * [0x60 - 0x67] io PCI: 00:1f.2 18 * [0x68 - 0x6f] io PCI: 00:1f.2 14 * [0x70 - 0x73] io PCI: 00:1f.2 1c * [0x74 - 0x77] io DOMAIN: 0000 io: base: 78 size: 78 align: 6 gran: 0 limit: ffff done DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff PCI: 00:1c.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 00:1c.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done PCI: 00:1c.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 00:1c.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done PCI: 00:02.0 18 * [0x0 - 0xfffffff] prefmem PCI: 00:02.0 10 * [0x10000000 - 0x10ffffff] mem PCI: 00:13.0 10 * [0x11000000 - 0x110fffff] mem PCI: 00:14.0 10 * [0x11100000 - 0x1110ffff] mem PCI: 00:1f.2 24 * [0x11110000 - 0x11117fff] mem PCI: 00:03.0 10 * [0x11118000 - 0x1111bfff] mem PCI: 00:13.0 14 * [0x1111c000 - 0x1111cfff] mem PCI: 00:15.0 10 * [0x1111d000 - 0x1111dfff] mem PCI: 00:15.0 14 * [0x1111e000 - 0x1111efff] mem PCI: 00:15.1 10 * [0x1111f000 - 0x1111ffff] mem PCI: 00:15.1 14 * [0x11120000 - 0x11120fff] mem PCI: 00:15.2 10 * [0x11121000 - 0x11121fff] mem PCI: 00:15.2 14 * [0x11122000 - 0x11122fff] mem PCI: 00:15.3 10 * [0x11123000 - 0x11123fff] mem PCI: 00:15.3 14 * [0x11124000 - 0x11124fff] mem PCI: 00:1f.6 10 * [0x11125000 - 0x11125fff] mem PCI: 00:16.0 10 * [0x11126000 - 0x1112601f] mem DOMAIN: 0000 mem: base: 11126020 size: 11126020 align: 28 gran: 0 limit: ffffffff done avoid_fixed_resources: DOMAIN: 0000 avoid_fixed_resources:@DOMAIN: 0000 10000000 limit 0000ffff avoid_fixed_resources:@DOMAIN: 0000 10000100 limit ffffffff constrain_resources: PCI: 00:00.0 60 base e0000000 limit e3ffffff mem (fixed) constrain_resources: PCI: 00:00.0 00 base 00000000 limit 0009ffff mem (fixed) constrain_resources: PCI: 00:00.0 01 base 000c0000 limit 7cffffff mem (fixed) constrain_resources: PCI: 00:00.0 02 base 7d000000 limit 7d7fffff mem (fixed) constrain_resources: PCI: 00:00.0 03 base 7d800000 limit 7fffffff mem (fixed) constrain_resources: PCI: 00:1f.0 00 base 00000000 limit 00000fff io (fixed) constrain_resources: PCI: 00:1f.0 48 base 00001400 limit 000017ff io (fixed) skipping PNP: 0c31.0@70 fixed resource, size=0! avoid_fixed_resources:@DOMAIN: 0000 10000000 base 00001800 limit 0000ffff avoid_fixed_resources:@DOMAIN: 0000 10000100 base c0000000 limit dfffffff Setting resources... DOMAIN: 0000 io: base:1800 size:78 align:6 gran:0 limit:ffff PCI: 00:02.0 20 * [0x1800 - 0x183f] io PCI: 00:1f.2 20 * [0x1840 - 0x185f] io PCI: 00:1f.2 10 * [0x1860 - 0x1867] io PCI: 00:1f.2 18 * [0x1868 - 0x186f] io PCI: 00:1f.2 14 * [0x1870 - 0x1873] io PCI: 00:1f.2 1c * [0x1874 - 0x1877] io DOMAIN: 0000 io: next_base: 1878 size: 78 align: 6 gran: 0 done PCI: 00:1c.0 io: base:ffff size:0 align:12 gran:12 limit:ffff PCI: 00:1c.0 io: next_base: ffff size: 0 align: 12 gran: 12 done DOMAIN: 0000 mem: base:c0000000 size:11126020 align:28 gran:0 limit:dfffffff PCI: 00:02.0 18 * [0xc0000000 - 0xcfffffff] prefmem PCI: 00:02.0 10 * [0xd0000000 - 0xd0ffffff] mem PCI: 00:13.0 10 * [0xd1000000 - 0xd10fffff] mem PCI: 00:14.0 10 * [0xd1100000 - 0xd110ffff] mem PCI: 00:1f.2 24 * [0xd1110000 - 0xd1117fff] mem PCI: 00:03.0 10 * [0xd1118000 - 0xd111bfff] mem PCI: 00:13.0 14 * [0xd111c000 - 0xd111cfff] mem PCI: 00:15.0 10 * [0xd111d000 - 0xd111dfff] mem PCI: 00:15.0 14 * [0xd111e000 - 0xd111efff] mem PCI: 00:15.1 10 * [0xd111f000 - 0xd111ffff] mem PCI: 00:15.1 14 * [0xd1120000 - 0xd1120fff] mem PCI: 00:15.2 10 * [0xd1121000 - 0xd1121fff] mem PCI: 00:15.2 14 * [0xd1122000 - 0xd1122fff] mem PCI: 00:15.3 10 * [0xd1123000 - 0xd1123fff] mem PCI: 00:15.3 14 * [0xd1124000 - 0xd1124fff] mem PCI: 00:1f.6 10 * [0xd1125000 - 0xd1125fff] mem PCI: 00:16.0 10 * [0xd1126000 - 0xd112601f] mem DOMAIN: 0000 mem: next_base: d1126020 size: 11126020 align: 28 gran: 0 done PCI: 00:1c.0 prefmem: base:dfffffff size:0 align:20 gran:20 limit:dfffffff PCI: 00:1c.0 prefmem: next_base: dfffffff size: 0 align: 20 gran: 20 done PCI: 00:1c.0 mem: base:dfffffff size:0 align:20 gran:20 limit:dfffffff PCI: 00:1c.0 mem: next_base: dfffffff size: 0 align: 20 gran: 20 done Root Device assign_resources, bus 0 link: 0 DOMAIN: 0000 assign_resources, bus 0 link: 0 PCI: 00:02.0 10 <- [0x00d0000000 - 0x00d0ffffff] size 0x01000000 gran 0x18 mem64 PCI: 00:02.0 18 <- [0x00c0000000 - 0x00cfffffff] size 0x10000000 gran 0x1c prefmem64 PCI: 00:02.0 20 <- [0x0000001800 - 0x000000183f] size 0x00000040 gran 0x06 io PCI: 00:03.0 10 <- [0x00d1118000 - 0x00d111bfff] size 0x00004000 gran 0x0e mem64 PCI: 00:13.0 10 <- [0x00d1000000 - 0x00d10fffff] size 0x00100000 gran 0x14 mem PCI: 00:13.0 14 <- [0x00d111c000 - 0x00d111cfff] size 0x00001000 gran 0x0c mem PCI: 00:14.0 10 <- [0x00d1100000 - 0x00d110ffff] size 0x00010000 gran 0x10 mem64 PCI: 00:15.0 10 <- [0x00d111d000 - 0x00d111dfff] size 0x00001000 gran 0x0c mem PCI: 00:15.0 14 <- [0x00d111e000 - 0x00d111efff] size 0x00001000 gran 0x0c mem PCI: 00:15.1 10 <- [0x00d111f000 - 0x00d111ffff] size 0x00001000 gran 0x0c mem PCI: 00:15.1 14 <- [0x00d1120000 - 0x00d1120fff] size 0x00001000 gran 0x0c mem PCI: 00:15.2 10 <- [0x00d1121000 - 0x00d1121fff] size 0x00001000 gran 0x0c mem PCI: 00:15.2 14 <- [0x00d1122000 - 0x00d1122fff] size 0x00001000 gran 0x0c mem PCI: 00:15.3 10 <- [0x00d1123000 - 0x00d1123fff] size 0x00001000 gran 0x0c mem PCI: 00:15.3 14 <- [0x00d1124000 - 0x00d1124fff] size 0x00001000 gran 0x0c mem PCI: 00:16.0 10 <- [0x00d1126000 - 0x00d112601f] size 0x00000020 gran 0x05 mem64 PCI: 00:1c.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 01 io PCI: 00:1c.0 24 <- [0x00dfffffff - 0x00dffffffe] size 0x00000000 gran 0x14 bus 01 prefmem PCI: 00:1c.0 20 <- [0x00dfffffff - 0x00dffffffe] size 0x00000000 gran 0x14 bus 01 mem PCI: 00:1f.0 assign_resources, bus 0 link: 0 PNP: 0c31.0 missing set_resources PCI: 00:1f.0 assign_resources, bus 0 link: 0 PCI: 00:1f.2 10 <- [0x0000001860 - 0x0000001867] size 0x00000008 gran 0x03 io PCI: 00:1f.2 14 <- [0x0000001870 - 0x0000001873] size 0x00000004 gran 0x02 io PCI: 00:1f.2 18 <- [0x0000001868 - 0x000000186f] size 0x00000008 gran 0x03 io PCI: 00:1f.2 1c <- [0x0000001874 - 0x0000001877] size 0x00000004 gran 0x02 io PCI: 00:1f.2 20 <- [0x0000001840 - 0x000000185f] size 0x00000020 gran 0x05 io PCI: 00:1f.2 24 <- [0x00d1110000 - 0x00d1117fff] size 0x00008000 gran 0x0f mem PCI: 00:1f.6 10 <- [0x00d1125000 - 0x00d1125fff] size 0x00001000 gran 0x0c mem64 DOMAIN: 0000 assign_resources, bus 0 link: 0 Root Device assign_resources, bus 0 link: 0 Done setting resources. Show resources in subtree (Root Device)...After assigning values. Root Device child on link 0 CPU_CLUSTER: 0 CPU_CLUSTER: 0 child on link 0 APIC: 00 APIC: 00 DOMAIN: 0000 child on link 0 PCI: 00:00.0 DOMAIN: 0000 resource base 1800 size 78 align 6 gran 0 limit ffff flags 40040100 index 10000000 DOMAIN: 0000 resource base c0000000 size 11126020 align 28 gran 0 limit dfffffff flags 40040200 index 10000100 PCI: 00:00.0 PCI: 00:00.0 resource base e0000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index 60 PCI: 00:00.0 resource base fed10000 size 8000 align 0 gran 0 limit 0 flags f0000200 index 48 PCI: 00:00.0 resource base fed18000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 68 PCI: 00:00.0 resource base fed19000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 40 PCI: 00:00.0 resource base fed84000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 5420 PCI: 00:00.0 resource base fed80000 size 4000 align 0 gran 0 limit 0 flags f0000200 index 5408 PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 0 PCI: 00:00.0 resource base c0000 size 7cf40000 align 0 gran 0 limit 0 flags e0004200 index 1 PCI: 00:00.0 resource base 7d000000 size 800000 align 0 gran 0 limit 0 flags f0004200 index 2 PCI: 00:00.0 resource base 7d800000 size 2800000 align 0 gran 0 limit 0 flags f0000200 index 3 PCI: 00:00.0 resource base 100000000 size 180000000 align 0 gran 0 limit 0 flags e0004200 index 4 PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 5 PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 6 PCI: 00:02.0 PCI: 00:02.0 resource base d0000000 size 1000000 align 24 gran 24 limit d0ffffff flags 60000201 index 10 PCI: 00:02.0 resource base c0000000 size 10000000 align 28 gran 28 limit cfffffff flags 60001201 index 18 PCI: 00:02.0 resource base 1800 size 40 align 6 gran 6 limit 183f flags 60000100 index 20 PCI: 00:03.0 PCI: 00:03.0 resource base d1118000 size 4000 align 14 gran 14 limit d111bfff flags 60000201 index 10 PCI: 00:13.0 PCI: 00:13.0 resource base d1000000 size 100000 align 20 gran 20 limit d10fffff flags 60000200 index 10 PCI: 00:13.0 resource base d111c000 size 1000 align 12 gran 12 limit d111cfff flags 60000200 index 14 PCI: 00:14.0 PCI: 00:14.0 resource base d1100000 size 10000 align 16 gran 16 limit d110ffff flags 60000201 index 10 PCI: 00:15.0 PCI: 00:15.0 resource base d111d000 size 1000 align 12 gran 12 limit d111dfff flags 60000200 index 10 PCI: 00:15.0 resource base d111e000 size 1000 align 12 gran 12 limit d111efff flags 60000200 index 14 PCI: 00:15.1 PCI: 00:15.1 resource base d111f000 size 1000 align 12 gran 12 limit d111ffff flags 60000200 index 10 PCI: 00:15.1 resource base d1120000 size 1000 align 12 gran 12 limit d1120fff flags 60000200 index 14 PCI: 00:15.2 PCI: 00:15.2 resource base d1121000 size 1000 align 12 gran 12 limit d1121fff flags 60000200 index 10 PCI: 00:15.2 resource base d1122000 size 1000 align 12 gran 12 limit d1122fff flags 60000200 index 14 PCI: 00:15.3 PCI: 00:15.3 resource base d1123000 size 1000 align 12 gran 12 limit d1123fff flags 60000200 index 10 PCI: 00:15.3 resource base d1124000 size 1000 align 12 gran 12 limit d1124fff flags 60000200 index 14 PCI: 00:15.4 PCI: 00:15.5 PCI: 00:15.6 PCI: 00:16.0 PCI: 00:16.0 resource base d1126000 size 20 align 12 gran 5 limit d112601f flags 60000201 index 10 PCI: 00:16.1 PCI: 00:16.2 PCI: 00:16.3 PCI: 00:17.0 PCI: 00:19.0 PCI: 00:1b.0 PCI: 00:1c.1 PCI: 00:1c.2 PCI: 00:1c.0 PCI: 00:1c.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c PCI: 00:1c.0 resource base dfffffff size 0 align 20 gran 20 limit dfffffff flags 60081202 index 24 PCI: 00:1c.0 resource base dfffffff size 0 align 20 gran 20 limit dfffffff flags 60080202 index 20 PCI: 00:1c.3 PCI: 00:1c.4 PCI: 00:1c.5 PCI: 00:1d.0 PCI: 00:1e.0 PCI: 00:1f.0 child on link 0 PNP: 0c31.0 PCI: 00:1f.0 resource base fec00000 size 1400000 align 0 gran 0 limit 0 flags c0000200 index 31fe PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0000100 index 0 PCI: 00:1f.0 resource base 1400 size 400 align 0 gran 0 limit 0 flags c0000100 index 48 PCI: 00:1f.0 resource base 1000 size 100 align 0 gran 0 limit 0 flags c0000100 index 40 PNP: 0c31.0 PNP: 0c31.0 resource base a size 0 align 0 gran 0 limit 0 flags c0000400 index 70 PCI: 00:1f.2 PCI: 00:1f.2 resource base 1860 size 8 align 3 gran 3 limit 1867 flags 60000100 index 10 PCI: 00:1f.2 resource base 1870 size 4 align 2 gran 2 limit 1873 flags 60000100 index 14 PCI: 00:1f.2 resource base 1868 size 8 align 3 gran 3 limit 186f flags 60000100 index 18 PCI: 00:1f.2 resource base 1874 size 4 align 2 gran 2 limit 1877 flags 60000100 index 1c PCI: 00:1f.2 resource base 1840 size 20 align 5 gran 5 limit 185f flags 60000100 index 20 PCI: 00:1f.2 resource base d1110000 size 8000 align 15 gran 15 limit d1117fff flags 60000200 index 24 PCI: 00:1f.3 PCI: 00:1f.6 PCI: 00:1f.6 resource base d1125000 size 1000 align 12 gran 12 limit d1125fff flags 60000201 index 10 Done allocating resources. BS: BS_DEV_RESOURCES times (us): entry 4 run 1651122 exit 4 Enabling resources... PCI: 00:00.0 subsystem <- 8086/1604 PCI: 00:00.0 cmd <- 06 PCI: 00:02.0 subsystem <- 8086/1626 PCI: 00:02.0 cmd <- 07 PCI: 00:03.0 subsystem <- 8086/160c PCI: 00:03.0 cmd <- 07 PCI: 00:13.0 subsystem <- 8086/9cb6 PCI: 00:13.0 cmd <- 107 PCI: 00:14.0 subsystem <- 8086/9cb1 PCI: 00:14.0 cmd <- 107 PCI: 00:15.0 subsystem <- 8086/9ce0 PCI: 00:15.0 cmd <- 107 PCI: 00:15.1 subsystem <- 8086/9ce1 PCI: 00:15.1 cmd <- 107 PCI: 00:15.2 subsystem <- 8086/9ce2 PCI: 00:15.2 cmd <- 107 PCI: 00:15.3 subsystem <- 8086/9ce5 PCI: 00:15.3 cmd <- 107 PCI: 00:16.0 subsystem <- 8086/9cba PCI: 00:16.0 cmd <- 07 PCI: 00:1c.0 bridge ctrl <- 0003 PCI: 00:1c.0 subsystem <- 8086/9c94 PCI: 00:1c.0 cmd <- 05 PCI: 00:1f.0 subsystem <- 8086/9cc3 PCI: 00:1f.0 cmd <- 107 PCI: 00:1f.2 subsystem <- 8086/9c83 PCI: 00:1f.2 cmd <- 107 PCI: 00:1f.6 subsystem <- 8086/9ca4 PCI: 00:1f.6 cmd <- 107 done. BS: BS_DEV_ENABLE times (us): entry 5 run 80526 exit 4 Initializing devices... Root Device init ... mainboard_init mainboard_ec_init Chrome EC: Set WAKE mask to 0x00000000 Missing Chromium EC memory map. Root Device init finished in 11316 usecs CPU_CLUSTER: 0 init ... MTRR: Physical address space: 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 0x00000000000c0000 - 0x000000007d800000 size 0x7d740000 type 6 0x000000007d800000 - 0x00000000c0000000 size 0x42800000 type 0 0x00000000c0000000 - 0x00000000d0000000 size 0x10000000 type 1 0x00000000d0000000 - 0x0000000100000000 size 0x30000000 type 0 0x0000000100000000 - 0x0000000280000000 size 0x180000000 type 6 MTRR: Fixed MSR 0x250 0x0606060606060606 MTRR: Fixed MSR 0x258 0x0606060606060606 MTRR: Fixed MSR 0x259 0x0000000000000000 MTRR: Fixed MSR 0x268 0x0606060606060606 MTRR: Fixed MSR 0x269 0x0606060606060606 MTRR: Fixed MSR 0x26a 0x0606060606060606 MTRR: Fixed MSR 0x26b 0x0606060606060606 MTRR: Fixed MSR 0x26c 0x0606060606060606 MTRR: Fixed MSR 0x26d 0x0606060606060606 MTRR: Fixed MSR 0x26e 0x0606060606060606 MTRR: Fixed MSR 0x26f 0x0606060606060606 call enable_fixed_mtrr() CPU physical address size: 39 bits MTRR: default type WB/UC MTRR counts: 6/6. MTRR: UC selected as default type. MTRR: 0 base 0x0000000000000000 mask 0x0000007f80000000 type 6 MTRR: 1 base 0x000000007d800000 mask 0x0000007fff800000 type 0 MTRR: 2 base 0x000000007e000000 mask 0x0000007ffe000000 type 0 MTRR: 3 base 0x00000000c0000000 mask 0x0000007ff0000000 type 1 MTRR: 4 base 0x0000000100000000 mask 0x0000007f00000000 type 6 MTRR: 5 base 0x0000000200000000 mask 0x0000007f80000000 type 6 MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled Initializing VR config. PCODE: 24MHz BLCK calibration response: 0 PCODE: 24MHz BLCK calibration value: 0x850609d3 PCH Power: PCODE Levels 0x3f245102 0x0058f38a CPU has 2 cores, 4 threads enabled. Setting up SMI for CPU Will perform SMM setup. CBFS: 'Master Header Locator' located CBFS at [300100:3fffc0) CBFS: Locating 'cpu_microcode_blob.bin' CBFS: Found @ offset af40 size 11440 microcode: sig=0x306d4 pf=0x40 revision=0x1f CPU: Intel(R) Core(TM) i7-5650U CPU @ 2.20GHz. Loading module at 00030000 with entry 00030000. filesize: 0x130 memsize: 0x130 Processing 16 relocs. Offset value of 0x00030000 Attempting to start 3 APs Waiting for 10ms after sending INIT. Waiting for 1st SIPI to complete...AP: slot 1 apic_id 1. AP: slot 3 apic_id 3. AP: slot 2 apic_id 2. done. Waiting for 2nd SIPI to complete...done. Loading module at 00038000 with entry 00038000. filesize: 0x1a8 memsize: 0x1a8 Processing 12 relocs. Offset value of 0x00038000 SMM Module: stub loaded at 00038000. Will call 7cfaee31(00000000) Installing SMM handler to 0x7d000000 Loading module at 7d010000 with entry 7d010070. filesize: 0xe48 memsize: 0x4e68 Processing 35 relocs. Offset value of 0x7d010000 Loading module at 7d008000 with entry 7d008000. filesize: 0x1a8 memsize: 0x1a8 Processing 12 relocs. Offset value of 0x7d008000 SMM Module: placing jmp sequence at 7d007c00 rel16 0x03fd SMM Module: placing jmp sequence at 7d007800 rel16 0x07fd SMM Module: placing jmp sequence at 7d007400 rel16 0x0bfd SMM Module: stub loaded at 7d008000. Will call 7d010070(00000000) Initializing Southbridge SMI... ... pmbase = 0x1000 SMI_STS: TCO PM1 PM1_STS: TMROF New SMBASE 0x7d000000 In relocation handler: CPU 0 New SMBASE=0x7d000000 IEDBASE=0x7d400000 Writing SMRR. base = 0x7d000006, mask=0xff800800 Relocation complete. New SMBASE 0x7cfffc00 In relocation handler: CPU 1 New SMBASE=0x7cfffc00 IEDBASE=0x7d400000 Writing SMRR. base = 0x7d000006, mask=0xff800800 Relocation complete. New SMBASE 0x7cfff400 In relocation handler: CPU 3 New SMBASE=0x7cfff400 IEDBASE=0x7d400000 Writing SMRR. base = 0x7d000006, mask=0xff800800 Relocation complete. New SMBASE 0x7cfff800 In relocation handler: CPU 2 New SMBASE=0x7cfff800 IEDBASE=0x7d400000 Writing SMRR. base = 0x7d000006, mask=0xff800800 Relocation complete. Initializing CPU #0 CPU: vendor Intel device 306d4 CPU: family 06, model 3d, stepping 04 Setting up local APIC... apic_id: 0x00 done. VMX status: disabled, unlocked cpu: energy policy set to 6 Turbo is available but hidden Turbo has been enabled CPU #0 initialized Initializing CPU #1 Initializing CPU #2 Initializing CPU #3 CPU: vendor Intel device 306d4 CPU: family 06, model 3d, stepping 04 CPU: vendor Intel device 306d4 CPU: family 06, model 3d, stepping 04 Setting up local APIC...Setting up local APIC... apic_id: 0x02 done. apic_id: 0x03 done. VMX status: disabled, unlocked VMX status: disabled, unlocked cpu: energy policy set to 6 cpu: energy policy set to 6 CPU #2 initialized CPU #3 initialized CPU: vendor Intel device 306d4 CPU: family 06, model 3d, stepping 04 Setting up local APIC... apic_id: 0x01 done. VMX status: disabled, unlocked cpu: energy policy set to 6 CPU #1 initialized cpu: frequency set to 3200 Enabling SMIs. Locking SMM. CPU_CLUSTER: 0 init finished in 443935 usecs PCI: 00:00.0 init ... Set BIOS_RESET_CPL CPU TDP: 15 Watts PCI: 00:00.0 init finished in 6390 usecs PCI: 00:02.0 init ... CBFS: 'Master Header Locator' located CBFS at [300100:3fffc0) CBFS: Locating 'pci8086,1626.rom' CBFS: 'pci8086,1626.rom' not found. CBFS: 'Master Header Locator' located CBFS at [300100:3fffc0) CBFS: Locating 'pci8086,0406.rom' CBFS: Found @ offset 47900 size 10000 In CBFS, ROM address for PCI: 00:02.0 = fff47a48 PCI expansion ROM, signature 0xaa55, INIT size 0x10000, data ptr 0x0040 PCI ROM image, vendor ID 8086, device ID 0406, PCI ROM image, Class Code 030000, Code Type 00 Copying VGA ROM Image from fff47a48 to 0xc0000, 0x10000 bytes pci_dev_init, 2 Real mode stub @00000600: 867 bytes Calling Option ROM... intel_vga_int15_handler: AX=5f35 BX=c000 CX=0002 DX=03da ... Option ROM returned. VGA Option ROM was run PCI: 00:02.0 init finished in 1309735 usecs PCI: 00:03.0 init ... Mini-HD: base = d1118000 HDA: Initializing codec #0 HDA: codec viddid: 80862808 HDA: No verb table entry found PCI: 00:03.0 init finished in 14983 usecs PCI: 00:13.0 init ... ADSP: Enable ACPI Mode IRQ3 PCI: 00:13.0 init finished in 4616 usecs PCI: 00:14.0 init ... PCI: 00:14.0 init finished in 1999 usecs PCI: 00:15.0 init ... Initializing Serial IO device PCI: 00:15.0 init finished in 4769 usecs PCI: 00:15.1 init ... Initializing Serial IO device PCI: 00:15.1 init finished in 4718 usecs PCI: 00:15.2 init ... Initializing Serial IO device PCI: 00:15.2 init finished in 4717 usecs PCI: 00:15.3 init ... Initializing Serial IO device PCI: 00:15.3 init finished in 4716 usecs PCI: 00:16.0 init ... ME: FW Partition Table : OK ME: Bringup Loader Failure : NO ME: Firmware Init Complete : NO ME: Manufacturing Mode : YES ME: Boot Options Present : NO ME: Update In Progress : NO ME: Current Working State : Initializing ME: Current Operation State : Bring up ME: Current Operation Mode : Security Override via Jumper ME: Error Code : Debug Failure ME: Progress Phase : BUP Phase ME: Power Management Event : Pseudo-global reset ME: Progress Phase State : 0x7b intel_me_path: mbp is not ready! ME: BIOS path: Error ME: MBP not ready PCI: 00:16.0 init finished in 53821 usecs PCI: 00:1c.0 init ... Initializing PCH PCIe bridge. PCI: 00:1c.0 init finished in 4689 usecs PCI: 00:1f.0 init ... rtc_failed = 0x4 RTC Init RTC: Clear requested zeroing cmos IOAPIC: Initializing IOAPIC at 0xfec00000 IOAPIC: Bootstrap Processor Local APIC = 0x00 IOAPIC: ID = 0x02 IOAPIC: Dumping registers reg 0x0000: 0x02000000 reg 0x0001: 0x00170020 reg 0x0002: 0x00000000 Set power off after power failure. ________________________________ From: Matt DeVillier <matt.devillier(a)gmail.com> Sent: Monday, July 31, 2017 7:06 PM To: Zheng Bao Cc: Nico Huber; coreboot(a)coreboot.org; stefan.reinauer(a)coreboot.org Subject: Re: [coreboot] Broadwell-U hangs at VGA init you want to extract the refcode blob as so: cbfstool shellball.rom extract -r BOOT_STUB -n fallback/refcode -f refcode.elf -m x86 then add it into your build On Mon, Jul 31, 2017 at 8:43 AM, Zheng Bao <fishbaoz(a)hotmail.com<mailto:fishbaoz@hotmail.com>> wrote: Thanks. That really helps. About the REFCODE_BLOB, the BLOB I extracted from ball-rom is BIN, instead of ELF which is required by current CBFS and rmodule in source. (And revision in ball-rom is not in main tree of repository.) Any idea to get REFCODE_BLOB? Thanks. Zheng ________________________________ From: Nico Huber <nico.huber(a)secunet.com<mailto:nico.huber@secunet.com>> Sent: Monday, July 31, 2017 10:52 AM To: Zheng Bao; coreboot(a)coreboot.org<mailto:coreboot@coreboot.org>; Matt DeVillier; stefan.reinauer(a)coreboot.org<mailto:stefan.reinauer@coreboot.org> Subject: Re: [coreboot] Broadwell-U hangs at VGA init Hi Zheng, On 30.07.2017 16:13, Zheng Bao wrote: > I have got the mrc.bin and mem init has got passed. > Now the new problem is that it hangs at VGA init. > > static void igd_setup_panel(struct device *dev) > { > config_t *conf = dev->chip_info; > u32 reg32; > > /* Setup Digital Port Hotplug */ > reg32 = gtt_read(PCH_PORT_HOTPLUG); <------- It hangs here. > if (!reg32) { > reg32 = (conf->gpu_dp_b_hotplug & 0x7) << 2; > reg32 |= (conf->gpu_dp_c_hotplug & 0x7) << 10; > reg32 |= (conf->gpu_dp_d_hotplug & 0x7) << 18; > gtt_write(PCH_PORT_HOTPLUG, reg32); > } > > It turns out as soon as i access VGA bar0+0xc4030, it hangs. > while accessing bar0 + 0xa00a is ok. sounds like the PCH part of the display engine isn't operational (pro- bably not all, but most register offsets with bit 19 set reside in the PCH). There are few steps to enable it [1], yet the Broadwell port seems to rely on the blob to do it. The datasheet [2] suggests that the same settings should be done for Broadwell too, but I can't find it in the source. So that leads to the conclusion: You forgot to add the second blob (HAVE_REFCODE_BLOB, it's BS, it's annoying, but you need it). That publicly documented settings move from the open source code into blobs is a very bad sign, IMO. Now, anybody tell me again, that things with Intel are getting better and they might become more open (the sta- tistics seem to say the opposite: the blobs get bigger, weirder, take over more responsibilities _and_ do a lot of stuff we already had open source for earlier platforms). Nico [1] src/southbridge/intel/lynxpoint/lpc.c:725 [2] Intel Document Number: 330837

1 0

ASUS KGPE-D16 Automated Test Failure [master]
by Raptor Engineering Automated Coreboot Test Stand Aug. 2, 2017

Aug. 2, 2017

The ASUS KGPE-D16 fails verification for branch master as of commit b08d73b8456c85ded8e27f37023aba27a0933031 The following tests failed: BOOT_FAILURE Commits since last successful test: See attached log for details This message was automatically generated from Raptor Engineering's ASUS KGPE-D16 test stand Want to test on your own equipment? Check out https://www.raptorengineering.com/content/REACTS/intro.html Raptor Engineering also offers coreboot consulting services! Please visit https://www.raptorengineering.com for more information Please contact Timothy Pearson at Raptor Engineering <tpearson(a)raptorengineering.com> regarding any issues stemming from this notification

1 0

Anybody going to SHA hacker camp?
by Nico Rikken Aug. 1, 2017

Aug. 1, 2017

Is anybody of the Coreboot community going to the SHA hacker camp the coming weekend? Perhaps we can meet up. I'll also bring some Coreboot- flashed T400's and X200 for sale. https://wiki.sha2017.org/w/User:Nico Kind regards, Nico Rikken (NL)

3 2

Re: [coreboot] Fwd: [FWD: Request for Chromebook Authentication Module Development]
by ron minnich Aug. 1, 2017

Aug. 1, 2017

This doesn't make sense to me. By putting the PIN in memory you expose its value at all steps in the delivery process. Chromebooks have a very good mechanism for keys that can be personalized to an individual, see my talk at last year's linuxconf in berlin where I showed how you can make a chromebook boot only a chromeos you have signed personally. Security is really hard to get right. I think you need to build on what's in the chromebook, not design your own addon, because that's almost certainly going to weaken security. What are you trying to do here? Is the target software stack chromeos? Why the PIN? We may want to drop coreboot list off this discussion but there are so many smart people on the coreboot list I wanted to give them a chance to respond too.

1 0

Re: [coreboot] Haswell port
by Peter Stuge Aug. 1, 2017

Aug. 1, 2017

Hello Konstantin, Konstantin Novikov wrote: > Yes, now I'm using VGA port. Yes, we'll commit our changes, but after we'll > end port. S3 isn't working now, and we have some troubles with Super I/O, > but we already did this work with b75-port. You don't have to wait until you have finished everything, in fact it is better if you don't. It is always easier for the community to review and accept many small changes which are spread out in time. Also, if there are some comments on your earlier changes, it is nice for you to have everything fresh in mind, because you have not yet finished the work. Kind regards //Peter

1 0

Re: [coreboot] Broadwell-U hangs at VGA init (update)
by Zheng Bao Aug. 1, 2017

Aug. 1, 2017

Refcode is added and VGA BIOS passes. hangs at "Set power off after power failure. " It seems that the ME is not 100% right. Zheng coreboot-4.6-891-gca74434-dirty Fri Jul 28 06:45:02 UTC 2017 romstage starting... PM1_STS: 0000 PM1_EN: 0000 PM1_CNT: 00000000 TCO_STS: 0000 0000 GPE0_STS: 08fe08fc 10000f35 6005e200 00000000 GPE0_EN: 00000000 00000000 00000000 00000000 GEN_PMCON: 0200 2024 4206 Previous Sleep State: S5 CPU: Intel(R) Core(TM) i7-5650U CPU @ 2.20GHz CPU: ID 306d4, Broadwell E0 or F0, ucode: 0000001f CPU: AES supported, TXT supported, VT supported MCH: device id 1604 (rev 09) is Broadwell F0 PCH: device id 9cc3 (rev 03) is Broadwell U Premium IGD: device id 1626 (rev 09) is Broadwell U GT3 (15W) CPU: frequency set to 2200 MHz SPD: index 0 (GPIO65=0 GPIO67=0 GPIO68=0 GPIO69=0) CBFS: 'Master Header Locator' located CBFS at [300100:3fffc0) CBFS: Locating 'spd.bin' CBFS: Found @ offset 6b080 size 1000 SPD: module type is DDR3 SPD: module part is 99U5469-011.A01LF SPD: banks 8, ranks 1, rows 16, columns 10, density 8192 Mb SPD: device width 16 bits, bus width 64 bits SPD: module size is 4096 MB (per channel) ME: FW Partition Table : OK ME: Bringup Loader Failure : NO ME: Firmware Init Complete : NO ME: Manufacturing Mode : YES ME: Boot Options Present : NO ME: Update In Progress : NO ME: Current Working State : Initializing ME: Current Operation State : Bring up ME: Current Operation Mode : Security Override via Jumper ME: Error Code : Debug Failure ME: Progress Phase : BUP Phase ME: Power Management Event : Pseudo-global reset ME: Progress Phase State : 0x7b ERROR: ME failed to respond FMAP: Found "FLASH" version 1.1 at 300000. FMAP: base = ffc00000 size = 400000 #areas = 3 MRC: no data in 'RW_MRC_CACHE' No MRC cache found. CBFS: 'Master Header Locator' located CBFS at [300100:3fffc0) CBFS: Locating 'mrc.bin' CBFS: Found @ offset 9fec0 size 36998 Starting Memory Reference Code Initializing Policy Installing common PPI MRC: Starting... Initializing Memory MRC: Done. MRC Version 2.6.0 Build 0 memcfg DDR3 clock 1600 MHz memcfg channel assignment: A: 0, B 1, C 2 memcfg channel[0] config (00780010): enhanced interleave mode on rank interleave on DIMMA 4096 MB width x16 single rank, selected DIMMB 0 MB width x16 single rank memcfg channel[1] config (00780010): enhanced interleave mode on rank interleave on DIMMA 4096 MB width x16 single rank, selected DIMMB 0 MB width x16 single rank CBMEM: IMD: root @ 7cfff000 254 entries. IMD: root @ 7cffec00 62 entries. External stage cache: IMD: root @ 7d3ff000 254 entries. IMD: root @ 7d3fec00 62 entries. MRC data at ff7d0d9c 6246 bytes create cbmem for dimm information MLB: board version Unknown CBFS: 'Master Header Locator' located CBFS at [300100:3fffc0) CBFS: Locating 'fallback/ramstage' CBFS: Found @ offset 1c400 size 144b9 Decompressing stage fallback/ramstage @ 0x7cf97fc0 (257104 bytes) Loading module at 7cf98000 with entry 7cf98000. filesize: 0x2c380 memsize: 0x3ec10 Processing 2817 relocs. Offset value of 0x7ce98000 coreboot-4.6-891-gca74434-dirty Fri Jul 28 06:45:02 UTC 2017 ramstage starting... Normal boot. BS: BS_PRE_DEVICE times (us): entry 5 run 7 exit 5 CBFS: 'Master Header Locator' located CBFS at [300100:3fffc0) CBFS: Locating 'fallback/refcode' CBFS: Found @ offset 30900 size 1274b Decompressing stage fallback/refcode @ 0x7cf62fc0 (201528 bytes) Loading module at 7cf63000 with entry 7cf63000. filesize: 0x29b38 memsize: 0x312f8 Processing 1695 relocs. Offset value of 0x7cf63000 Initializing Policy Installing common PPI PEI: Starting... Initializing System Agent Initializing PCH PEI: Done. BS: BS_DEV_INIT_CHIPS times (us): entry 5 run 94299 exit 5 Enumerating buses... Show all devs... Before device enumeration. Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 DOMAIN: 0000: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:02.0: enabled 1 PCI: 00:03.0: enabled 1 PCI: 00:13.0: enabled 1 PCI: 00:14.0: enabled 1 PCI: 00:15.0: enabled 1 PCI: 00:15.1: enabled 1 PCI: 00:15.2: enabled 1 PCI: 00:15.3: enabled 1 PCI: 00:15.4: enabled 0 PCI: 00:15.5: enabled 0 PCI: 00:15.6: enabled 0 PCI: 00:16.0: enabled 1 PCI: 00:16.1: enabled 0 PCI: 00:16.2: enabled 0 PCI: 00:16.3: enabled 0 PCI: 00:17.0: enabled 0 PCI: 00:19.0: enabled 0 PCI: 00:1b.0: enabled 0 PCI: 00:1c.0: enabled 0 PCI: 00:1c.1: enabled 0 PCI: 00:1c.2: enabled 1 PCI: 00:1c.3: enabled 0 PCI: 00:1c.4: enabled 0 PCI: 00:1c.5: enabled 0 PCI: 00:1d.0: enabled 0 PCI: 00:1e.0: enabled 0 PCI: 00:1f.0: enabled 1 PNP: 0c31.0: enabled 1 PCI: 00:1f.2: enabled 1 PCI: 00:1f.3: enabled 0 PCI: 00:1f.6: enabled 1 Compare with tree... Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 DOMAIN: 0000: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:02.0: enabled 1 PCI: 00:03.0: enabled 1 PCI: 00:13.0: enabled 1 PCI: 00:14.0: enabled 1 PCI: 00:15.0: enabled 1 PCI: 00:15.1: enabled 1 PCI: 00:15.2: enabled 1 PCI: 00:15.3: enabled 1 PCI: 00:15.4: enabled 0 PCI: 00:15.5: enabled 0 PCI: 00:15.6: enabled 0 PCI: 00:16.0: enabled 1 PCI: 00:16.1: enabled 0 PCI: 00:16.2: enabled 0 PCI: 00:16.3: enabled 0 PCI: 00:17.0: enabled 0 PCI: 00:19.0: enabled 0 PCI: 00:1b.0: enabled 0 PCI: 00:1c.0: enabled 0 PCI: 00:1c.1: enabled 0 PCI: 00:1c.2: enabled 1 PCI: 00:1c.3: enabled 0 PCI: 00:1c.4: enabled 0 PCI: 00:1c.5: enabled 0 PCI: 00:1d.0: enabled 0 PCI: 00:1e.0: enabled 0 PCI: 00:1f.0: enabled 1 PNP: 0c31.0: enabled 1 PCI: 00:1f.2: enabled 1 PCI: 00:1f.3: enabled 0 PCI: 00:1f.6: enabled 1 Root Device scanning... root_dev_scan_bus for Root Device CPU_CLUSTER: 0 enabled DOMAIN: 0000 enabled DOMAIN: 0000 scanning... PCI: pci_scan_bus for bus 00 PCI: 00:00.0 [8086/0000] ops PCI: 00:00.0 [8086/1604] enabled PCI: 00:02.0 [8086/0000] ops PCI: 00:02.0 [8086/1626] enabled PCI: 00:03.0 [8086/0000] ops PCI: 00:03.0 [8086/160c] enabled PCI: 00:13.0 [8086/0000] ops PCI: 00:13.0 [8086/9cb6] enabled PCI: 00:14.0 [8086/0000] ops PCI: 00:14.0 [8086/9cb1] enabled PCI: 00:15.0 [8086/0000] ops PCI: 00:15.0 [8086/9ce0] enabled PCI: 00:15.1 [8086/0000] ops PCI: 00:15.1 [8086/9ce1] enabled PCI: 00:15.2 [8086/0000] ops PCI: 00:15.2 [8086/9ce2] enabled PCI: 00:15.3 [8086/0000] ops PCI: 00:15.3 [8086/9ce5] enabled PCI: 00:15.4: Disabling device PCI: 00:15.5: Disabling device PCI: 00:15.6: Disabling device PCI: 00:16.0 [8086/0000] ops PCI: 00:16.0 [8086/9cba] enabled PCI: 00:16.1: Disabling device PCI: 00:16.2: Disabling device PCI: 00:16.3: Disabling device PCI: 00:17.0: Disabling device PCI: 00:19.0: Disabling device PCI: 00:1b.0 [8086/0000] ops HDA disabled, I/O buffers routed to ADSP PCI: 00:1b.0 [8086/9ca0] disabled PCI: 00:1c.0 [8086/0000] bus ops PCI: 00:1c.0 [8086/9c90] disabled PCI: 00:1c.1 [8086/0000] bus ops PCI: 00:1c.1 [8086/9c92] disabled PCI: 00:1c.2 [8086/0000] bus ops PCIe Root Port 3 ASPM is enabled PCI: 00:1c.2 [8086/9c94] enabled PCI: 00:1c.3 [8086/0000] bus ops PCI: 00:1c.3 [8086/9c96] disabled PCI: 00:1c.4 [8086/0000] bus ops PCI: 00:1c.4 [8086/9c98] disabled PCI: 00:1c.5 [8086/0000] bus ops PCI: 00:1c.0: Disabling device PCI: 00:1c.1: Disabling device PCI: 00:1c.3: Disabling device PCI: 00:1c.4: Disabling device PCI: 00:1c.4: Timeout waiting for 328h PCI: 00:1c.5: Disabling device PCI: 00:1c.5: Timeout waiting for 328h PCH: PCIe map 1c.2 -> 1c.0 PCH: PCIe map 1c.0 -> 1c.1 PCH: PCIe map 1c.1 -> 1c.2 PCH: RPFN 0x00543210 -> 0x00dcb0a9 PCI: 00:1c.5 [8086/9c9a] disabled PCI: 00:1e.0: Disabling device PCI: 00:1f.0 [8086/0000] bus ops PCI: 00:1f.0 [8086/9cc3] enabled PCI: 00:1f.2 [8086/0000] ops PCI: 00:1f.2 [8086/9c83] enabled PCI: 00:1f.3: Disabling device PCI: 00:1f.6 [8086/9ca4] enabled PCI: 00:1c.0 scanning... do_pci_scan_bridge for PCI: 00:1c.0 PCI: pci_scan_bus for bus 01 scan_bus: scanning of bus PCI: 00:1c.0 took 8121 usecs PCI: 00:1f.0 scanning... scan_lpc_bus for PCI: 00:1f.0 PNP: 0c31.0 enabled scan_lpc_bus for PCI: 00:1f.0 done scan_bus: scanning of bus PCI: 00:1f.0 took 9898 usecs scan_bus: scanning of bus DOMAIN: 0000 took 220433 usecs root_dev_scan_bus for Root Device done scan_bus: scanning of bus Root Device took 238194 usecs done BS: BS_DEV_ENUMERATE times (us): entry 5 run 412960 exit 4 found VGA at PCI: 00:02.0 Setting up VGA for PCI: 00:02.0 Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device Allocating resources... Reading resources... Root Device read_resources bus 0 link: 0 CPU_CLUSTER: 0 read_resources bus 0 link: 0 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done DOMAIN: 0000 read_resources bus 0 link: 0 mc_add_fixed_mmio_resources: Adding PCIEXBAR @ 60 0xe0000000-0xe3ffffff. mc_add_fixed_mmio_resources: Adding MCHBAR @ 48 0xfed10000-0xfed17fff. mc_add_fixed_mmio_resources: Adding DMIBAR @ 68 0xfed18000-0xfed18fff. mc_add_fixed_mmio_resources: Adding EPBAR @ 40 0xfed19000-0xfed19fff. mc_add_fixed_mmio_resources: Adding GDXCBAR @ 5420 0xfed84000-0xfed84fff. mc_add_fixed_mmio_resources: Adding EDRAMBAR @ 5408 0xfed80000-0xfed83fff. MC MAP: TOM: 0x200000000 MC MAP: TOUUD: 0x280000000 MC MAP: MESEG_BASE: 0x7ffff00000 MC MAP: MESEG_LIMIT: 0xfffff MC MAP: REMAP_BASE: 0x200000000 MC MAP: REMAP_LIMIT: 0x27fffffff MC MAP: TOLUD: 0x80000000 MC MAP: BGSM: 0x7d800000 MC MAP: BDSM: 0x7e000000 MC MAP: TESGMB: 0x7d000000 MC MAP: GGC: 0x1c1 PCI: 00:1c.0 read_resources bus 1 link: 0 PCI: 00:1c.0 read_resources bus 1 link: 0 done PCI: 00:1f.0 read_resources bus 0 link: 0 PNP: 0c31.0 missing read_resources PCI: 00:1f.0 read_resources bus 0 link: 0 done DOMAIN: 0000 read_resources bus 0 link: 0 done Root Device read_resources bus 0 link: 0 done Done reading resources. Show resources in subtree (Root Device)...After reading. Root Device child on link 0 CPU_CLUSTER: 0 CPU_CLUSTER: 0 child on link 0 APIC: 00 APIC: 00 DOMAIN: 0000 child on link 0 PCI: 00:00.0 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100 PCI: 00:00.0 PCI: 00:00.0 resource base e0000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index 60 PCI: 00:00.0 resource base fed10000 size 8000 align 0 gran 0 limit 0 flags f0000200 index 48 PCI: 00:00.0 resource base fed18000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 68 PCI: 00:00.0 resource base fed19000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 40 PCI: 00:00.0 resource base fed84000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 5420 PCI: 00:00.0 resource base fed80000 size 4000 align 0 gran 0 limit 0 flags f0000200 index 5408 PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 0 PCI: 00:00.0 resource base c0000 size 7cf40000 align 0 gran 0 limit 0 flags e0004200 index 1 PCI: 00:00.0 resource base 7d000000 size 800000 align 0 gran 0 limit 0 flags f0004200 index 2 PCI: 00:00.0 resource base 7d800000 size 2800000 align 0 gran 0 limit 0 flags f0000200 index 3 PCI: 00:00.0 resource base 100000000 size 180000000 align 0 gran 0 limit 0 flags e0004200 index 4 PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 5 PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 6 PCI: 00:02.0 PCI: 00:02.0 resource base 0 size 1000000 align 24 gran 24 limit ffffffffffffffff flags 201 index 10 PCI: 00:02.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffffffffffff flags 1201 index 18 PCI: 00:02.0 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 index 20 PCI: 00:03.0 PCI: 00:03.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10 PCI: 00:13.0 PCI: 00:13.0 resource base 0 size 100000 align 20 gran 20 limit ffffffff flags 200 index 10 PCI: 00:13.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 14 PCI: 00:14.0 PCI: 00:14.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10 PCI: 00:15.0 PCI: 00:15.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 PCI: 00:15.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 14 PCI: 00:15.1 PCI: 00:15.1 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 PCI: 00:15.1 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 14 PCI: 00:15.2 PCI: 00:15.2 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 PCI: 00:15.2 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 14 PCI: 00:15.3 PCI: 00:15.3 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 PCI: 00:15.3 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 14 PCI: 00:15.4 PCI: 00:15.5 PCI: 00:15.6 PCI: 00:16.0 PCI: 00:16.0 resource base 0 size 20 align 12 gran 5 limit ffffffffffffffff flags 201 index 10 PCI: 00:16.1 PCI: 00:16.2 PCI: 00:16.3 PCI: 00:17.0 PCI: 00:19.0 PCI: 00:1b.0 PCI: 00:1c.1 PCI: 00:1c.2 PCI: 00:1c.0 PCI: 00:1c.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 00:1c.3 PCI: 00:1c.4 PCI: 00:1c.5 PCI: 00:1d.0 PCI: 00:1e.0 PCI: 00:1f.0 child on link 0 PNP: 0c31.0 PCI: 00:1f.0 resource base fec00000 size 1400000 align 0 gran 0 limit 0 flags c0000200 index 31fe PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0000100 index 0 PCI: 00:1f.0 resource base 1400 size 400 align 0 gran 0 limit 0 flags c0000100 index 48 PCI: 00:1f.0 resource base 1000 size 100 align 0 gran 0 limit 0 flags c0000100 index 40 PNP: 0c31.0 PNP: 0c31.0 resource base a size 0 align 0 gran 0 limit 0 flags c0000400 index 70 PCI: 00:1f.2 PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10 PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14 PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18 PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c PCI: 00:1f.2 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 PCI: 00:1f.2 resource base 0 size 8000 align 15 gran 15 limit ffffffff flags 200 index 24 PCI: 00:1f.3 PCI: 00:1f.6 PCI: 00:1f.6 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10 DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff PCI: 00:1c.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff PCI: 00:1c.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done PCI: 00:02.0 20 * [0x0 - 0x3f] io PCI: 00:1f.2 20 * [0x40 - 0x5f] io PCI: 00:1f.2 10 * [0x60 - 0x67] io PCI: 00:1f.2 18 * [0x68 - 0x6f] io PCI: 00:1f.2 14 * [0x70 - 0x73] io PCI: 00:1f.2 1c * [0x74 - 0x77] io DOMAIN: 0000 io: base: 78 size: 78 align: 6 gran: 0 limit: ffff done DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff PCI: 00:1c.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 00:1c.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done PCI: 00:1c.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 00:1c.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done PCI: 00:02.0 18 * [0x0 - 0xfffffff] prefmem PCI: 00:02.0 10 * [0x10000000 - 0x10ffffff] mem PCI: 00:13.0 10 * [0x11000000 - 0x110fffff] mem PCI: 00:14.0 10 * [0x11100000 - 0x1110ffff] mem PCI: 00:1f.2 24 * [0x11110000 - 0x11117fff] mem PCI: 00:03.0 10 * [0x11118000 - 0x1111bfff] mem PCI: 00:13.0 14 * [0x1111c000 - 0x1111cfff] mem PCI: 00:15.0 10 * [0x1111d000 - 0x1111dfff] mem PCI: 00:15.0 14 * [0x1111e000 - 0x1111efff] mem PCI: 00:15.1 10 * [0x1111f000 - 0x1111ffff] mem PCI: 00:15.1 14 * [0x11120000 - 0x11120fff] mem PCI: 00:15.2 10 * [0x11121000 - 0x11121fff] mem PCI: 00:15.2 14 * [0x11122000 - 0x11122fff] mem PCI: 00:15.3 10 * [0x11123000 - 0x11123fff] mem PCI: 00:15.3 14 * [0x11124000 - 0x11124fff] mem PCI: 00:1f.6 10 * [0x11125000 - 0x11125fff] mem PCI: 00:16.0 10 * [0x11126000 - 0x1112601f] mem DOMAIN: 0000 mem: base: 11126020 size: 11126020 align: 28 gran: 0 limit: ffffffff done avoid_fixed_resources: DOMAIN: 0000 avoid_fixed_resources:@DOMAIN: 0000 10000000 limit 0000ffff avoid_fixed_resources:@DOMAIN: 0000 10000100 limit ffffffff constrain_resources: PCI: 00:00.0 60 base e0000000 limit e3ffffff mem (fixed) constrain_resources: PCI: 00:00.0 00 base 00000000 limit 0009ffff mem (fixed) constrain_resources: PCI: 00:00.0 01 base 000c0000 limit 7cffffff mem (fixed) constrain_resources: PCI: 00:00.0 02 base 7d000000 limit 7d7fffff mem (fixed) constrain_resources: PCI: 00:00.0 03 base 7d800000 limit 7fffffff mem (fixed) constrain_resources: PCI: 00:1f.0 00 base 00000000 limit 00000fff io (fixed) constrain_resources: PCI: 00:1f.0 48 base 00001400 limit 000017ff io (fixed) skipping PNP: 0c31.0@70 fixed resource, size=0! avoid_fixed_resources:@DOMAIN: 0000 10000000 base 00001800 limit 0000ffff avoid_fixed_resources:@DOMAIN: 0000 10000100 base c0000000 limit dfffffff Setting resources... DOMAIN: 0000 io: base:1800 size:78 align:6 gran:0 limit:ffff PCI: 00:02.0 20 * [0x1800 - 0x183f] io PCI: 00:1f.2 20 * [0x1840 - 0x185f] io PCI: 00:1f.2 10 * [0x1860 - 0x1867] io PCI: 00:1f.2 18 * [0x1868 - 0x186f] io PCI: 00:1f.2 14 * [0x1870 - 0x1873] io PCI: 00:1f.2 1c * [0x1874 - 0x1877] io DOMAIN: 0000 io: next_base: 1878 size: 78 align: 6 gran: 0 done PCI: 00:1c.0 io: base:ffff size:0 align:12 gran:12 limit:ffff PCI: 00:1c.0 io: next_base: ffff size: 0 align: 12 gran: 12 done DOMAIN: 0000 mem: base:c0000000 size:11126020 align:28 gran:0 limit:dfffffff PCI: 00:02.0 18 * [0xc0000000 - 0xcfffffff] prefmem PCI: 00:02.0 10 * [0xd0000000 - 0xd0ffffff] mem PCI: 00:13.0 10 * [0xd1000000 - 0xd10fffff] mem PCI: 00:14.0 10 * [0xd1100000 - 0xd110ffff] mem PCI: 00:1f.2 24 * [0xd1110000 - 0xd1117fff] mem PCI: 00:03.0 10 * [0xd1118000 - 0xd111bfff] mem PCI: 00:13.0 14 * [0xd111c000 - 0xd111cfff] mem PCI: 00:15.0 10 * [0xd111d000 - 0xd111dfff] mem PCI: 00:15.0 14 * [0xd111e000 - 0xd111efff] mem PCI: 00:15.1 10 * [0xd111f000 - 0xd111ffff] mem PCI: 00:15.1 14 * [0xd1120000 - 0xd1120fff] mem PCI: 00:15.2 10 * [0xd1121000 - 0xd1121fff] mem PCI: 00:15.2 14 * [0xd1122000 - 0xd1122fff] mem PCI: 00:15.3 10 * [0xd1123000 - 0xd1123fff] mem PCI: 00:15.3 14 * [0xd1124000 - 0xd1124fff] mem PCI: 00:1f.6 10 * [0xd1125000 - 0xd1125fff] mem PCI: 00:16.0 10 * [0xd1126000 - 0xd112601f] mem DOMAIN: 0000 mem: next_base: d1126020 size: 11126020 align: 28 gran: 0 done PCI: 00:1c.0 prefmem: base:dfffffff size:0 align:20 gran:20 limit:dfffffff PCI: 00:1c.0 prefmem: next_base: dfffffff size: 0 align: 20 gran: 20 done PCI: 00:1c.0 mem: base:dfffffff size:0 align:20 gran:20 limit:dfffffff PCI: 00:1c.0 mem: next_base: dfffffff size: 0 align: 20 gran: 20 done Root Device assign_resources, bus 0 link: 0 DOMAIN: 0000 assign_resources, bus 0 link: 0 PCI: 00:02.0 10 <- [0x00d0000000 - 0x00d0ffffff] size 0x01000000 gran 0x18 mem64 PCI: 00:02.0 18 <- [0x00c0000000 - 0x00cfffffff] size 0x10000000 gran 0x1c prefmem64 PCI: 00:02.0 20 <- [0x0000001800 - 0x000000183f] size 0x00000040 gran 0x06 io PCI: 00:03.0 10 <- [0x00d1118000 - 0x00d111bfff] size 0x00004000 gran 0x0e mem64 PCI: 00:13.0 10 <- [0x00d1000000 - 0x00d10fffff] size 0x00100000 gran 0x14 mem PCI: 00:13.0 14 <- [0x00d111c000 - 0x00d111cfff] size 0x00001000 gran 0x0c mem PCI: 00:14.0 10 <- [0x00d1100000 - 0x00d110ffff] size 0x00010000 gran 0x10 mem64 PCI: 00:15.0 10 <- [0x00d111d000 - 0x00d111dfff] size 0x00001000 gran 0x0c mem PCI: 00:15.0 14 <- [0x00d111e000 - 0x00d111efff] size 0x00001000 gran 0x0c mem PCI: 00:15.1 10 <- [0x00d111f000 - 0x00d111ffff] size 0x00001000 gran 0x0c mem PCI: 00:15.1 14 <- [0x00d1120000 - 0x00d1120fff] size 0x00001000 gran 0x0c mem PCI: 00:15.2 10 <- [0x00d1121000 - 0x00d1121fff] size 0x00001000 gran 0x0c mem PCI: 00:15.2 14 <- [0x00d1122000 - 0x00d1122fff] size 0x00001000 gran 0x0c mem PCI: 00:15.3 10 <- [0x00d1123000 - 0x00d1123fff] size 0x00001000 gran 0x0c mem PCI: 00:15.3 14 <- [0x00d1124000 - 0x00d1124fff] size 0x00001000 gran 0x0c mem PCI: 00:16.0 10 <- [0x00d1126000 - 0x00d112601f] size 0x00000020 gran 0x05 mem64 PCI: 00:1c.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 01 io PCI: 00:1c.0 24 <- [0x00dfffffff - 0x00dffffffe] size 0x00000000 gran 0x14 bus 01 prefmem PCI: 00:1c.0 20 <- [0x00dfffffff - 0x00dffffffe] size 0x00000000 gran 0x14 bus 01 mem PCI: 00:1f.0 assign_resources, bus 0 link: 0 PNP: 0c31.0 missing set_resources PCI: 00:1f.0 assign_resources, bus 0 link: 0 PCI: 00:1f.2 10 <- [0x0000001860 - 0x0000001867] size 0x00000008 gran 0x03 io PCI: 00:1f.2 14 <- [0x0000001870 - 0x0000001873] size 0x00000004 gran 0x02 io PCI: 00:1f.2 18 <- [0x0000001868 - 0x000000186f] size 0x00000008 gran 0x03 io PCI: 00:1f.2 1c <- [0x0000001874 - 0x0000001877] size 0x00000004 gran 0x02 io PCI: 00:1f.2 20 <- [0x0000001840 - 0x000000185f] size 0x00000020 gran 0x05 io PCI: 00:1f.2 24 <- [0x00d1110000 - 0x00d1117fff] size 0x00008000 gran 0x0f mem PCI: 00:1f.6 10 <- [0x00d1125000 - 0x00d1125fff] size 0x00001000 gran 0x0c mem64 DOMAIN: 0000 assign_resources, bus 0 link: 0 Root Device assign_resources, bus 0 link: 0 Done setting resources. Show resources in subtree (Root Device)...After assigning values. Root Device child on link 0 CPU_CLUSTER: 0 CPU_CLUSTER: 0 child on link 0 APIC: 00 APIC: 00 DOMAIN: 0000 child on link 0 PCI: 00:00.0 DOMAIN: 0000 resource base 1800 size 78 align 6 gran 0 limit ffff flags 40040100 index 10000000 DOMAIN: 0000 resource base c0000000 size 11126020 align 28 gran 0 limit dfffffff flags 40040200 index 10000100 PCI: 00:00.0 PCI: 00:00.0 resource base e0000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index 60 PCI: 00:00.0 resource base fed10000 size 8000 align 0 gran 0 limit 0 flags f0000200 index 48 PCI: 00:00.0 resource base fed18000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 68 PCI: 00:00.0 resource base fed19000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 40 PCI: 00:00.0 resource base fed84000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 5420 PCI: 00:00.0 resource base fed80000 size 4000 align 0 gran 0 limit 0 flags f0000200 index 5408 PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 0 PCI: 00:00.0 resource base c0000 size 7cf40000 align 0 gran 0 limit 0 flags e0004200 index 1 PCI: 00:00.0 resource base 7d000000 size 800000 align 0 gran 0 limit 0 flags f0004200 index 2 PCI: 00:00.0 resource base 7d800000 size 2800000 align 0 gran 0 limit 0 flags f0000200 index 3 PCI: 00:00.0 resource base 100000000 size 180000000 align 0 gran 0 limit 0 flags e0004200 index 4 PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 5 PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 6 PCI: 00:02.0 PCI: 00:02.0 resource base d0000000 size 1000000 align 24 gran 24 limit d0ffffff flags 60000201 index 10 PCI: 00:02.0 resource base c0000000 size 10000000 align 28 gran 28 limit cfffffff flags 60001201 index 18 PCI: 00:02.0 resource base 1800 size 40 align 6 gran 6 limit 183f flags 60000100 index 20 PCI: 00:03.0 PCI: 00:03.0 resource base d1118000 size 4000 align 14 gran 14 limit d111bfff flags 60000201 index 10 PCI: 00:13.0 PCI: 00:13.0 resource base d1000000 size 100000 align 20 gran 20 limit d10fffff flags 60000200 index 10 PCI: 00:13.0 resource base d111c000 size 1000 align 12 gran 12 limit d111cfff flags 60000200 index 14 PCI: 00:14.0 PCI: 00:14.0 resource base d1100000 size 10000 align 16 gran 16 limit d110ffff flags 60000201 index 10 PCI: 00:15.0 PCI: 00:15.0 resource base d111d000 size 1000 align 12 gran 12 limit d111dfff flags 60000200 index 10 PCI: 00:15.0 resource base d111e000 size 1000 align 12 gran 12 limit d111efff flags 60000200 index 14 PCI: 00:15.1 PCI: 00:15.1 resource base d111f000 size 1000 align 12 gran 12 limit d111ffff flags 60000200 index 10 PCI: 00:15.1 resource base d1120000 size 1000 align 12 gran 12 limit d1120fff flags 60000200 index 14 PCI: 00:15.2 PCI: 00:15.2 resource base d1121000 size 1000 align 12 gran 12 limit d1121fff flags 60000200 index 10 PCI: 00:15.2 resource base d1122000 size 1000 align 12 gran 12 limit d1122fff flags 60000200 index 14 PCI: 00:15.3 PCI: 00:15.3 resource base d1123000 size 1000 align 12 gran 12 limit d1123fff flags 60000200 index 10 PCI: 00:15.3 resource base d1124000 size 1000 align 12 gran 12 limit d1124fff flags 60000200 index 14 PCI: 00:15.4 PCI: 00:15.5 PCI: 00:15.6 PCI: 00:16.0 PCI: 00:16.0 resource base d1126000 size 20 align 12 gran 5 limit d112601f flags 60000201 index 10 PCI: 00:16.1 PCI: 00:16.2 PCI: 00:16.3 PCI: 00:17.0 PCI: 00:19.0 PCI: 00:1b.0 PCI: 00:1c.1 PCI: 00:1c.2 PCI: 00:1c.0 PCI: 00:1c.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c PCI: 00:1c.0 resource base dfffffff size 0 align 20 gran 20 limit dfffffff flags 60081202 index 24 PCI: 00:1c.0 resource base dfffffff size 0 align 20 gran 20 limit dfffffff flags 60080202 index 20 PCI: 00:1c.3 PCI: 00:1c.4 PCI: 00:1c.5 PCI: 00:1d.0 PCI: 00:1e.0 PCI: 00:1f.0 child on link 0 PNP: 0c31.0 PCI: 00:1f.0 resource base fec00000 size 1400000 align 0 gran 0 limit 0 flags c0000200 index 31fe PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0000100 index 0 PCI: 00:1f.0 resource base 1400 size 400 align 0 gran 0 limit 0 flags c0000100 index 48 PCI: 00:1f.0 resource base 1000 size 100 align 0 gran 0 limit 0 flags c0000100 index 40 PNP: 0c31.0 PNP: 0c31.0 resource base a size 0 align 0 gran 0 limit 0 flags c0000400 index 70 PCI: 00:1f.2 PCI: 00:1f.2 resource base 1860 size 8 align 3 gran 3 limit 1867 flags 60000100 index 10 PCI: 00:1f.2 resource base 1870 size 4 align 2 gran 2 limit 1873 flags 60000100 index 14 PCI: 00:1f.2 resource base 1868 size 8 align 3 gran 3 limit 186f flags 60000100 index 18 PCI: 00:1f.2 resource base 1874 size 4 align 2 gran 2 limit 1877 flags 60000100 index 1c PCI: 00:1f.2 resource base 1840 size 20 align 5 gran 5 limit 185f flags 60000100 index 20 PCI: 00:1f.2 resource base d1110000 size 8000 align 15 gran 15 limit d1117fff flags 60000200 index 24 PCI: 00:1f.3 PCI: 00:1f.6 PCI: 00:1f.6 resource base d1125000 size 1000 align 12 gran 12 limit d1125fff flags 60000201 index 10 Done allocating resources. BS: BS_DEV_RESOURCES times (us): entry 4 run 1651122 exit 4 Enabling resources... PCI: 00:00.0 subsystem <- 8086/1604 PCI: 00:00.0 cmd <- 06 PCI: 00:02.0 subsystem <- 8086/1626 PCI: 00:02.0 cmd <- 07 PCI: 00:03.0 subsystem <- 8086/160c PCI: 00:03.0 cmd <- 07 PCI: 00:13.0 subsystem <- 8086/9cb6 PCI: 00:13.0 cmd <- 107 PCI: 00:14.0 subsystem <- 8086/9cb1 PCI: 00:14.0 cmd <- 107 PCI: 00:15.0 subsystem <- 8086/9ce0 PCI: 00:15.0 cmd <- 107 PCI: 00:15.1 subsystem <- 8086/9ce1 PCI: 00:15.1 cmd <- 107 PCI: 00:15.2 subsystem <- 8086/9ce2 PCI: 00:15.2 cmd <- 107 PCI: 00:15.3 subsystem <- 8086/9ce5 PCI: 00:15.3 cmd <- 107 PCI: 00:16.0 subsystem <- 8086/9cba PCI: 00:16.0 cmd <- 07 PCI: 00:1c.0 bridge ctrl <- 0003 PCI: 00:1c.0 subsystem <- 8086/9c94 PCI: 00:1c.0 cmd <- 05 PCI: 00:1f.0 subsystem <- 8086/9cc3 PCI: 00:1f.0 cmd <- 107 PCI: 00:1f.2 subsystem <- 8086/9c83 PCI: 00:1f.2 cmd <- 107 PCI: 00:1f.6 subsystem <- 8086/9ca4 PCI: 00:1f.6 cmd <- 107 done. BS: BS_DEV_ENABLE times (us): entry 5 run 80526 exit 4 Initializing devices... Root Device init ... mainboard_init mainboard_ec_init Chrome EC: Set WAKE mask to 0x00000000 Missing Chromium EC memory map. Root Device init finished in 11316 usecs CPU_CLUSTER: 0 init ... MTRR: Physical address space: 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 0x00000000000c0000 - 0x000000007d800000 size 0x7d740000 type 6 0x000000007d800000 - 0x00000000c0000000 size 0x42800000 type 0 0x00000000c0000000 - 0x00000000d0000000 size 0x10000000 type 1 0x00000000d0000000 - 0x0000000100000000 size 0x30000000 type 0 0x0000000100000000 - 0x0000000280000000 size 0x180000000 type 6 MTRR: Fixed MSR 0x250 0x0606060606060606 MTRR: Fixed MSR 0x258 0x0606060606060606 MTRR: Fixed MSR 0x259 0x0000000000000000 MTRR: Fixed MSR 0x268 0x0606060606060606 MTRR: Fixed MSR 0x269 0x0606060606060606 MTRR: Fixed MSR 0x26a 0x0606060606060606 MTRR: Fixed MSR 0x26b 0x0606060606060606 MTRR: Fixed MSR 0x26c 0x0606060606060606 MTRR: Fixed MSR 0x26d 0x0606060606060606 MTRR: Fixed MSR 0x26e 0x0606060606060606 MTRR: Fixed MSR 0x26f 0x0606060606060606 call enable_fixed_mtrr() CPU physical address size: 39 bits MTRR: default type WB/UC MTRR counts: 6/6. MTRR: UC selected as default type. MTRR: 0 base 0x0000000000000000 mask 0x0000007f80000000 type 6 MTRR: 1 base 0x000000007d800000 mask 0x0000007fff800000 type 0 MTRR: 2 base 0x000000007e000000 mask 0x0000007ffe000000 type 0 MTRR: 3 base 0x00000000c0000000 mask 0x0000007ff0000000 type 1 MTRR: 4 base 0x0000000100000000 mask 0x0000007f00000000 type 6 MTRR: 5 base 0x0000000200000000 mask 0x0000007f80000000 type 6 MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled Initializing VR config. PCODE: 24MHz BLCK calibration response: 0 PCODE: 24MHz BLCK calibration value: 0x850609d3 PCH Power: PCODE Levels 0x3f245102 0x0058f38a CPU has 2 cores, 4 threads enabled. Setting up SMI for CPU Will perform SMM setup. CBFS: 'Master Header Locator' located CBFS at [300100:3fffc0) CBFS: Locating 'cpu_microcode_blob.bin' CBFS: Found @ offset af40 size 11440 microcode: sig=0x306d4 pf=0x40 revision=0x1f CPU: Intel(R) Core(TM) i7-5650U CPU @ 2.20GHz. Loading module at 00030000 with entry 00030000. filesize: 0x130 memsize: 0x130 Processing 16 relocs. Offset value of 0x00030000 Attempting to start 3 APs Waiting for 10ms after sending INIT. Waiting for 1st SIPI to complete...AP: slot 1 apic_id 1. AP: slot 3 apic_id 3. AP: slot 2 apic_id 2. done. Waiting for 2nd SIPI to complete...done. Loading module at 00038000 with entry 00038000. filesize: 0x1a8 memsize: 0x1a8 Processing 12 relocs. Offset value of 0x00038000 SMM Module: stub loaded at 00038000. Will call 7cfaee31(00000000) Installing SMM handler to 0x7d000000 Loading module at 7d010000 with entry 7d010070. filesize: 0xe48 memsize: 0x4e68 Processing 35 relocs. Offset value of 0x7d010000 Loading module at 7d008000 with entry 7d008000. filesize: 0x1a8 memsize: 0x1a8 Processing 12 relocs. Offset value of 0x7d008000 SMM Module: placing jmp sequence at 7d007c00 rel16 0x03fd SMM Module: placing jmp sequence at 7d007800 rel16 0x07fd SMM Module: placing jmp sequence at 7d007400 rel16 0x0bfd SMM Module: stub loaded at 7d008000. Will call 7d010070(00000000) Initializing Southbridge SMI... ... pmbase = 0x1000 SMI_STS: TCO PM1 PM1_STS: TMROF New SMBASE 0x7d000000 In relocation handler: CPU 0 New SMBASE=0x7d000000 IEDBASE=0x7d400000 Writing SMRR. base = 0x7d000006, mask=0xff800800 Relocation complete. New SMBASE 0x7cfffc00 In relocation handler: CPU 1 New SMBASE=0x7cfffc00 IEDBASE=0x7d400000 Writing SMRR. base = 0x7d000006, mask=0xff800800 Relocation complete. New SMBASE 0x7cfff400 In relocation handler: CPU 3 New SMBASE=0x7cfff400 IEDBASE=0x7d400000 Writing SMRR. base = 0x7d000006, mask=0xff800800 Relocation complete. New SMBASE 0x7cfff800 In relocation handler: CPU 2 New SMBASE=0x7cfff800 IEDBASE=0x7d400000 Writing SMRR. base = 0x7d000006, mask=0xff800800 Relocation complete. Initializing CPU #0 CPU: vendor Intel device 306d4 CPU: family 06, model 3d, stepping 04 Setting up local APIC... apic_id: 0x00 done. VMX status: disabled, unlocked cpu: energy policy set to 6 Turbo is available but hidden Turbo has been enabled CPU #0 initialized Initializing CPU #1 Initializing CPU #2 Initializing CPU #3 CPU: vendor Intel device 306d4 CPU: family 06, model 3d, stepping 04 CPU: vendor Intel device 306d4 CPU: family 06, model 3d, stepping 04 Setting up local APIC...Setting up local APIC... apic_id: 0x02 done. apic_id: 0x03 done. VMX status: disabled, unlocked VMX status: disabled, unlocked cpu: energy policy set to 6 cpu: energy policy set to 6 CPU #2 initialized CPU #3 initialized CPU: vendor Intel device 306d4 CPU: family 06, model 3d, stepping 04 Setting up local APIC... apic_id: 0x01 done. VMX status: disabled, unlocked cpu: energy policy set to 6 CPU #1 initialized cpu: frequency set to 3200 Enabling SMIs. Locking SMM. CPU_CLUSTER: 0 init finished in 443935 usecs PCI: 00:00.0 init ... Set BIOS_RESET_CPL CPU TDP: 15 Watts PCI: 00:00.0 init finished in 6390 usecs PCI: 00:02.0 init ... CBFS: 'Master Header Locator' located CBFS at [300100:3fffc0) CBFS: Locating 'pci8086,1626.rom' CBFS: 'pci8086,1626.rom' not found. CBFS: 'Master Header Locator' located CBFS at [300100:3fffc0) CBFS: Locating 'pci8086,0406.rom' CBFS: Found @ offset 47900 size 10000 In CBFS, ROM address for PCI: 00:02.0 = fff47a48 PCI expansion ROM, signature 0xaa55, INIT size 0x10000, data ptr 0x0040 PCI ROM image, vendor ID 8086, device ID 0406, PCI ROM image, Class Code 030000, Code Type 00 Copying VGA ROM Image from fff47a48 to 0xc0000, 0x10000 bytes pci_dev_init, 2 Real mode stub @00000600: 867 bytes Calling Option ROM... intel_vga_int15_handler: AX=5f35 BX=c000 CX=0002 DX=03da ... Option ROM returned. VGA Option ROM was run PCI: 00:02.0 init finished in 1309735 usecs PCI: 00:03.0 init ... Mini-HD: base = d1118000 HDA: Initializing codec #0 HDA: codec viddid: 80862808 HDA: No verb table entry found PCI: 00:03.0 init finished in 14983 usecs PCI: 00:13.0 init ... ADSP: Enable ACPI Mode IRQ3 PCI: 00:13.0 init finished in 4616 usecs PCI: 00:14.0 init ... PCI: 00:14.0 init finished in 1999 usecs PCI: 00:15.0 init ... Initializing Serial IO device PCI: 00:15.0 init finished in 4769 usecs PCI: 00:15.1 init ... Initializing Serial IO device PCI: 00:15.1 init finished in 4718 usecs PCI: 00:15.2 init ... Initializing Serial IO device PCI: 00:15.2 init finished in 4717 usecs PCI: 00:15.3 init ... Initializing Serial IO device PCI: 00:15.3 init finished in 4716 usecs PCI: 00:16.0 init ... ME: FW Partition Table : OK ME: Bringup Loader Failure : NO ME: Firmware Init Complete : NO ME: Manufacturing Mode : YES ME: Boot Options Present : NO ME: Update In Progress : NO ME: Current Working State : Initializing ME: Current Operation State : Bring up ME: Current Operation Mode : Security Override via Jumper ME: Error Code : Debug Failure ME: Progress Phase : BUP Phase ME: Power Management Event : Pseudo-global reset ME: Progress Phase State : 0x7b intel_me_path: mbp is not ready! ME: BIOS path: Error ME: MBP not ready PCI: 00:16.0 init finished in 53821 usecs PCI: 00:1c.0 init ... Initializing PCH PCIe bridge. PCI: 00:1c.0 init finished in 4689 usecs PCI: 00:1f.0 init ... rtc_failed = 0x4 RTC Init RTC: Clear requested zeroing cmos IOAPIC: Initializing IOAPIC at 0xfec00000 IOAPIC: Bootstrap Processor Local APIC = 0x00 IOAPIC: ID = 0x02 IOAPIC: Dumping registers reg 0x0000: 0x02000000 reg 0x0001: 0x00170020 reg 0x0002: 0x00000000 Set power off after power failure. ________________________________ From: Matt DeVillier <matt.devillier(a)gmail.com> Sent: Monday, July 31, 2017 7:06 PM To: Zheng Bao Cc: Nico Huber; coreboot(a)coreboot.org; stefan.reinauer(a)coreboot.org Subject: Re: [coreboot] Broadwell-U hangs at VGA init you want to extract the refcode blob as so: cbfstool shellball.rom extract -r BOOT_STUB -n fallback/refcode -f refcode.elf -m x86 then add it into your build On Mon, Jul 31, 2017 at 8:43 AM, Zheng Bao <fishbaoz(a)hotmail.com<mailto:fishbaoz@hotmail.com>> wrote: Thanks. That really helps. About the REFCODE_BLOB, the BLOB I extracted from ball-rom is BIN, instead of ELF which is required by current CBFS and rmodule in source. (And revision in ball-rom is not in main tree of repository.) Any idea to get REFCODE_BLOB? Thanks. Zheng ________________________________ From: Nico Huber <nico.huber(a)secunet.com<mailto:nico.huber@secunet.com>> Sent: Monday, July 31, 2017 10:52 AM To: Zheng Bao; coreboot(a)coreboot.org<mailto:coreboot@coreboot.org>; Matt DeVillier; stefan.reinauer(a)coreboot.org<mailto:stefan.reinauer@coreboot.org> Subject: Re: [coreboot] Broadwell-U hangs at VGA init Hi Zheng, On 30.07.2017 16:13, Zheng Bao wrote: > I have got the mrc.bin and mem init has got passed. > Now the new problem is that it hangs at VGA init. > > static void igd_setup_panel(struct device *dev) > { > config_t *conf = dev->chip_info; > u32 reg32; > > /* Setup Digital Port Hotplug */ > reg32 = gtt_read(PCH_PORT_HOTPLUG); <------- It hangs here. > if (!reg32) { > reg32 = (conf->gpu_dp_b_hotplug & 0x7) << 2; > reg32 |= (conf->gpu_dp_c_hotplug & 0x7) << 10; > reg32 |= (conf->gpu_dp_d_hotplug & 0x7) << 18; > gtt_write(PCH_PORT_HOTPLUG, reg32); > } > > It turns out as soon as i access VGA bar0+0xc4030, it hangs. > while accessing bar0 + 0xa00a is ok. sounds like the PCH part of the display engine isn't operational (pro- bably not all, but most register offsets with bit 19 set reside in the PCH). There are few steps to enable it [1], yet the Broadwell port seems to rely on the blob to do it. The datasheet [2] suggests that the same settings should be done for Broadwell too, but I can't find it in the source. So that leads to the conclusion: You forgot to add the second blob (HAVE_REFCODE_BLOB, it's BS, it's annoying, but you need it). That publicly documented settings move from the open source code into blobs is a very bad sign, IMO. Now, anybody tell me again, that things with Intel are getting better and they might become more open (the sta- tistics seem to say the opposite: the blobs get bigger, weirder, take over more responsibilities _and_ do a lot of stuff we already had open source for earlier platforms). Nico [1] src/southbridge/intel/lynxpoint/lpc.c:725 [2] Intel Document Number: 330837

1 0

New Defects reported by Coverity Scan for coreboot
by scan-admin＠coverity.com Aug. 1, 2017

Aug. 1, 2017

Hi, Please find the latest report on new defect(s) introduced to coreboot found with Coverity Scan. 3 new defect(s) introduced to coreboot found with Coverity Scan. New defect(s) Reported-by: Coverity Scan Showing 3 of 3 defect(s) ** CID 1378783: Control flow issues (NO_EFFECT) /3rdparty/arm-trusted-firmware/plat/compat/plat_topology_compat.c: 147 in plat_get_power_domain_tree_desc() ________________________________________________________________________________________________________ *** CID 1378783: Control flow issues (NO_EFFECT) /3rdparty/arm-trusted-firmware/plat/compat/plat_topology_compat.c: 147 in plat_get_power_domain_tree_desc() 141 142 /* 143 * We assume that the platform allocates affinity instance ids from 144 * 0 onwards at each affinity level in the mpidr. FIRST_MPIDR = 0.0.0.0 145 */ 146 affmap_idx = 0; >>> CID 1378783: Control flow issues (NO_EFFECT) >>> "afflvl" is converted to an unsigned type because it's compared to an unsigned constant. 147 for (afflvl = PLATFORM_MAX_AFFLVL; afflvl >= MPIDR_AFFLVL0; afflvl--) { 148 affmap_idx = init_pwr_domain_tree_desc(FIRST_MPIDR, 149 affmap_idx, 150 PLATFORM_MAX_AFFLVL, 151 afflvl); 152 } ** CID 1378782: Integer handling issues (NO_EFFECT) /3rdparty/arm-trusted-firmware/lib/cpus/errata_report.c: 75 in errata_print_msg() ________________________________________________________________________________________________________ *** CID 1378782: Integer handling issues (NO_EFFECT) /3rdparty/arm-trusted-firmware/lib/cpus/errata_report.c: 75 in errata_print_msg() 69 [ERRATA_MISSING] = "missing!" 70 }; 71 static const char *const __unused bl_str = BL_STRING; 72 const char *msg __unused; 73 74 >>> CID 1378782: Integer handling issues (NO_EFFECT) >>> This greater-than-or-equal-to-zero comparison of an unsigned value is always true. "status >= 0U". 75 assert(status >= 0 && status < ARRAY_SIZE(errata_status_str)); 76 assert(cpu); 77 assert(id); 78 79 msg = errata_status_str[status]; 80 ** CID 1378781: Integer handling issues (NO_EFFECT) /3rdparty/arm-trusted-firmware/lib/xlat_tables/xlat_tables_common.c: 314 in init_xlation_table_inner() ________________________________________________________________________________________________________ *** CID 1378781: Integer handling issues (NO_EFFECT) /3rdparty/arm-trusted-firmware/lib/xlat_tables/xlat_tables_common.c: 314 in init_xlation_table_inner() 308 309 static mmap_region_t *init_xlation_table_inner(mmap_region_t *mm, 310 uintptr_t base_va, 311 uint64_t *table, 312 int level) 313 { >>> CID 1378781: Integer handling issues (NO_EFFECT) >>> "level" is converted to an unsigned type because it's compared to an unsigned constant. 314 assert(level >= XLAT_TABLE_LEVEL_MIN && level <= XLAT_TABLE_LEVEL_MAX); 315 316 unsigned int level_size_shift = 317 L0_XLAT_ADDRESS_SHIFT - level * XLAT_TABLE_ENTRIES_SHIFT; 318 u_register_t level_size = (u_register_t)1 << level_size_shift; 319 u_register_t level_index_mask = ________________________________________________________________________________________________________ To view the defects in Coverity Scan visit, https://u2389337.ct.sendgrid.net/wf/click?upn=08onrYu34A-2BWcWUl-2F-2BfV0V0… To manage Coverity Scan email notifications for "coreboot(a)coreboot.org", click https://u2389337.ct.sendgrid.net/wf/click?upn=08onrYu34A-2BWcWUl-2F-2BfV0V0…

1 0