Your branch is up-to-date with 'origin/master'.
Deleted branch coreboot (was 7759d3a).
Branch coreboot set up to track remote branch master from origin.
Switched to a new branch 'coreboot'
CONFIG SeaBIOS origin/master
Error: File ./.seabiosconfig does not exist
make: *** [Makefile:48: config] Error 1
make: *** [payloads/external/Makefile.inc:72: seabios] Ошибка 2
But file exist in root coreboot directory. What is wrong?
29.06.2017 18:40, Martin Roth пишет:
> There are numerous places in shell scripts where '~' doesn't expand to
> match $HOME. I'd recommend putting the config in the coreboot
> directory and setting the config file to './.seabiosconfig'.
> If you really want it in your home directory, you can use
> On Thu, Jun 29, 2017 at 2:16 AM, Rostislav Okulov via coreboot
> <coreboot(a)coreboot.org <mailto:email@example.com>> wrote:
> I made my own seabios config file (.seabiosconfig) and put it in
> root coreboot directory. Add it in configuration like this
> CONFIG_PAYLOAD_CONFIGFILE="~/coreboot/.seabiosconfig" Next I do
> ~/coreboot> make to build coreboot but .seabiosconfig file skipped
> by make script and default file used instead
> How to properly add my custom seabios config file?
> coreboot mailing list: coreboot(a)coreboot.org
On 30.06.2017 06:25, ron minnich wrote:
> there's something I am certain I don't understand about SMM on intel
> The question is pretty simple. Consider a system with a recent intel
> chipset and flash. Is there some special secret sauce that disables writing
> to flash unless in SMM and if so, what is it?
it's a bit in the SPI configuration that Intel encourages everybody to
set (to give SMM a bigger attack surface and make the platform overall
less secure, I suppose?).
> Thanks to anyone who can point me to chapter and verse of a data sheet.
Search for BIOS_CNTL / SMM_BWP in your PCH datasheet or (BIOS_SPI_BC /
EISS from Skylake/100 series on).
there's something I am certain I don't understand about SMM on intel
The question is pretty simple. Consider a system with a recent intel
chipset and flash. Is there some special secret sauce that disables writing
to flash unless in SMM and if so, what is it?
Thanks to anyone who can point me to chapter and verse of a data sheet.
I made my own seabios config file (.seabiosconfig) and put it in root coreboot directory. Add it in configuration like this CONFIG_PAYLOAD_CONFIGFILE="~/coreboot/.seabiosconfig" Next I do ~/coreboot> make to build coreboot but .seabiosconfig file skipped by make script and default file used instead (/coreboot/payloads/external/SeaBIOS/seabios/.config)
How to properly add my custom seabios config file?
Sorry, my last answer was very short.
As M2N-E has a RS232 port, I am using cutecom on another computer connected through RS232/serial/com port.
You could use a USB/RS232 too.
De : Mike Banon <mikebdp2(a)gmail.com>
Envoyé : mercredi 28 juin 2017 14:08
À : Martin A
Objet : Re: [coreboot] Asus M2N-E
I just was curious about how the coreboot debugging process looks like, my experience is too small in this field. Please tell, with what hardware tools you are using a cutecom software?
^^^ sadly Ajays NET20DC is end-of-life and AMIDebug Rx is way too expensive (don't remember if it costs $500 or $5000, still a lot of money)
Please tell, are you using any of these devices? Or you made your own DIY dongle using this manual:
What your coreboot debugging setup looks like, in addition to cutecom?
wish good luck to your projects
On Mon, Jun 5, 2017 at 10:24 PM, Martin A <tintinsansmilou(a)hotmail.com<mailto:firstname.lastname@example.org>> wrote:
I use Cutecom.
De : Mike Banon <mikebdp2(a)gmail.com<mailto:email@example.com>>
Envoyé : lundi 5 juin 2017 17:03
À : Martin A
Objet : Re: [coreboot] Asus M2N-E
Hi Martin! Please tell: what tools are you using to receive this coreboot booting log?
On Wed, May 24, 2017 at 12:14 AM, Martin A <tintinsansmilou(a)hotmail.com<mailto:firstname.lastname@example.org>> wrote:
Thanks a lot for your help, really appreciate.
I tried try with a dual core Athlon 64 X2 and the boot log is an exact copy of the Opteron's.
So it has something to do with the mainboard.
Hope Uwe Hermann see this.
De : Timothy Pearson <tpearson(a)raptorengineering.com<mailto:email@example.com>>
Envoyé : mardi 23 mai 2017 19:56
À : Martin A
Cc : coreboot(a)coreboot.org<mailto:firstname.lastname@example.org>
Objet : Re: [coreboot] Asus M2N-E
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On 05/23/2017 03:37 AM, Martin A wrote:
> Sorry, here is the "not so perfect" boot log.
> Many weirds points, no ?
> Thank you very much
> BSP overran lower stack boundary. Undefined behaviour may result!
This is probably the issue right here. This means a coreboot developer
(preferably with access to this hardware) needs to take a look at the
stack allocation for the 0xf Opteron chips to see why coreboot is
overrunning the stack space.
+1 (415) 727-8645 (direct line)
+1 (512) 690-0200 (switchboard)
Raptor Engineering::Home Page<https://www.raptorengineering.com/>
Let Raptor Engineering handle your next high-performance digital design! We offer consulting services in: Embedded systems design; Boot firmware development (e.g ...
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coreboot mailing list: coreboot(a)coreboot.org<mailto:email@example.com>
We've been investigating lately the issue with ASM1061 on the APU2 board,
because it often turns up in different discussions. Problem is, that the mPCIe 2
slot on APU2 platform is not working the same as mPCIe 1 slot. Controller is not
detected, and even if it is, the machine enters boot loop (after some disk is
physically connected).I've pinpointed the location of the machine reset to AHCI
port detect routines in SeaBIOS. I've made some notes about my investigation
WLAN cards, as far as I know, work without major problems. The one difference
between the slots is that mPCIe 2 is actually using PCI express channel
dedicated to graphic card (so is using the root complex in north bridge),
whereas mPCIe 1 is using PCI express root complex from the south bridge.
Does anybody have any insights, where could I look further to investigate this
issue, because I'm stuck at the moment?
Embedded Systems Engineer
http://3mdeb.com | @3mdeb_com
Hi (again) coreboot:
I read the below from the digest.
Having brought the P2B-LS into coreboot along with RAM init to 440BX
northbridge and cache init to Slot 1 CPUs back in 2010, I am
interested in bringing this platform up to standard. Where can I read
up on this cbmem in romstage standard?
However, of the family I only have P2B-LS and P3B-F on hand to boot test.
I just checked out the master from git in case they are part of the readings.
On Thu, May 11, 2017 at 3:55 PM, <coreboot-request(a)coreboot.org> wrote:
> Date: Thu, 11 May 2017 10:24:16 -0600
> From: Martin Roth <gaumless(a)gmail.com>
> To: coreboot <coreboot(a)coreboot.org>
> Subject: [coreboot] Platform / Chip removals after upcoming releases
> Content-Type: text/plain; charset="utf-8"
> Along with the latest coreboot release, coreboot announced some standards
> for removing platforms after upcoming releases.
> * After the 4.7 release platforms that do not support cbmem in romstage
> will be removed. Please see the list of platforms to be removed if no work
> is done to update them at the end of this email.
> Code removal after the 4.7 release
> The next expectation that will need to be met for all platforms is cbmem in
> romstage. This currently affects numerous platforms, including most, if not
> all of AMD's platforms. Work to update many of these platforms has started,
> but there are others that have not made any progress towards this goal. A
> of the platforms that are affected by this is included at the end of this
> 146 Platforms currently scheduled for removal after 4.7 if no work is done
> to update them
Thanks for the info. After adding changes, I can able to build coreboot
After flashing coreboot.rom, still ethernet is not working (Ethernet port's
LED is not blinking). Actually, My broad has Broadcom Ethernet controller.
Is there any specific setting have to do for Broadcom in Coreboot's
CPU: Intel Rageley CPU.
Mother Board: Accton AS7512X_32
Switch IC: Cavium.
On Mon, Jun 26, 2017 at 6:43 PM, Dhanasekar Jaganathan <
> Hi All,
> I am trying to enable ethernet in coreboot + GRUB2. So I have enabled
> following option in make meuconfig,
> *1. Payload -> Add a PXE ROM = Y*
> *2. Payload -> PXE options -> PXE ROM to use = "Build and add an iPXE ROM
> After enabling those option, I am getting below error,
> *"util/zbin.c:7:18: fatal error: lzma.h: No such file or directory."*
> I have noticed lzma.h is not available in /payloads/external/iPXE/ipxe/
> Is there any option I have to enable? or have I missed any option ? in
> make menuconfig.
> Correct me, If steps (which I followed) to enable PXE ROM is wrong.
the last time I tried coreboot on X201 (2 months ago) there were some
problems with powering the device off and also with suspend to RAM.
These problems are also somehow mentioned on wiki in Issues.
I would like to ask if someone has an idea how to try to fix this
issues. I can do C programming and am willing to experiment on my X201,
but do not know what exactly should I try and how...
After a git pull, the following error appeared:
make: *** No rule to make target
'src/vendorcode/amd/agesa/f15tn/Include/gcc-intrin.h', needed by