coreboot June 2017

coreboot@coreboot.org

57 participants
159 discussions

problems with compilation for asrock g41c-gs-2.0
by Rostislav Okulov 15 Jun '17

15 Jun '17

Hello, guys. I need some help with coreboot. First I have created config with "make menuconfig" compilation works with Rom chip size 8Mb (but if I understand correctly for this motherboard it Rom chip size should be 1Mb) with 1Mb building stops here: FMAP build/util/cbfstool/fmaptool -h build/fmap_config.h build/fmap.fmd build/fmap.fmap syntax error FATAL: Failed while processing provided descriptor Makefile.inc:856: recipe for target 'build/fmap.fmap' failed make: *** [build/fmap.fmap] Error 4 Second When I 've created seabios config and copied it with name .seabiosconfig in coreboot directory anyway script use it's default config CC ramstage/arch/x86/wakeup.o CP ramstage/arch/x86/memlayout.ld CP ramstage/lib/program.ld CC generated/ramstage.o CC cbfs/fallback/ramstage.debug Fetching new commits from the SeaBIOS git repo Checking out SeaBIOS revision origin/master Switched to branch 'master' Your branch is up-to-date with 'origin/master'. Deleted branch coreboot (was 3fdabae). Branch coreboot set up to track remote branch master from origin. Switched to a new branch 'coreboot' CONFIG SeaBIOS origin/master /home/gutsycat/coreboot/coreboot/payloads/external/SeaBIOS/seabios/.config:15:warning: override: reassigning to symbol COREBOOT /home/gutsycat/coreboot/coreboot/payloads/external/SeaBIOS/seabios/.config:15:warning: override: COREBOOT changes choice state /home/gutsycat/coreboot/coreboot/payloads/external/SeaBIOS/seabios/.config:90:warning: override: reassigning to symbol VGA_COREBOOT /home/gutsycat/coreboot/coreboot/payloads/external/SeaBIOS/seabios/.config:90:warning: override: VGA_COREBOOT changes choice state /home/gutsycat/coreboot/coreboot/payloads/external/SeaBIOS/seabios/.config:91:warning: override: reassigning to symbol BUILD_VGABIOS /home/gutsycat/coreboot/coreboot/payloads/external/SeaBIOS/seabios/.config:102:warning: override: reassigning to symbol DEBUG_SERIAL # # configuration written to /home/gutsycat/coreboot/coreboot/payloads/external/SeaBIOS/seabios/.config # MAKE SeaBIOS origin/master Build Kconfig config file Compile checking out/src/misc.o Compile checking out/src/stacks.o Compile checking out/src/output.o Third How can I test my ROM with and emulator before installing it? Thank you for your help.

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Re: [coreboot] How to give control to bootable USB
by Nico Huber 15 Jun '17

15 Jun '17

Hi Dhanasekar, On 14.06.2017 11:21, Dhanasekar Jaganathan wrote: > Hi Taiidan, > > My USB ONIE installers don't have "isolinux/syslinux.cfg". It has > "boot/grub/grub.cfg". > > When I try to run "syslinux_configfile (usb0)/boot/grub/grub.cfg" in GRUB > command line, I am getting "*kernel without label*" error. > > Please provide your commands Taiidan already told you the correct command name (33 lines below). You might have missed it ;) Nico > > Thanks, > Dhanasekar > > On Wed, Jun 14, 2017 at 3:22 AM, Taiidan(a)gmx.com <Taiidan(a)gmx.com> wrote: > >> On 06/13/2017 10:22 AM, Dhanasekar Jaganathan wrote: >> >> Hi All, >>> >>> I am trying to install ONIE from USB which has ONIE installer. Actually, I >>> am using GRUB2 as a payload. If Coreboot display list of bootable >>> device,I >>> can select USB which will install a OS in the hard disk. As I understood >>> that Coreboot won't display list of available bootable device (not like >>> vendor bios).I don't know how to give control to bootable USB or boot a >>> bootable USB by coreboot. Can you please help me on this?. >>> >>> >>> Thanks, >>> Dhanasekar >>> >> Assuming you are booting a standard linux distro iso: >> syslinux_configfile (*TAB* to see what is available >> >> then simply for instance syslinux_configfile (usb0,msdos1)/isolinux/syslinux.cfg >> (or w/e) >> >> also configfile (ahci0,msdos1)/grub2/grub.cfg to load a grub cfg >> >> Ideally you would add a grub cfg to the coreboot image that does something >> like load a config file from a specified local disk so that it is easy to >> update (ie: no re-flashing) instructions for that are on the wiki. >> >> SeaBIOS would provide the classic AMI style F12 selection menu, but I >> don't like it due to how many times I have accidentally enabled option rom >> execution by forgetting to include the configuration file. >> > > >

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Re: [coreboot] CBFS mounting failure
by Nico Huber 15 Jun '17

15 Jun '17

Hi, On 14.06.2017 23:23, Gailu Singh wrote: > Hi Experts, > > We are using grub2 payload. > > When we configure coreboot with CONFIG_CBFS_SIZE and CONFIG_ROM_SIZE to be > same, grub fails to mount cbfsdisk. if you work with a modern x86 system that is expected. The flash chip isn't dedicated to the "BIOS" anymore. In case of an Intel system the CBFS must not be bigger than the BIOS region of the flash chip, or it will be overwritten by other firmware parts. Again in case of Intel, you can use `ifdtool` [1] to decode the flash regions. Nico [1] in `util/ifdtool` of the coreboot source tree

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Re: [coreboot] t420 MCE and crashing with ivy bridge cpu
by Nico Huber 15 Jun '17

15 Jun '17

Hello Marcus, I guess you are not alone: https://ticket.coreboot.org/issues/121 Looks like the same issue, on a T520 with Ivy Bridge CPU. According to some reports, the combination was working before. Maybe it's a regression. The combination is probably not often tested. Also, as you speak of the flash image as if it were a single entity: It's not. There are multiple firmwares and configuration blobs that share the flash chip. You shouldn't flash all of them at once. It can confuse the Management Engine (ME) and cause random errors. Hard to trace the issue down then, if you don't know which part of the flash (or the flashing process itself) causes it. You can check your coreboot log for ME errors. Speaking of the ME, it might be possible that you need a version that supports Ivy Bridge. Just a random guess, I don't have any experience with the ME firmware shipped with Sandy Bridge. One last thought, you should make sure that the microcode updates are applied. Hope that helps, Nico

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CBFS mounting failure
by Gailu Singh 14 Jun '17

14 Jun '17

Hi Experts, We are using grub2 payload. When we configure coreboot with CONFIG_CBFS_SIZE and CONFIG_ROM_SIZE to be same, grub fails to mount cbfsdisk. We added prints and found that it fails at following check in grub-core/fs/cbfs.c ptr = grub_cpu_to_le32 (ptr); header_off = (grub_disk_get_size (disk) << GRUB_DISK_SECTOR_BITS) + (grub_int32_t) ptr; if (grub_disk_read (disk, 0, header_off, sizeof (head), &head)) goto fail; However if we keep margin of min 64KB between CONFIG_ROM_SIZE and CONFIG_CBFS_SIZE it works perfectly. Is there any possibility that coreboot mess up cbfs layout when both rom size and cbfs size are same Thank you

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t420 MCE and crashing with ivy bridge cpu
by Marcus Walsh 14 Jun '17

14 Jun '17

Hi, I'm running a 3630qm in my t420 with coreboot. When using the original sandybridge cpu, I have no issues. When using the ivy bridge 3630qm: On linux, 300 seconds into boot I get 2 machine check exceptions (posted below). The exceptions indicate an issue with level 2 cache. I ran all the tests on memtest86 (which also tests cpu caches) and got no errors. I do not have another board anymore to test the cpu to rule out the possibility of a hardware issue with the cpu, however the cpu was perfect last time I used it. On both Windows 10 and Linux (Debian), after a random amount of time running, the computer becomes unresponsive and the screen goes black with some artifacting on the edge of the screen. This occurs more frequently when running on battery, usually after about 10 minutes. When running on AC, this does not occur for a few hours. On Windows, I set all the power management to "High performance", disabled ASPM, and the issue has not occurred since when running on AC, I have yet to test it properly on battery power. I ran Linux with pcie_aspm=off, and the issue still occurs. These issues occur on every coreboot rom I have tried. Including the rom on the t420 coreboot wiki page. I'm also using the original t420 battery, and not the extended one, if that matters. Questions: 1) What else can I do to figure out if this is indeed a hardware issue or not? 2) Are there any specific kernel versions or parameters I should try? 3) Are there any coreboot config options I should try? Any help at all would be really appreciated. I really want to make sure this is a hardware problem before I shell out for another cpu. The whole point of installing coreboot was so that I could reuse this cpu. Here are the MCE's, it is always the same two, CACHE Level-2 Generic Error on bank 7 and bank 8, and it always occurs 300 seconds after boot. Hardware event. This is not a software error. MCE 0 CPU 0 BANK 7 MISC 1040000086 ADDR feffff40 TIME 1496380314 Fri Jun 2 06:11:54 2017 MCG status: MCi status: Error overflow Uncorrected error MCi_MISC register valid MCi_ADDR register valid Processor context corrupt MCA: corrected filtering (some unreported errors in same region) Generic CACHE Level-2 Generic Error STATUS ee2000000003110a MCGSTATUS 0 MCGCAP c09 APICID 0 SOCKETID 0 CPUID Vendor Intel Family 6 Model 58 Hardware event. This is not a software error. MCE 1 CPU 0 BANK 8 MISC 1040000086 ADDR feffff00 TIME 1496380314 Fri Jun 2 06:11:54 2017 MCG status: MCi status: Error overflow Uncorrected error MCi_MISC register valid MCi_ADDR register valid Processor context corrupt MCA: corrected filtering (some unreported errors in same region) Generic CACHE Level-2 Generic Error STATUS ee2000000003110a MCGSTATUS 0 MCGCAP c09 APICID 0 SOCKETID 0 CPUID Vendor Intel Family 6 Model 58

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t420 MCE and crashing with ivy bridge cpu
by Marcus Walsh 14 Jun '17

14 Jun '17

1 0

Re: [coreboot] How to give control to bootable USB
by Taiidan＠gmx.com 14 Jun '17

14 Jun '17

On 06/13/2017 10:22 AM, Dhanasekar Jaganathan wrote: > Hi All, > > I am trying to install ONIE from USB which has ONIE installer. Actually, I > am using GRUB2 as a payload. If Coreboot display list of bootable device,I > can select USB which will install a OS in the hard disk. As I understood > that Coreboot won't display list of available bootable device (not like > vendor bios).I don't know how to give control to bootable USB or boot a > bootable USB by coreboot. Can you please help me on this?. > > > Thanks, > Dhanasekar Assuming you are booting a standard linux distro iso: syslinux_configfile (*TAB* to see what is available then simply for instance syslinux_configfile (usb0,msdos1)/isolinux/syslinux.cfg (or w/e) also configfile (ahci0,msdos1)/grub2/grub.cfg to load a grub cfg Ideally you would add a grub cfg to the coreboot image that does something like load a config file from a specified local disk so that it is easy to update (ie: no re-flashing) instructions for that are on the wiki. SeaBIOS would provide the classic AMI style F12 selection menu, but I don't like it due to how many times I have accidentally enabled option rom execution by forgetting to include the configuration file.

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Re: [coreboot] soc/amd/stoneyridge
by Taiidan＠gmx.com 14 Jun '17

14 Jun '17

I don't think that trying to support every 10+ year old board is worth it, but at least a few from each genre (desktop, server/workstation and embedded) should be required to be ported for a style change to occur rather than everything simply abandoned as there wasn't anyone willing to update it. AFAIK as of now every non-development AMD board will be dropped in a few release cycles, I am not a firmware developer but I can't understand as to how a code style change makes that worth it especially considering many of those are the last and latest owner controlled x86 devices. In terms of vendor support (for the very few that do that); the majority of coreboot boards are in the expensive server or the embedded category so I don't think that it is unreasonable to expect the hypothetical vendor that releases code and advertises coreboot support to directly support for both initial release equivalent functionality and security it for 2x the hw warranty (as that is generally a useful life for most hardware) The "standard" 3 and now even 1 year update lifecycle that comes with hardware is creating a massive internet security issue.

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Re: [coreboot] AMD EPYC and PSP
by Taiidan＠gmx.com 14 Jun '17

14 Jun '17

On 06/08/2017 10:48 AM, Johnysecured88 via coreboot wrote: > Does anyone anticipate the new EPYC cpus not having PSP? > > Sent with [ProtonMail](https://protonmail.com) Secure Email. I see no reason why they wouldn't. It doesn't really matter, for the price they'll be sold for you might as well buy POWER as you'd be getting better performance (8 threads/core) and an actual owner controlled device. I can't understand as to why everyone complains that power is expensive when they're comparing it to low end x86 processors, in terms of raw compute power you'd spend just as much with an off the shelf equivalent dell/hpe - the high end xeon CPU's alone are 2K+ if you DIY.

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coreboot June 2017