coreboot March 2017

coreboot@coreboot.org

79 participants
267 discussions

Re: [coreboot] Lenovo Thinkpad X201: cannot boot encrypted Debian w/Coreboot & GRUB2
by Nico Huber 24 Mar '17

24 Mar '17

On 24.03.2017 04:16, Sam Kuper wrote: > On 23/03/2017, Arthur Heymans <arthur(a)aheymans.xyz> wrote: >> Last option is hook up libgfxinit, an alternative Intel display init >> code written in ada/spark, which might set up display correctly... > > Nice. I will look into that when I get a chance. It might take me a > while. I haven't built an Ada toolchain before. Would be great if it > works, though! This got a lot easier just yesterday. On most Linux distros you just have to install the gnat package (sometimes called gcc-ada) matching your GCC. Then, if you are up-to-date on coreboot master, this should work: $ make crossgcc-clean $ # or `mv util/crossgcc/xgcc{,.bak}` if you want to keep a backup $ make crossgcc-i386 BUILD_LANGUAGES=c,ada CPUS=4 The `BUILD_LANGUAGES=c,ada` shouldn't be necessary but makes it error- out in case something is wrong with gnat. You'll have to hook it up for the X201 then, similar to "1b3a6e4b14 mb/google/slippy: Hook up libgfxinit". And select CONFIG_MAINBOARD_ USE_LIBGFXINIT. Let me know if you have further questions / need any assistance. Nico

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Re: [coreboot] Lenovo Thinkpad X201: cannot boot encrypted Debian w/Coreboot & GRUB2
by Peter Stuge 24 Mar '17

24 Mar '17

Sam Kuper wrote: > GNUtoo in 2013: > GNUtoo in 2013: > phcoder in 2013: > phcoder in 2014: > Kl3 in 2015 > > So, it would seem that during 2013-2015, native graphics init became > operational within Coreboot for the X201. TL;DR: That code was always poor, don't expect it to work reliably. Don't assume that any merged code is general and robust, only because it might have worked for some developers in some case. If you need reliable graphics init then please use the VGA BIOS until you can [sponsor someone who can] analyze and address (potentially also design) problems in the native graphics init C code. If you do go on into development, then please do not waste time on the native graphics init C code, but instead please work on making use of libgfxinit on the platform you are interested in. It is the way to go forward. Thanks //Peter

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New Defects reported by Coverity Scan for coreboot
by scan-admin＠coverity.com 24 Mar '17

24 Mar '17

Hi, Please find the latest report on new defect(s) introduced to coreboot found with Coverity Scan. 1 new defect(s) introduced to coreboot found with Coverity Scan. 1 defect(s), reported by Coverity Scan earlier, were marked fixed in the recent build analyzed by Coverity Scan. New defect(s) Reported-by: Coverity Scan Showing 1 of 1 defect(s) ** CID 1372941: Control flow issues (UNREACHABLE) /src/northbridge/intel/i945/debug.c: 86 in dump_spd_registers() ________________________________________________________________________________________________________ *** CID 1372941: Control flow issues (UNREACHABLE) /src/northbridge/intel/i945/debug.c: 86 in dump_spd_registers() 80 device = DIMM0; 81 while (device <= DIMM3) { 82 int status = 0; 83 int i; 84 printk(BIOS_DEBUG, "\ndimm %02x", device); 85 >>> CID 1372941: Control flow issues (UNREACHABLE) >>> Since the loop increment "i++;" is unreachable, the loop body will never execute more than once. 86 for (i = 0; (i < 256); i++) { 87 if ((i % 16) == 0) 88 printk(BIOS_DEBUG, "\n%02x: ", i); 89 status = smbus_read_byte(device, i); 90 if (status < 0) 91 printk(BIOS_DEBUG, "bad device: %02x\n", -status); ________________________________________________________________________________________________________ To view the defects in Coverity Scan visit, https://u2389337.ct.sendgrid.net/wf/click?upn=08onrYu34A-2BWcWUl-2F-2BfV0V0… To manage Coverity Scan email notifications for "coreboot(a)coreboot.org", click https://u2389337.ct.sendgrid.net/wf/click?upn=08onrYu34A-2BWcWUl-2F-2BfV0V0…

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Re: [coreboot] Maintain boot order for multiple EFI based OS
by Martin Roth 24 Mar '17

24 Mar '17

As I recall, the rangeley FSP actually *REQUIRES* the mrc cache. Not having it would be a definite problem. Did you select "Use MRC Cache in FMAP"? If you did, that puts it outside of cbfs, so it wouldn't show up in that list. Are you working from upstream coreboot, or a tree from somewhere else? Martin On Fri, Mar 24, 2017 at 7:00 AM, <Sibi.Rajasekaran(a)dell.com> wrote: > Dell - Internal Use - Confidential > > Hi Matt, > > Thanks for the prompt response. > > I am using Rangeley FSP in my coreboot environment and I don’t see mrc cache > in the coreboot region even though I chose to use MRC Cache in the config. > > Performing operation on 'COREBOOT' region... > > Name Offset Type Size > > cbfs master header 0x0 cbfs header 32 > > fallback/romstage 0x80 stage 27612 > > cpu_microcode_blob.bin 0x6cc0 microcode 167936 > > fallback/ramstage 0x2fd40 stage 121204 > > config 0x4d700 raw 539 > > revision 0x4d980 raw 588 > > cmos_layout.bin 0x4dc40 cmos_layout 1320 > > fallback/dsdt.aml 0x4e1c0 raw 8074 > > fallback/payload 0x501c0 payload 648600 > > img/memtest 0xee7c0 payload 180268 > > (empty) 0x11a840 null 415320 > > fsp.bin 0x17fec0 fsp 389120 > > (empty) 0x1def00 null 132504 > > bootblock 0x1ff4c0 bootblock 2560 > > > > I had built the tianocore long before(may be 6 months back) and I am pretty > sure I chose release payload. > > > > Thanks, > > Sibi > > From: Matt DeVillier [mailto:matt.devillier@gmail.com] > Sent: Friday, March 24, 2017 2:23 PM > To: Rajasekaran, Sibi <Sibi_Rajasekaran(a)Dell.com> > Cc: Zoran Stojsavljevic <zoran.stojsavljevic(a)gmail.com>; coreboot > <coreboot(a)coreboot.org> > Subject: Re: [coreboot] Maintain boot order for multiple EFI based OS > > > > > > > > On Fri, Mar 24, 2017 at 6:26 PM, <Sibi.Rajasekaran(a)dell.com> wrote: > > > > For your question, takes around 26 seconds from power On till Tianocore > execute completion. Looking at reducing this boot time. > > > > > > Sibi, if you're not using mrc cache for RAM training, that's likely > contributing 10s or so at least. Have you enabled coreboot timestamps and > used cbmem to examine time to payload execute? Also, building Tianocore in > debug (vs release) mode adds a bit of time as well due to the volume of > serial output. I use coreboot + Tianocore on Baytrail N28xx/29xx (though > not with FSP) and normal boot (after RAM training) with a release payload is > on the order of 2s, with coreboot taking about 6-700ms of that. > > > -- > coreboot mailing list: coreboot(a)coreboot.org > https://www.coreboot.org/mailman/listinfo/coreboot

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Re: [coreboot] Recall: Maintain boot order for multiple EFI based OS
by ron minnich 24 Mar '17

24 Mar '17

There's really no way to recall a post to a list that is global. On Fri, Mar 24, 2017 at 7:02 AM Zoran Stojsavljevic < zoran.stojsavljevic(a)gmail.com> wrote: > About this... This, we'll do on the common ground that GOOGLE people do > understand you, and me (after all)!? > > Do you, Google people? (I need mandatory reply/Re: -> Better be, so... if > you do NOT agree, I 'll take the appropriate Legal Action)! ; -) > > Zoran > > On Fri, Mar 24, 2017 at 2:43 PM, <Sibi.Rajasekaran(a)dell.com> wrote: > > > > *Dell - Internal Use - Confidential * > > Hi, > > > > Just the two of you in the email. > > I am trying to remove the Dell Internal folly that my outlook attaches to > my emails which someone already commented not to do so. > > No other reason for recalling. > > > > Thanks, > > Sibi > > *From:* Zoran Stojsavljevic [mailto:zoran.stojsavljevic@gmail.com] > *Sent:* Friday, March 24, 2017 6:54 PM > *To:* Rajasekaran, Sibi <Sibi_Rajasekaran(a)Dell.com> > *Cc:* Matt DeVillier <matt.devillier(a)gmail.com>; coreboot < > coreboot(a)coreboot.org> > *Subject:* Re: Recall: [coreboot] Maintain boot order for multiple EFI > based OS > > > > OK, Sibi, I read you... As I understand, you would like to recall the > complete thread. > > > > Your decision... You are free man, and I value that... I have here only > ONE Question? Why? > > > > Thank you, > > Zoran > > > > On Fri, Mar 24, 2017 at 2:02 PM, <Sibi.Rajasekaran(a)dell.com> wrote: > > Rajasekaran, Sibi would like to recall the message, "[coreboot] Maintain > boot order for multiple EFI based OS". > > > > -- > coreboot mailing list: coreboot(a)coreboot.org > https://www.coreboot.org/mailman/listinfo/coreboot

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Group demographics
by tturne＠codeaurora.org 24 Mar '17

24 Mar '17

Folks, I've been monitoring the list for ~6 months with a couple of posts. My point of interest is working with Coreboot on ARMv8 targeting a Chromebook. I have a couple of questions for this group. Q.1) Are questions related to Coreboot + Payload that boots a Chromebook appropriate for this list or a ChromiumOS list? Q.2) What percentage of the developers on this list are working with Chromebook vs trying to get Coreboot to run on an arbitrary laptop or other device? Cheers, T.mike

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Re: [coreboot] Recall: Maintain boot order for multiple EFI based OS
by Zoran Stojsavljevic 24 Mar '17

24 Mar '17

About this... This, we'll do on the common ground that GOOGLE people do understand you, and me (after all)!? Do you, Google people? (I need mandatory reply/Re: -> Better be, so... if you do NOT agree, I 'll take the appropriate Legal Action)! ; -) Zoran On Fri, Mar 24, 2017 at 2:43 PM, <Sibi.Rajasekaran(a)dell.com> wrote: > > > *Dell - Internal Use - Confidential * > > Hi, > > > > Just the two of you in the email. > > I am trying to remove the Dell Internal folly that my outlook attaches to > my emails which someone already commented not to do so. > > No other reason for recalling. > > > > Thanks, > > Sibi > > *From:* Zoran Stojsavljevic [mailto:zoran.stojsavljevic@gmail.com] > *Sent:* Friday, March 24, 2017 6:54 PM > *To:* Rajasekaran, Sibi <Sibi_Rajasekaran(a)Dell.com> > *Cc:* Matt DeVillier <matt.devillier(a)gmail.com>; coreboot < > coreboot(a)coreboot.org> > *Subject:* Re: Recall: [coreboot] Maintain boot order for multiple EFI > based OS > > > > OK, Sibi, I read you... As I understand, you would like to recall the > complete thread. > > > > Your decision... You are free man, and I value that... I have here only > ONE Question? Why? > > > > Thank you, > > Zoran > > > > On Fri, Mar 24, 2017 at 2:02 PM, <Sibi.Rajasekaran(a)dell.com> wrote: > > Rajasekaran, Sibi would like to recall the message, "[coreboot] Maintain > boot order for multiple EFI based OS". > > >

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Re: [coreboot] Recall: Maintain boot order for multiple EFI based OS
by Gregg Levine 24 Mar '17

24 Mar '17

Hello! Our friend is under the impression that this is a closed source Exchange based list, (which it is not!). Instead of a properly managed open source list, which it is. ----- Gregg C Levine gregg.drwho8(a)gmail.com "This signature fought the Time Wars, time and again." On Fri, Mar 24, 2017 at 9:24 AM, Zoran Stojsavljevic <zoran.stojsavljevic(a)gmail.com> wrote: > OK, Sibi, I read you... As I understand, you would like to recall the > complete thread. > > Your decision... You are free man, and I value that... I have here only ONE > Question? Why? > > Thank you, > Zoran > > On Fri, Mar 24, 2017 at 2:02 PM, <Sibi.Rajasekaran(a)dell.com> wrote: >> >> Rajasekaran, Sibi would like to recall the message, "[coreboot] Maintain >> boot order for multiple EFI based OS". > > > > -- > coreboot mailing list: coreboot(a)coreboot.org > https://www.coreboot.org/mailman/listinfo/coreboot

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Re: [coreboot] Recall: Maintain boot order for multiple EFI based OS
by Zoran Stojsavljevic 24 Mar '17

24 Mar '17

OK, Sibi, I read you... As I understand, you would like to recall the complete thread. Your decision... You are free man, and I value that... I have here only ONE Question? Why? Thank you, Zoran On Fri, Mar 24, 2017 at 2:02 PM, <Sibi.Rajasekaran(a)dell.com> wrote: > Rajasekaran, Sibi would like to recall the message, "[coreboot] Maintain > boot order for multiple EFI based OS".

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Re: [coreboot] Maintain boot order for multiple EFI based OS
by Sibi.Rajasekaran＠dell.com 24 Mar '17

24 Mar '17

Dell - Internal Use - Confidential Hi Matt, Thanks for the prompt response. I am using Rangeley FSP in my coreboot environment and I don’t see mrc cache in the coreboot region even though I chose to use MRC Cache in the config. Performing operation on 'COREBOOT' region... Name Offset Type Size cbfs master header 0x0 cbfs header 32 fallback/romstage 0x80 stage 27612 cpu_microcode_blob.bin 0x6cc0 microcode 167936 fallback/ramstage 0x2fd40 stage 121204 config 0x4d700 raw 539 revision 0x4d980 raw 588 cmos_layout.bin 0x4dc40 cmos_layout 1320 fallback/dsdt.aml 0x4e1c0 raw 8074 fallback/payload 0x501c0 payload 648600 img/memtest 0xee7c0 payload 180268 (empty) 0x11a840 null 415320 fsp.bin 0x17fec0 fsp 389120 (empty) 0x1def00 null 132504 bootblock 0x1ff4c0 bootblock 2560 I had built the tianocore long before(may be 6 months back) and I am pretty sure I chose release payload. Thanks, Sibi From: Matt DeVillier [mailto:matt.devillier@gmail.com] Sent: Friday, March 24, 2017 2:23 PM To: Rajasekaran, Sibi <Sibi_Rajasekaran(a)Dell.com> Cc: Zoran Stojsavljevic <zoran.stojsavljevic(a)gmail.com>; coreboot <coreboot(a)coreboot.org> Subject: Re: [coreboot] Maintain boot order for multiple EFI based OS On Fri, Mar 24, 2017 at 6:26 PM, <Sibi.Rajasekaran(a)dell.com<mailto:Sibi.Rajasekaran@dell.com>> wrote: For your question, takes around 26 seconds from power On till Tianocore execute completion. Looking at reducing this boot time. Sibi, if you're not using mrc cache for RAM training, that's likely contributing 10s or so at least. Have you enabled coreboot timestamps and used cbmem to examine time to payload execute? Also, building Tianocore in debug (vs release) mode adds a bit of time as well due to the volume of serial output. I use coreboot + Tianocore on Baytrail N28xx/29xx (though not with FSP) and normal boot (after RAM training) with a release payload is on the order of 2s, with coreboot taking about 6-700ms of that.

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coreboot March 2017