coreboot March 2017

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79 participants
267 discussions

Re: [coreboot] PS/2 Mouse on KGPE-D16
by Taiidan＠gmx.com 20 Mar '17

20 Mar '17

On 03/20/2017 05:15 PM, cb(a)imap.cc wrote: > Has anybody had any success using a PS/2 mouse on the KGPE-D16? > > > > I tried a few PS/2 compatible USB mice, along with an adaptor, without > success and thought that the mice might be to blame but I've just > confirmed a native PS/2 mouse doesn't seem to work either. > > > I've tried booting directly from SeaBIOS and also with GRUB2 as a > secondary and no combination I try seems to work. Maybe a silly question but did you enable PS/2 init in menuconfig?

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Intel ME and the onboard e1000e
by Trammell Hudson 20 Mar '17

20 Mar '17

As a very belated data point to disabling the ME on the x230, it appears that it also disables the e1000e wired ethernet. The Linux kernel's ich8lan.c file reports an error that "No valid NVM bank present" and won't bring up eth0 if the ME has been flashed with a minimal firmware. Since the ME shares the device with the host for command & control by external parties, this seems like there must be some setup that the ME does on the device to coordinate access with the x86. -- Trammell

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PS/2 Mouse on KGPE-D16
by cb＠imap.cc 20 Mar '17

20 Mar '17

Has anybody had any success using a PS/2 mouse on the KGPE-D16? I tried a few PS/2 compatible USB mice, along with an adaptor, without success and thought that the mice might be to blame but I've just confirmed a native PS/2 mouse doesn't seem to work either. I've tried booting directly from SeaBIOS and also with GRUB2 as a secondary and no combination I try seems to work.

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Re: [coreboot] Lenovo Thinkpad Yoga 11e (1st Gen, Win10 variant)
by John Lewis 20 Mar '17

20 Mar '17

Again, I'm being Captain Vague here, but I'm fairly sure Ron/similar have advised on the difficulty of doing something like this before - not that it's as hard as doing a port from scratch, but that you still do need pretty in-depth firmware/c experience to do it. Regards, John. On 20/03/17 12:10, Christopher Grossarth wrote: > Thanks for the swift reply. > > I didn't say I thought this would be easy. I know porting to a new > board isn't a trivial task but that's what we try to do here, no? > > Do you know of a tool for extracting the EC for comparison? > > And if there are any nuts and bolts folks out there, I'd like to hear > ideas. > > Struggle is my middle name. > > Best, > > C. "Struggle" Grossarth > > > On Mon, Mar 20, 2017, 5:47 AM John Lewis <jlewis(a)johnlewis.ie > <mailto:jlewis@johnlewis.ie>> wrote: > > Hi C Grossarth, > > Well, the Win variant will have a different EC for a start, so if > you're expecting to be able to build and flash coreboot for the > Chromebook variant with minimal changes, you will probably > struggle. Other people will know much more what's required than I > though - I just have reasonably high-level knowledge, not nuts and > bolts. > > Regards, > > John. > > > On 20/03/17 02:38, Christopher Grossarth wrote: >> Hello All, >> >> I have been exploring coreboot, and have successfully built and >> flashed it on a MacBook 2,1. Initially I was using Libreboot, but >> wanted more control over the end result. >> >> I bought a Lenovo ChromeBook Yoga 11e 1st Gen), but swiftly >> returned it after I realized the product description on Lenovo's >> page mislabeled it as having SSD and RAM modules. The ChromeBook >> version has eMMC and soldered on RAM. >> >> The Windows 10 version of the same variety (Intel Celeron N2930) >> has a SSD and a replaceable/upgradeable RAM module. >> The ChromeBook variant is codenamed Glimmer. >> >> I would like to know what steps would be necessary to build and >> flash coreboot onto the Win10 board. >> Most importantly, how would I go about extracting the information >> so that I can edit the Glimmer config overlays to reflect the >> hardware config in the Win10 variant? >> >> Many Thanks in advance, >> >> C Grossarth. >> >> >

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Re: [coreboot] USB Support on Apollo Lake
by Zoran Stojsavljevic 20 Mar '17

20 Mar '17

Hello Gaily, Several time here, on Coreboot threads, I wrote the following (regarding BYT and post ATOM families skus): There are two root hub controllers in BYT: USB 3.0 - xHCI and USB 2.0 (legacy one) - EHCI. The trick here is that you/nobody could not have them both working at the same time. Either you set/select one, or another. Why? They are on the different clocking domains. In other words all your USBs will hang out either of USB 3.0 root hub, either of USB 2.0 root hub. You could NOT mix outside USB ports (to have them hanging out from both root hubs mixed). To enhance/fix this further, past BYT time, INTEL totally removed from ATOM silicon (not only) EHCI legacy USB 2.0 root hub, because of that bug. So, since BSW (including APL-I, former BXT-I), there is ONLY USB 3.0 xHCI root hub. The (maybe) efficient method is to put on xHCI 3.0 passive Belkin USB 2.0 bridge as bypass, maybe this can make this transition smooth. Helps with my HSW notebook, since mine notebook USB 3.0 root hub ports do not work with my printer USB 2.0 eHCI port, connected straight (with Belkin does, but on WIN10 OS). About IO mapped UART I have no idea, but I think there should be some (virtual?!) UARTs available. Not sure how this design plays out (certainly, you should have SW drivers for these for Linux). Have no clue about GRUB/GRUB2 implementation. You might also try USB to UART physical converter, and see if it is recognized by GRUB2. Does work for Linux. Zoran On Mon, Mar 20, 2017 at 1:01 PM, Gailu Singh <gailu96(a)gmail.com> wrote: > Hi Werner, > > Thanks for your detailed clarification. Looks like Intel removing various > legacy interfaces and support for alternatives is yet to be developed in > grub. No only they removed USB2.0 altogether, they also removed IO mapped > UART and we can't get serial console working on this board either with grub. > > For USB I am making a last attempt to use PCIE USB2.0 card and ordered > following from Aliexpress but I have serious doubts if this will work in > Grub2. Will post the results once I get the cards delivered. > > https://www.aliexpress.com/item/Hot-New-Mini-PCI-E-Card- > Slot-Expansion-to-USB-2-0-Interface-Adapter-Riser-Card/ > 32531508095.html?spm=2114.13010608.0.0.KTeUNS > > > Thank you very much once again. > > On Mon, Mar 20, 2017 at 5:18 PM, Zeh, Werner <werner.zeh(a)siemens.com> > wrote: > >> Hi Gailu. >> >> I don't think that one can configure the xHCI to behave like an EHCI so >> that GRUB2 can natively support it. >> xHCI has different version number in the PCI space which will prevent the >> EHCI driver in GRUB2 to use this controller at all. >> Not speaking about the complete different register set and operational >> model. >> >> What in turn should work is that "some of the BIOS" (which in >> coreboot-context is the payload like SeaBIOS) will handle all the >> xHCI stuff and provide a legacy interface to the OS (and here GRUB acts >> as an OS) to just read mass storage devices using interrupts. >> >> Beside that you are lost with GRUB2 and xHCI, sorry! >> >> Werner >> >> >Hi Experts, >> > >> >Does coreboot support USB port initialization in legacy mode on Apollo >> Lake as some of the BIOS does so that grub or other payloads can use it as >> USB2.0? >> > >> >There is no USB2.0 port on this board and Grub2 doesn't support xhci so >> we seems to be reaching to a dead end. >> > >> >I am trying to see if the dual role USB ports can be initialized in >> coreboot/fsp so that they can act as USB2.0 for payloads. >> > >> >Thanks >> > > > -- > coreboot mailing list: coreboot(a)coreboot.org > https://www.coreboot.org/mailman/listinfo/coreboot >

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Re: [coreboot] Lenovo Thinkpad Yoga 11e (1st Gen, Win10 variant)
by John Lewis 20 Mar '17

20 Mar '17

Hi C Grossarth, Well, the Win variant will have a different EC for a start, so if you're expecting to be able to build and flash coreboot for the Chromebook variant with minimal changes, you will probably struggle. Other people will know much more what's required than I though - I just have reasonably high-level knowledge, not nuts and bolts. Regards, John. On 20/03/17 02:38, Christopher Grossarth wrote: > Hello All, > > I have been exploring coreboot, and have successfully built and > flashed it on a MacBook 2,1. Initially I was using Libreboot, but > wanted more control over the end result. > > I bought a Lenovo ChromeBook Yoga 11e 1st Gen), but swiftly returned > it after I realized the product description on Lenovo's page > mislabeled it as having SSD and RAM modules. The ChromeBook version > has eMMC and soldered on RAM. > > The Windows 10 version of the same variety (Intel Celeron N2930) has > a SSD and a replaceable/upgradeable RAM module. > The ChromeBook variant is codenamed Glimmer. > > I would like to know what steps would be necessary to build and flash > coreboot onto the Win10 board. > Most importantly, how would I go about extracting the information so > that I can edit the Glimmer config overlays to reflect the hardware > config in the Win10 variant? > > Many Thanks in advance, > > C Grossarth. > >

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Re: [coreboot] USB Support on Apollo Lake
by Gailu Singh 20 Mar '17

20 Mar '17

Hi Werner, Thanks for your detailed clarification. Looks like Intel removing various legacy interfaces and support for alternatives is yet to be developed in grub. No only they removed USB2.0 altogether, they also removed IO mapped UART and we can't get serial console working on this board either with grub. For USB I am making a last attempt to use PCIE USB2.0 card and ordered following from Aliexpress but I have serious doubts if this will work in Grub2. Will post the results once I get the cards delivered. https://www.aliexpress.com/item/Hot-New-Mini-PCI-E-Card-Slot-Expansion-to-U… Thank you very much once again. On Mon, Mar 20, 2017 at 5:18 PM, Zeh, Werner <werner.zeh(a)siemens.com> wrote: > Hi Gailu. > > I don't think that one can configure the xHCI to behave like an EHCI so > that GRUB2 can natively support it. > xHCI has different version number in the PCI space which will prevent the > EHCI driver in GRUB2 to use this controller at all. > Not speaking about the complete different register set and operational > model. > > What in turn should work is that "some of the BIOS" (which in > coreboot-context is the payload like SeaBIOS) will handle all the > xHCI stuff and provide a legacy interface to the OS (and here GRUB acts as > an OS) to just read mass storage devices using interrupts. > > Beside that you are lost with GRUB2 and xHCI, sorry! > > Werner > > >Hi Experts, > > > >Does coreboot support USB port initialization in legacy mode on Apollo > Lake as some of the BIOS does so that grub or other payloads can use it as > USB2.0? > > > >There is no USB2.0 port on this board and Grub2 doesn't support xhci so > we seems to be reaching to a dead end. > > > >I am trying to see if the dual role USB ports can be initialized in > coreboot/fsp so that they can act as USB2.0 for payloads. > > > >Thanks >

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Re: [coreboot] USB Support on Apollo Lake
by Zeh, Werner 20 Mar '17

20 Mar '17

Hi Gailu. I don't think that one can configure the xHCI to behave like an EHCI so that GRUB2 can natively support it. xHCI has different version number in the PCI space which will prevent the EHCI driver in GRUB2 to use this controller at all. Not speaking about the complete different register set and operational model. What in turn should work is that "some of the BIOS" (which in coreboot-context is the payload like SeaBIOS) will handle all the xHCI stuff and provide a legacy interface to the OS (and here GRUB acts as an OS) to just read mass storage devices using interrupts. Beside that you are lost with GRUB2 and xHCI, sorry! Werner >Hi Experts, > >Does coreboot support USB port initialization in legacy mode on Apollo Lake as some of the BIOS does so that grub or other payloads can use it as USB2.0? > >There is no USB2.0 port on this board and Grub2 doesn't support xhci so we seems to be reaching to a dead end. > >I am trying to see if the dual role USB ports can be initialized in coreboot/fsp so that they can act as USB2.0 for payloads. > >Thanks

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ASUS F2A85-M ROM Stage Behavior
by Berj K Chilingirian 20 Mar '17

20 Mar '17

Dear Coreboot Community, I am trying to understand the execution of coreboot’s ROM stage on my ASUS F2A85-M motherboard and was hoping to get your advice and guidance. I have an ASUS F2A85-M motherboard with an AMD A6-5400K processor, and a single Kingston KVR1333D3N9/2G DDR3 DIMM memory in DIMM_A2. I followed the Lesson 1 guide for building coreboot (built with the coreinfo payload) and flashed the resulting image to the appropriate BIOS chip for the F2A85-M motherboard. Because my processor was not supported I needed to add the appropriate CPU device ID in src/cpu/amd/agesa/family15tn/model_15_init.c and switch the == to != on line 255 of src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuFamilyTranslation.c (I saw this hack in a previous exchange<https://www.coreboot.org/pipermail/coreboot/2014-February/077383.html>). The resulting defconfig of the build looks like this: CONFIG_VENDOR_ASUS=y CONFIG_BOARD_ASUS_F2A85_M=y CONFIG_CONSOLE_POST=y CONFIG_PAYLOAD_ELF=y CONFIG_PAYLOAD_FILE="payloads/coreinfo/build/coreinfo.elf” I also have a serial port adapter (to USB) so that I can see the output of the coreboot process. Using this setup I am able to start up the machine with coreboot and get to the coreinfo screen (which I can then interact with). I am confused, however, by the output I am seeing from the boot process (attached). Specifically, it appears that the AmdInitReset procedure never exits, as shown below. coreboot-4.5-1349-g41dded3-dirty Mon Mar 20 03:04:09 UTC 2017 romstage starting... POST: 0x34 BSP Family_Model: 00610f21 cpu_init_detectedx = 00000000 POST: 0x37 AmdInitReset: Start *** !!AGESA cb_AgesaV0.0.0.1 *** FCH Reset Data Block Allocation: [0x0], Ptr = 0x004001e0 Fch OEM config in INIT RESET Done PCI: 00:14.4 bridge ctrl <- 0003 PCI: 00:14.4 cmd <- 00 PCI: 00:14.5 subsystem <- 1022/1410 PCI: 00:14.5 cmd <- 02 PCI: 00:15.0 bridge ctrl <- 0003 PCI: 00:15.0 cmd <- 00 PCI: 00:15.1 bridge ctrl <- 0003 … Then, procedures like AmdInitPost are never called.. How then is the memory controller and DRAM being initialized and configured? I thought this was being done by AmdInitPost but it appears it is never running this code. I am especially confused as to how coreinfo can function (and read DRAM contents) without the memory controller and DRAM being configured first.. Based on the few examples<http://pastebin.com/2Lbew82b> of outputs for F2A85-M I can find online, this output seems to be an anomaly and I’d like to understand what may be causing AmdInitReset to not end properly and the processor to never enter cache-as-ram mode in the romstage. For reference, the last commit of my coreboot source is this<https://github.com/coreboot/coreboot/commit/41dded3548327d2cb6bd8845e78b94e…> (which seems to be up-to-date at present). Thank you for any guidance you can provide on this issue; it is much appreciated! Best, Berj

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Re: [coreboot] RYZen single APU design
by Zoran Stojsavljevic 20 Mar '17

20 Mar '17

Since last 24 hours, this is the newest AMD RyZen member/sku falling of The Sky! :-) Monster AMD Ryzen 16-Core CPU Could Be On The Way: $1000 Cheaper And Faster Than Intel https://www.forbes.com/sites/antonyleather/2017/03/19/monste r-amd-ryzen-16-core-cpu-could-be-on-the-way-1000-cheaper- and-faster-than-intel/#47ce736a3d62 I just sent to AMD questions regarding this one (extra nice if Z370 would be integrated in it and make this silicon true SoC)! Exactly what I need for one of projects I am trying to boost. And if the price for single sku would be $700 USD (as they advertise), The Sky is The Limit! [image: Inline image 1] Zoran On Sat, Mar 18, 2017 at 8:05 AM, Zoran Stojsavljevic < zoran.stojsavljevic(a)gmail.com> wrote: > Hello Qmaster, Taiidan, > > Thank you for the replies. Last day (March 16th, 2017, Thursday) of > Embedded World 2017 I took the trip from Munich to Nuremberg on my own dime > (to visit EW 2017), and to speak with some people/companies I supported > previously (while being "Intel-er", you name it, the support joke), and I > had also the plan to visit AMD booth, so seconds prior I left to Munich > HBf, I sent this email, to see what community will tell. > > Interesting talks I had with AMD people. I was able to grab attention of > the most technical guy on the booth, so we had 30 minutes very productive > and lengthy conversation, since I had prepared exact requirements for so > far for implementation of the one of the US patents about efficient RAID > big data storage. > > Since I am NOT (per say) AMD guy (unfortunately, still in my sub-conscious > INTEL guy, it is (MUST) changing for the near Future), and I really would > like to embark on their technology since/including RyZen, I have learned a > lot. And what I have learned is about Naples. It is a true killer (if this > is The Truth what they say about it)! > > After returning home, that evening, I quickly re-assessed my notes, and > immediately was able to find the real video about Naples: > https://www.youtube.com/watch?v=PN93G6Rg2ek (please, watch it from 1:20) > > Naples: True SoC (integrated PCH/Chipset), has 8-channel DDR4 (3.2 GHz > clock speed) memory access, able to bring at maximum of 256GB of DDR4 > memory, has PCIe X 128 lanes (overall)... And it'll come June/July 2017 > time-frame. No signs of price tag, so far! > > And, YES, no way to get rid of AMD Chip-set. Too costly for managing Power > Management/PMIC and far fetched VRs' regulators, although I see that AMD > one is NOT so demanding as INTEL PCH (why it is so, you should ask, whom?)!? > > Thank you, > Zoran > > On Fri, Mar 17, 2017 at 1:54 AM, Taiidan(a)gmx.com <Taiidan(a)gmx.com> wrote: > >> On 03/16/2017 06:05 AM, qma ster wrote: >> >> As far as I know, AMD does not have any "evil brother" of Intel ME. It >>> only >>> has AMD PSP (Platform Secure Processor) that is built-in to CPU. So, I >>> don't think that cutting a PCH from AMD CPU has any practical value: even >>> if the platform will boot after such a radical change to computer's >>> hardware, you'll lose a lot of essential stuff like USB ports >>> >> "only has" huh? >> PSP and ME do literally the same thing and have the same capabilities, >> they're a like for like with implementation details being the only >> difference. >> > >

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coreboot March 2017