coreboot January 2017

coreboot@coreboot.org

75 participants
186 discussions

Re: [coreboot] PECI temperature in lm-sensors
by Pierre P 23 Jan '17

23 Jan '17

In my case sensors-detect found one SuperIO the first time I ran it, but there was a second one "hidden" in a i2c chip, each one provide different information. In the end I had two kernel modules loaded instead of only one previously. Pierre ________________________________ From: Аладышев Константин <aladyshev(a)nicevt.ru> Sent: Monday, January 23, 2017 4:01 PM To: 'Pierre P' Subject: Re: [coreboot] PECI temperature in lm-sensors Hi! No, "sensors-detect" founds my SuperIO and needed kernel module is installed in system correctly. The problem is in "sensors" command. It displays all voltages and pch temperatures correctly, except of PECI temperature from CPU, PECI agent temp is always zero. From: Pierre P [mailto:ppz@outlook.fr] Sent: Monday, January 23, 2017 5:40 PM To: Аладышев Константин Subject: Re: [coreboot] PECI temperature in lm-sensors Hi, Had a similar issue on a KCMA-D8. When running sensors-detect you have to force probing of i2c chips (default choice is "NO" if you just press enter when asked) then hopefully with one of them it will detect other sensors. Hope this helps Pierre ________________________________ From: coreboot <coreboot-bounces(a)coreboot.org<mailto:coreboot-bounces@coreboot.org>> on behalf of Аладышев Константин <aladyshev(a)nicevt.ru<mailto:aladyshev@nicevt.ru>> Sent: Monday, January 23, 2017 3:17 PM To: coreboot(a)coreboot.org<mailto:coreboot@coreboot.org> Subject: [coreboot] PECI temperature in lm-sensors Does someone have any experience with enabling PECI monitoring on nuvoton SuperIOs ? I'm trying to enable it on board with Haswell+Lynxpoint CPU and NCT6776 SuperIO. But all I see in lm-sensors output for now is zero temperature for PECI Agent. Does coreboot have any SuperIO chips/Intel CPUs/motherboards, that have this functional enabled? What is usually need to be done to enable PECI monitoring? -- coreboot mailing list: coreboot(a)coreboot.org<mailto:coreboot@coreboot.org> https://www.coreboot.org/mailman/listinfo/coreboot

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Re: [coreboot] Coreboot binary for ASUS F2A85-M
by Kyösti Mälkki 23 Jan '17

23 Jan '17

On Mon, Jan 23, 2017 at 2:41 PM, Maxim Gusev via coreboot < coreboot(a)coreboot.org> wrote: > Hi Daniel, > > Now I have compiled coreboot 4.5 with the SeaBIOS 1.9.3 as a payload and > the VGAbios: > I am using the Asus EN8600GT as a videocard (PCIe) and I took out the > binary here: > https://www.techpowerup.com/vgabios/?architecture=& > manufacturer=Asus&model=8600+GT&interface=PCI-E&memType=& > memSize=256&since= > > Also I have turned on in console settings "Show POST codes...", but there > is nothing works:( > You probably also need POST_DEVICE_PCI_PCIE set in your .config. In menuconfig: "Device to send POST codes to" -> "PCI/PCIe". As for the serial port: I think this mainboard is not a retail version, but came from ASUS Essentio Desktop PC CM1745. http://www.ascendtech.us/asus-f2a85-m-cm1745-dp-motherboard_i_mb90mibiw5g0x… Looks like RS232 level translator ICs are also missing and some other differences on BOM too. Kyösti

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Re: [coreboot] Coreboot binary for ASUS F2A85-M
by Daniel Kulesz 23 Jan '17

23 Jan '17

Hi Maxim, no it normally does not make any sounds, unless you have set e. g. grub to beep once its loaded. But you *need* to have a payload, otherwise nothing will boot. I suggest you try to SeaBIOS in the first instance. Also, you need to have either an external graphics cards (PCIe) or the vga bios, otherwise you also won't see anything on the screen until the point when you boot an operating system like linux which initializes the graphics. The F2A-85M *does* have a serial port soldered on the board, but there is no connector for it. You need to get a simple cable like this one and connect it to your board: https://www.quietpc.com/images/products/serial-port-pci-brackets-1-large.jpg Cheers, Daniel On Sun, 22 Jan 2017 15:33:00 -0500 Maxim Gusev <mail(a)maximgusev.com> wrote: > Hi! > I'm using Athlon x2 340. > The post card shows only 0000. Can it show something while loading? Or not... > I dont use any payloads now and no vga bios. > Also my mainboard dont have soldered serial port. > > Should the mainboard make sounds during the boot process? > Thanks! > > > > -------- Original Message -------- > Subject: Re: Coreboot binary for ASUS F2A85-M > Local Time: 20 Января 2017 г. 3:16 ночи > UTC Time: 20 Января 2017 г. 00:16 > From: daniel.ina1(a)googlemail.com > To: Maxim Gusev <mail(a)maximgusev.com> > coreboot(a)coreboot.org <coreboot(a)coreboot.org> > > Hi Max, > > I had my F2A-85M working with an A10-6700 which needed some additional tweaking because the Quadcore-CPU was causing timing issues in SeaBIOS. On my previous cpu (A4-5300) everything was fine so I suppose the same should work on your dualcore as well. > > You can find my config files (for the A10-6700) together with some logs in this commit: > > https://review.coreboot.org/cgit/board-status.git/commit/?id=947fdae2518172… > > However, I also had the issue that I didn't receive any video output unless the Linux kernel initialized the video or I plugged an PCIe GPU. I tried including the VBIOS, but were out of luck for both CPUs/APUs. > > Did you try hooking up a serial cable to see what is going on (provided you have debug instructions compiled in). > > Cheers, Daniel

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Re: [coreboot] Rangeley FSP reports "Err[24]: GetSet Value exceeds limits" during memory init
by Andy Knowles 23 Jan '17

23 Jan '17

Hi Patrick, I have an RCC-DFF from ADI. The memory is soldered down, but from their BIOS source it seems they aren’t using the FSP memory down option, so I suspect they have an EEPROM on the board with SPD data pretending to be a DIMM. I’m going to try booting it with memory down set in FSP and SPD data in coreboot instead. Thanks, Andy From: Agrain Patrick [mailto:patrick.agrain@al-enterprise.com] HI Andy, RCC-VE dev board from ADI has also memory down. It may help to compare. But unfortunately, schematics are not available. Regards, Patrick Agrain

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Quad core CPU overheat?
by Pok Gu 23 Jan '17

23 Jan '17

Hi community, Has anyone installed quad core CPUs to the thinkpad T420 experienced the issue of overheat? I have the issue with both Linux and Windows. Under Linux, when building crossgcc with all cores it may overheat and turn off the laptop. (After installed the thermald software it seems a bit better) Under Windows, when doing multipal thread java tasks it also may overheat and turn off. But is there any software that can solve this under Windows? Cheers

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Re: [coreboot] Rangeley FSP reports "Err[24]: GetSet Value exceeds limits" during memory init
by Agrain Patrick 23 Jan '17

23 Jan '17

HI Andy, RCC-VE dev board from ADI has also memory down. It may help to compare. But unfortunately, schematics are not available. Regards, Patrick Agrain De : coreboot [mailto:coreboot-bounces@coreboot.org] De la part de Andy Knowles Envoyé : lundi 23 janvier 2017 11:00 À : Zoran Stojsavljevic Cc : coreboot(a)coreboot.org Objet : Re: [coreboot] Rangeley FSP reports "Err[24]: GetSet Value exceeds limits" during memory init Hi Zoran, Thanks for responding. I have built and tested coreboot+FSP (using BCT) on a DIMM based Rangeley board without issues. Unfortunately I don’t have any other memory down based boards to test on except our own prototype. But I can try to fake memory down on the DIMM board and see if it still works. I’m waiting on a debug FSP from Intel, hopefully that will narrow down the problem on our prototype hardware. Regards, Andy From: Zoran Stojsavljevic [mailto:zoran.stojsavljevic@gmail.com] Hello Andy, I would advise to you to try the same coreboot with DIMM or SIMM INTEL Rangeley based CRB, and see if this does work, for some reason? Couple of experiments more with different CRBs with different memory configurations would not make too much headaches, don't you think? If you do not use BCT tool, the following is true. You should use Binary Configuration TOOL (BCT) to change some configuration parameters for Rangeley (you should have in Rangeley FSP package also included BCT)! As previously discussed, even though Intel FSP is a binary file, it needs a provision to customize its internal states and features; therefore, it has reserved a data region inside the binary for customization. The data area also contains a couple of platform-specific parameters that Intel FSP would otherwise have no knowledge about, or would initialize the board with default values. The Boot Setting File (BSF) plays an important role for this purpose. It is basically a text file that contains firmware internal settings associated with the board; for example, the SMBUS (System Management Bus) address of a SPD (Serial Presence Detect) ROM on a DIMM (Dual Inline Memory Module) is one of the data in the BSF. $gPlatformFspPkgTokenSpaceGuid_PcdMrcInitSPDAddr1 1 byte $_DEFAULT_ = 0xA0 $gPlatformFspPkgTokenSpaceGuid_PcdMrcInitSPDAddr2 1 byte $_DEFAULT_ = 0xA2 The data in BSF is represented in a GUI-based tool, which allows developers to visualize the meaning of each component in BSF. With the GUI and BSF, it is collectively called a Binary Configuration Tool (BCT). There are three versions of BCT: one runs under Windows, one runs under Linux, and the third is a command-line option under Linux. Please, search for the book called: Embedded Firmware Solutions [describing INTEL FSP]... And search for Chapter 3. There, everything is explicitly well explained/organized. Hope this helps, Zoran

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Re: [coreboot] Rangeley FSP reports "Err[24]: GetSet Value exceeds limits" during memory init
by Andy Knowles 23 Jan '17

23 Jan '17

Hi Zoran, Thanks for responding. I have built and tested coreboot+FSP (using BCT) on a DIMM based Rangeley board without issues. Unfortunately I don’t have any other memory down based boards to test on except our own prototype. But I can try to fake memory down on the DIMM board and see if it still works. I’m waiting on a debug FSP from Intel, hopefully that will narrow down the problem on our prototype hardware. Regards, Andy From: Zoran Stojsavljevic [mailto:zoran.stojsavljevic@gmail.com] Hello Andy, I would advise to you to try the same coreboot with DIMM or SIMM INTEL Rangeley based CRB, and see if this does work, for some reason? Couple of experiments more with different CRBs with different memory configurations would not make too much headaches, don't you think? If you do not use BCT tool, the following is true. You should use Binary Configuration TOOL (BCT) to change some configuration parameters for Rangeley (you should have in Rangeley FSP package also included BCT)! As previously discussed, even though Intel FSP is a binary file, it needs a provision to customize its internal states and features; therefore, it has reserved a data region inside the binary for customization. The data area also contains a couple of platform-specific parameters that Intel FSP would otherwise have no knowledge about, or would initialize the board with default values. The Boot Setting File (BSF) plays an important role for this purpose. It is basically a text file that contains firmware internal settings associated with the board; for example, the SMBUS (System Management Bus) address of a SPD (Serial Presence Detect) ROM on a DIMM (Dual Inline Memory Module) is one of the data in the BSF. $gPlatformFspPkgTokenSpaceGuid_PcdMrcInitSPDAddr1 1 byte $_DEFAULT_ = 0xA0 $gPlatformFspPkgTokenSpaceGuid_PcdMrcInitSPDAddr2 1 byte $_DEFAULT_ = 0xA2 The data in BSF is represented in a GUI-based tool, which allows developers to visualize the meaning of each component in BSF. With the GUI and BSF, it is collectively called a Binary Configuration Tool (BCT). There are three versions of BCT: one runs under Windows, one runs under Linux, and the third is a command-line option under Linux. Please, search for the book called: Embedded Firmware Solutions [describing INTEL FSP]... And search for Chapter 3. There, everything is explicitly well explained/organized. Hope this helps, Zoran

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Re: [coreboot] Rangeley FSP reports "Err[24]: GetSet Value exceeds limits" during memory init
by Agrain Patrick 23 Jan '17

23 Jan '17

Hello Andy, We were also facing such an issue when developing our Rangeley-based CPU board (with DIMM modules). This message was due to a wrong polarization on the DATA_MASK pin. The pb with this message is that it is displayed in every case of failure during the DDR test. A good way to reduce the possibility is to ask your Intel contact to provide you with a verbose FSP. That way, you may see at which part of the test you get the failure. Hope it helps. Best regards, Patrick Agrain De : coreboot [mailto:coreboot-bounces@coreboot.org] De la part de Zoran Stojsavljevic Envoyé : dimanche 22 janvier 2017 14:15 À : Andy Knowles Cc : coreboot(a)coreboot.org Objet : Re: [coreboot] Rangeley FSP reports "Err[24]: GetSet Value exceeds limits" during memory init Hello Andy, I would advise to you to try the same coreboot with DIMM or SIMM INTEL Rangeley based CRB, and see if this does work, for some reason? Couple of experiments more with different CRBs with different memory configurations would not make too much headaches, don't you think? If you do not use BCT tool, the following is true. You should use Binary Configuration TOOL (BCT) to change some configuration parameters for Rangeley (you should have in Rangeley FSP package also included BCT)! As previously discussed, even though Intel FSP is a binary file, it needs a provision to customize its internal states and features; therefore, it has reserved a data region inside the binary for customization. The data area also contains a couple of platform-specific parameters that Intel FSP would otherwise have no knowledge about, or would initialize the board with default values. The Boot Setting File (BSF) plays an important role for this purpose. It is basically a text file that contains firmware internal settings associated with the board; for example, the SMBUS (System Management Bus) address of a SPD (Serial Presence Detect) ROM on a DIMM (Dual Inline Memory Module) is one of the data in the BSF. $gPlatformFspPkgTokenSpaceGuid_PcdMrcInitSPDAddr1 1 byte $_DEFAULT_ = 0xA0 $gPlatformFspPkgTokenSpaceGuid_PcdMrcInitSPDAddr2 1 byte $_DEFAULT_ = 0xA2 The data in BSF is represented in a GUI-based tool, which allows developers to visualize the meaning of each component in BSF. With the GUI and BSF, it is collectively called a Binary Configuration Tool (BCT). There are three versions of BCT: one runs under Windows, one runs under Linux, and the third is a command-line option under Linux. Please, search for the book called: Embedded Firmware Solutions [describing INTEL FSP]... And search for Chapter 3. There, everything is explicitly well explained/organized. Hope this helps, Zoran On Fri, Jan 20, 2017 at 1:47 PM, Andy Knowles <aknowles(a)gallleonec.onmicrosoft.com<mailto:aknowles@gallleonec.onmicrosoft.com>> wrote: I’m trying to bring up an Intel Rangeley based prototype board using coreboot and Intel FSP. During FspInitEntry, FSP prints: Err[24]: GetSet Value exceeds limits to serial debug and halts. Does anyone know what this means? I’m using the Memory Down option in the FSP and filling in the MEM_DOWN_DIMM_CONFIG structure in mainboard/…/romstage.c I can see that the FSP is reading and validating this structure, as changing the ram speed has an effect on memory clock frequency, and if I put in invalid values the FSP will complain. I’ve tried reducing memory speed, disabling ECC, disabling channel 1 but I always get the same error. Does anyone else have any experience with Memory Down on Rangeley? Andy Knowles -- coreboot mailing list: coreboot(a)coreboot.org<mailto:coreboot@coreboot.org> https://www.coreboot.org/mailman/listinfo/coreboot

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Flash ROM access during boot
by Paul Menzel 23 Jan '17

23 Jan '17

Dear coreboot folks, Playing around with the trace feature of the Dediprog EM100Pro, I noticed several flash ROM accesses until the payload is loaded. Are there ways or strategies to preload the whole flash ROM chip content into memory for faster access right after RAM is set up for example? What does that depend on? Does that make any sense at all? Thanks, Paul

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How to quit Tint payload?
by Paul Menzel 22 Jan '17

22 Jan '17

Dear coreboot folks, Starting the Tint payload, in my case from SeaBIOS, when the game is over, the score is shown. How can I quit the payload, which probably means restart the system? Pressing ESC or Ctrl + Alt + Del don’t work. The only way I have found so far, is hitting the reset button on the mainboard. Thanks, Paul

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coreboot January 2017