coreboot January 2017

coreboot@coreboot.org

75 participants
186 discussions

Adding our company to www.coreboot.org/Products
by Kevin Keijzer 26 Jan '17

26 Jan '17

Hello, Our company [1] offers a coreboot flashing service [2] for various coreboot-supported devices. We would like to be added to https://www.coreboot.org/Products if possible. If there are any steps we have to undertake, please let us know. Thanks in advance! [1] https://www.datraverse.com/ [2] https://wiki.datraverse.com/doku.php?id=services:hardware -- With kind regards, Kevin Keijzer GNU/Linux systems administrator, Datraverse B.V. https://www.datraverse.com/

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Re: [coreboot] Coreboot binary for ASUS F2A85-M
by Maxim Gusev 26 Jan '17

26 Jan '17

It is very strange, but my keyboard doesn't work. I have tried to connect another keyboard - LEDs blinked 20 percent of cases and also diesn't work. I took your advice Martin and increased the delay (200, 500, 5000) - didn't help. cbfstool coreboot.rom add-int -i 200 -n "etc/usb-time-sigatt" Unfortunately I don't have the PS/2 keyboard:( Regards Maxim -------- Original Message -------- Subject: Re: [coreboot] Coreboot binary for ASUS F2A85-M Local Time: 24 Января 2017 г. 10:17 вечера UTC Time: 24 Января 2017 г. 19:17 From: gaumless(a)gmail.com To: Maxim Gusev <mail(a)maximgusev.com> Daniel Kulesz <daniel.ina1(a)googlemail.com>, Kyösti Mälkki <kyosti.malkki(a)gmail.com>, hackurx(a)opensec.fr <hackurx(a)opensec.fr>, coreboot(a)coreboot.org <coreboot(a)coreboot.org> Using your ROM, I'm getting USB keyboard in both grub and linux. You might try setting SeaBIOS's usb-time-sigatt to something higher than 100: https://www.seabios.org/Runtime_config "The USB2 specification requires devices to signal that they are attached within 100ms of the USB port being powered on. Some USB devices are known to require more time. Prior to receiving an attachment signal there is no way to know if a USB port is empty or if it has a device attached. One may specify an amount of time here (in milliseconds, default 100) to wait for a USB device attachment signal. Increasing this value will also increase the overall machine bootup time." Here's the command to add a 200ms wait to your rom: cbfstool coreboot.rom add-int -i 200 -n "etc/usb-time-sigatt" Martin On Tue, Jan 24, 2017 at 9:55 AM, Maxim Gusev <mail(a)maximgusev.com> wrote: > Hi, Martin, Daniel, Kyösti, Loic, > Hi, friends > > The problem was in the programmer which programmed incorrectly. > Now I see the post codes and SeaBIOS works. > Also as you mentioned, it is important to put the memory in the slot > furthest away from the processor, > I have only one memory module and otherwise the system doesn't work. > > "As was mentioned by Daniel, you don't need the external > card's VBIOS built into the rom. If you're using SeaBIOS, it will > read the vbios directly from the card." > > You are right, in this case all is working, otherwise - doesn't (shouldn't > use VGAbios from the Internet in my case). > > Now my keyboard does not work (Logitech Y-UL76). I have tried in all slots > (even using 10 pin to usb adapter). > The power seems to be there, because the mouse once blinked when it was > connected-disconnected. > Usb settings enabled in config, as I understand. Please help to fix. > > Here is my config and binary (attached to the e-mail). > Config: http://pastebin.com/BYgiLabA > > Thank you very much! > Maxim > Tried in all slots (even using adapter 10 pin usb) > > -------- Original Message -------- > Subject: Re: [coreboot] Coreboot binary for ASUS F2A85-M > Local Time: 24 Января 2017 г. 3:29 ночи > UTC Time: 24 Января 2017 г. 00:29 > From: gaumless(a)gmail.com > To: Maxim Gusev <mail(a)maximgusev.com> > Daniel Kulesz <daniel.ina1(a)googlemail.com>, coreboot(a)coreboot.org > <coreboot(a)coreboot.org> > > Hi Maxim, > Try this: Remove all of the memory in the board except for one DIMM > in the slot furthest away from the processor. AGESA on this chip has > a requirement (that some vendors apparently worked around) that DIMMs > be populated from the furthest slot to the closest. > > It looks like the code to route Port 80h to PCI isn't in that > chipset. That's something we should check before giving that option. > > As was mentioned by Daniel, you don't need (or want) the external > card's VBIOS built into the rom. If you're using SeaBIOS, it will > read the vbios directly from the card. > > If these steps don't help, I'll work with you to get a rom that boots for > you. > > Martin > > On Mon, Jan 23, 2017 at 3:12 PM, Maxim Gusev via coreboot > <coreboot(a)coreboot.org> wrote: >> Thank you for advise about pc speaker console! I will try it today. >> I am using CH341A programmer and its soft of 1.18 version. Also i am using >> the original WINBOND W25Q64BV 8mb chip. >> Yes, if I flash back the original UEFI ROM onto the chip - the system >> start >> up again. >> >> Maxim >> >> >> -------- Original Message -------- >> Subject: Re: [coreboot] Coreboot binary for ASUS F2A85-M >> Local Time: 23 Января 2017 г. 11:03 вечера >> UTC Time: 23 Января 2017 г. 20:03 >> From: daniel.ina1(a)googlemail.com >> To: Maxim Gusev <mail(a)maximgusev.com> >> coreboot(a)coreboot.org <coreboot(a)coreboot.org> >> >> My F2A85-M is currently down, so I can't test it with your config - sorry >> (but maybe in two days or so). But one more thing you could try is the pc >> speaker console: >> >> https://www.coreboot.org/Spkmodem >> >> At least, if it starts beeping this would be already a good sign. >> >> Btw.: How did you actually flash coreboot onto the chip? And did you use >> the >> original BIOS chip? If not, did you make sure your other chip is also 8M >> in >> size? If you flash back the original ROM onto the chip - does the system >> start up again? >> >> Cheers, Daniel >> >> >> On Mon, 23 Jan 2017 14:16:25 -0500 >> Maxim Gusev <mail(a)maximgusev.com> wrote: >> >>> I tried different ways to initialize the VGA card - does not work. >>> I also tried with your config file - did not work (as I remember, it was >>> further suggested in the manual mode to complete the configuration). >>> Here is my config file: http://pastebin.com/RVLcGku8 >>> I have a feeling that coreboot is programmed or read (from the spi flash) >>> to the wrong address, >>> although it is unlikely because it is, as I understand it, is written in >>> the mainboard sources, and I never touched them. >>> >>> >>> >>> >>> -------- Original Message -------- >>> Subject: Re: [coreboot] Coreboot binary for ASUS F2A85-M >>> Local Time: 23 Января 2017 г. 10:01 вечера >>> UTC Time: 23 Января 2017 г. 19:01 >>> From: daniel.ina1(a)googlemail.com >>> To: Maxim Gusev <mail(a)maximgusev.com> >>> Kyösti Mälkki <kyosti.malkki(a)gmail.com>, coreboot(a)coreboot.org >>> <coreboot(a)coreboot.org> >>> >>> On Mon, 23 Jan 2017 15:51:16 +0200 >>> Kyösti Mälkki <kyosti.malkki(a)gmail.com> wrote: >>> >>> > On Mon, Jan 23, 2017 at 2:41 PM, Maxim Gusev via coreboot < >>> > coreboot(a)coreboot.org> wrote: >>> > >>> > > Hi Daniel, >>> > > >>> > > Now I have compiled coreboot 4.5 with the SeaBIOS 1.9.3 as a payload >>> > > and >>> > > the VGAbios: >>> > > I am using the Asus EN8600GT as a videocard (PCIe) and I took out the >>> > > binary here: >>> > > https://www.techpowerup.com/vgabios/?architecture=& >>> > > manufacturer=Asus&model=8600+GT&interface=PCI-E&memType=& >>> > > memSize=256&since= >>> > > >>> >>> To my understanding, when using an external graphics card you don't need >>> to extract or put any VGA blobs in. But you need to initialize the PCIe >>> video. Can you provide us with the full config you are using, please? Or >>> did >>> you try my config which I linked in my initial answer? (There, it should >>> be >>> already enabled as far as I remember) >>> >>> > > Also I have turned on in console settings "Show POST codes...", but >>> > > there >>> > > is nothing works:( >>> > > >>> > >>> > You probably also need POST_DEVICE_PCI_PCIE set in your .config. In >>> > menuconfig: "Device to send POST codes to" -> "PCI/PCIe". >>> > >>> > As for the serial port: I think this mainboard is not a retail version, >>> > but >>> > came from ASUS Essentio Desktop PC CM1745. >>> > >>> > >>> > http://www.ascendtech.us/asus-f2a85-m-cm1745-dp-motherboard_i_mb90mibiw5g0x… >>> > >>> > Looks like RS232 level translator ICs are also missing and some other >>> > differences on BOM too. >>> > >>> >>> Indeed, there seem to be different versions of the board then. I have the >>> retail version, and mine has the connectors soldered. Can someone update >>> the >>> wiki, please? >>> >>> Cheers, Daniel >> >> >> >> -- >> coreboot mailing list: coreboot(a)coreboot.org >> https://www.coreboot.org/mailman/listinfo/coreboot > >

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Re: [coreboot] Does the 62xx Series Opteron work *securely* without microcode?
by Robert Wilkinson 26 Jan '17

26 Jan '17

On Wed, Jan 25, 2017 at 11:26:53AM -0600, Aaron Durbin via coreboot wrote: > On Wed, Jan 25, 2017 at 11:24 AM, Timothy Pearson > <tpearson(a)raptorengineering.com> wrote: > > -----BEGIN PGP SIGNED MESSAGE----- > > Hash: SHA1 > > > > On 01/24/2017 10:55 PM, Taiidan(a)gmx.com wrote: > >> I know the 63xx has a very fatal NMI exploit, but according to the > >> libreboot (oh no) website the 62xx works safely out of the box without > >> microcode however I would like to confirm if this is actually true. > >> > >> I looked at the errata .pdf from the AMD website but I didn't see > >> anything that seemed significant. > >> > >> > > > > As far as we have been able to determine it does, again with the caveat > > that this is without microcode _updates_, not without microcode. There > > is still the off chance that these CPUs ship with a backdoor inside the > > burnt microcode ROM that is patched out with an update. Unlike POWER > > and ARM we are solely dependent on the vendor being trustworthy enough > > to disclose issues in their errata document; outside of that, there is > > simply no feasible way to know for certain what bugs are lurking inside > > the CPU. > > POWER and ARM parts can have microcode too. That's up to the > implementation. I'm not sure how you can distinguish the difference. > Because one posts an update vs others never indicating there is an > update? Even if parts have no microcode, there's a possibility of > backdoors baked into the silicon. In all situations one needs to trust > the vendor. I guess that "Reflections on Trusting Trust" by Ken Thompson (https://www.ece.cmu.edu/~ganger/712.fall02/papers/p761-thompson.pdf) is still (and will always be) relevant? Bob -- BOFH excuse #62: need to wrap system in aluminum foil to fix problem

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Shrinking the ME region to make more space for CBFS
by Nathaniel Roach 25 Jan '17

25 Jan '17

Hi all! It was suggested to me that some of you on the list might be interested so I'm chucking it up here. Once you run me_cleaner in it's current revision, it's possible to trim the ME region file down to the last relevant (read: non 0xFF) byte and then shrink the region in the IFD - freeing up to about 4MiB for use in CBFS or for other things. (This means you should be able to fit a linux kernel in flash now too) I'd initially written a rough how to here: https://nroach44.id.au/index.php/2017/01/24/thinkpad-x220-shrink-the-me-reg… but since I've done some more work & some tweaks, I'm planning to re-write it when me_cleaner integrates the "minimum size" readout that makes this a bit easier. I've tested this with my X220 (which had the full 5MiB region) and, as per comments on the me_cleaner github, the 1.5MiB image from the coreboot wiki. The former shrinks to ~900K while the latter shrinks to ~300K, and there's no adverse effects to the operation of the machine. It's been tested on my X220 and github user alegru has tested it on their T420, so I'm not sure if it will work for anything !(SANDYBRIDGE).

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Re: [coreboot] How to extract fsp.bin from image?
by 김유석 책임연구원 25 Jan '17

25 Jan '17

Thank you. It is very useful to me. 2017-01-26 오전 1:45에 Andy Knowles 이(가) 쓴 글: > > Hi, > > Use the cbfstool, like so: > > build/util/cbfstool/cbfstool build/coreboot.rom extract -n fsp.bin -f > fsp.bin > > Good luck! > > Andy > > *From:*coreboot [mailto:coreboot-bounces@coreboot.org] *On Behalf Of > *??? ????? > *Sent:* Wednesday, 25 January 2017 08:43 > *To:* coreboot(a)coreboot.org > *Subject:* [coreboot] How to extract fsp.bin from image? > > Dear Sir. > > My Purpose isextract*"Intel fsp.bin"* from bios image. > > > *_First_*, (I was know that get possible "Intel fsp.bin" from Intel > website. and already download It is.) > > This time i have a some bios image. > > This one is _"ADI_RCCVE-01.00.00.08.rom"_. It is get from ADI. > > Another one is _"BIOS.bin"_. It is dump from Intel CRB. > > _This image's are perfectly support all function. ex) GbE, PCIe, *spi > flash*_ > > I was download the coreboot source from official coreboot git. > > And build this source code, It is done. > > And attach the "Intel fsp.bin" and "descriptor.bin" to my coreboot > image(It is a "official coreboot source"). > > But occured the some problem. > > *_First._*Not enable all PCIe port. But was resolved, *I was modify > the fsp.bin used by BCT.* > > *_Second._*Can't access spi flash used by "flashrom" utility. this > util can't found the spi flash on my board. > > But, If i use the "ADI_RCCVE-01.00.00.08.rom" and "Intel CRB's bios > imge" on my board, can access the spi flash memory used by "flashrom" > utility. > > So, I want to extract "Intel FSP.bin" and "descriptor.bin" from > "ADI_RCCVE-01.00.00.08.rom" and "Intel CRB's bios imge". > > I was success extract the "descriptor.bin" > > *But fail the extract "Intel fsp.bin".* > > Could help to me? > > Thank you. >

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Re: [coreboot] Does the 62xx Series Opteron work *securely* without microcode?
by Taiidan＠gmx.com 25 Jan '17

25 Jan '17

On 01/25/2017 01:35 PM, ron minnich wrote: > Tim and Aaron are right. If you have a machine with microcode updates, you > should load the updates. I have never understood the objections to > microcode blobs. If you accept the microcode that's on the machine already, > then objecting to the microcode blob is creating a distinction without a > difference. > > ron Thanks for the input guys (and yeah I meant microcode updates) I suppose this reasoning makes sense, although still though I like the idea of something working out of the box with no day one patches (with 63xx opteron, if for whatever reason updates aren't applied it is game over) I wonder if OEM's bother with meaningful security when they fab the chips to make sure they aren't messed around with...

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Add coreboot storage driver
by Guvendik, Bora 25 Jan '17

25 Jan '17

Port sdhci and mmc driver from depthcharge to coreboot. The purpose is to speed up boot time by starting storage initialization on another CPU in parallel. On the Apollolake systems we checked, we found that cpu can take up to 300ms sending CMD1s to HW, so we can avoid this delay by parallelizing. - Why not add this parallelization in the payload instead? There is potentially more time to parallelize things in coreboot. Payload execution is much faster, so we don't get much parallel execution time. - Why not send CMD1 once in coreboot to trigger power-up and let HW initialize using only 1 cpu? Jedec spec requires the CPU to keep sending CMD1s when the hardware is busy (section 6.4.3). We tested with real-world hardware and it indeed didn't work with a single CMD1. - Why did you port the driver from depthcharge? I wanted to use a driver that is proven to avoid bugs. It is also easier to apply patches back and forth. https://review.coreboot.org/#/c/18105 Thanks Bora

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ASUS KGPE-D16 Automated Test Failure [master]
by Raptor Engineering Automated Coreboot Test Stand 25 Jan '17

25 Jan '17

The ASUS KGPE-D16 fails verification for branch master as of commit dcad289841836f37ae8b885f59b80ecad690a22f The following tests failed: BOOT_FAILURE Commits since last successful test: dcad289 mb/intel/d510mo: Add cmos.layout and cmos.default 2a0e998 nb/intel/pineview: Make preallocated igd memory a cmos parameter 9bcc002 util: Add me_cleaner b144a34 libpayload: fix build See attached log for details This message was automatically generated from Raptor Engineering's ASUS KGPE-D16 test stand Want to test on your own equipment? Check out https://www.raptorengineering.com/content/REACTS/intro.html Raptor Engineering also offers coreboot consulting services! Please visit https://www.raptorengineering.com for more information Please contact Timothy Pearson at Raptor Engineering <tpearson(a)raptorengineering.com> regarding any issues stemming from this notification

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Does the 62xx Series Opteron work *securely* without microcode?
by Taiidan＠gmx.com 25 Jan '17

25 Jan '17

I know the 63xx has a very fatal NMI exploit, but according to the libreboot (oh no) website the 62xx works safely out of the box without microcode however I would like to confirm if this is actually true. I looked at the errata .pdf from the AMD website but I didn't see anything that seemed significant.

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How to extract fsp.bin from image?
by 김유석 책임연구원 25 Jan '17

25 Jan '17

Dear Sir. My Purpose isextract *"Intel fsp.bin"* from bios image. *_First_*, (I was know that get possible "Intel fsp.bin" from Intel website. and already download It is.) This time i have a some bios image. This one is _"ADI_RCCVE-01.00.00.08.rom"_. It is get from ADI. Another one is _"__BIOS.bin"_. It is dump from Intel CRB. _This image's are per__fectly __support all function.____ex) GbE, PCIe, _*_spi flash_* I was download the coreboot source from official coreboot git. And build this source code, It is done. And attach the "Intel fsp.bin" and "descriptor.bin" to my coreboot image(It is a "official coreboot source"). But occured the some problem. *_First_**_._* Not enable all PCIe port. But was resolved, *I was modify the fsp.bin use**d by BCT.* _*Second.*_ Can't access spi flash used by "flashrom" utility. this util can't found the spi flash on my board. But, If i use the "ADI_RCCVE-01.00.00.08.rom" and "Intel CRB's bios imge" on my board, can access the spi flash memory used by "flashrom" utility. So, I want to extract "Intel FSP.bin" and "descriptor.bin" from "ADI_RCCVE-01.00.00.08.rom" and "Intel CRB's bios imge". I was success extract the "descriptor.bin" *But fail the extract "Intel fsp.bin".* Could help to me? Thank you.

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coreboot January 2017