coreboot January 2017

coreboot@coreboot.org

75 participants
186 discussions

Re: [coreboot] SMBIOS table enablement in coreboot
by Mayuri Tendulkar 25 Jan '17

25 Jan '17

We are using coreboot 4.4 only, because when I do dmidecode – t 0, its showing me bios version as 4.4-573. Still type 17 doesn’t come up. How we can access DIMM information from HOB? From: cheng yichen [mailto:blessyichen@gmail.com] Sent: 25 January 2017 15:35 To: Mayuri Tendulkar <mayuri.tendulkar(a)aricent.com> Cc: David Hendricks <dhendrix(a)google.com>; coreboot <coreboot(a)coreboot.org> Subject: Re: [coreboot] SMBIOS table enablement in coreboot Hi Mayuri I have the same question with braswell coreboot that the source code is got from intel. Intel source code don't implement smbios type 17. but you can get dimm information in HOB that is created in FSB image. If you use coreboot4.4 for your bay trail platform. I think the type 17 is created. Thank you 2017-01-25 17:48 GMT+08:00 Mayuri Tendulkar <mayuri.tendulkar(a)aricent.com<mailto:mayuri.tendulkar@aricent.com>>: Hi David Thanks for response. So are there any other settings which enable Type 17 i.e. DDR data information in SMBIOS? We don’t see this Type 17 information in our table. Regards Mayuri From: David Hendricks [mailto:dhendrix@google.com<mailto:dhendrix@google.com>] Sent: 18 January 2017 01:58 To: Mayuri Tendulkar <mayuri.tendulkar(a)aricent.com<mailto:mayuri.tendulkar@aricent.com>> Cc: coreboot <coreboot(a)coreboot.org<mailto:coreboot@coreboot.org>> Subject: Re: [coreboot] SMBIOS table enablement in coreboot Hi Mayuri, On Sun, Jan 15, 2017 at 5:40 PM, Mayuri Tendulkar <mayuri.tendulkar(a)aricent.com<mailto:mayuri.tendulkar@aricent.com>> wrote: Hi David Yes, below are settings for our system. As we are using Intel Baytrail, does this SMBIOS manufacturer shd be Intel? That's up to you. Mainboard manufacturer, along with product name, serial number, and version, are strings which are expected to be assigned by the vendor. You may set these in your mainboard's Kconfig file. The Macbook 2.1 port shows an example of how to do this: https://review.coreboot.org/cgit/coreboot.git/tree/src/mainboard/apple/macb…. Other SMBIOS tables such as memory info is generated automatically by coreboot. For example, the type 4 table should have details about your processor manufacturer (Intel) as well as information which implies Baytrail (CPU family, model, and stepping). CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="xxxxx" # CONFIG_SMBIOS_PROVIDED_BY_MOBO is not set CONFIG_GENERATE_SMBIOS_TABLES=y CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="yyyy" Regards Mayuri From: David Hendricks [mailto:dhendrix@google.com<mailto:dhendrix@google.com>] Sent: 14 January 2017 08:19 To: Mayuri Tendulkar <mayuri.tendulkar(a)aricent.com<mailto:mayuri.tendulkar@aricent.com>> Cc: coreboot <coreboot(a)coreboot.org<mailto:coreboot@coreboot.org>> Subject: Re: [coreboot] SMBIOS table enablement in coreboot Hi Mayuri, Do you have GENERATE_SMBIOS_TABLES enabled in your config? On Fri, Jan 13, 2017 at 12:56 AM, Mayuri Tendulkar <mayuri.tendulkar(a)aricent.com<mailto:mayuri.tendulkar@aricent.com>> wrote: Hi We are using coreboot for our board based on Intel Baytrail 3845. When we use dmidecode –t to get DDR details, we get empty. It means data is missing in SMBIOS. Are there any settings in coreboot to enable this? Regards Mayuri "DISCLAIMER: This message is proprietary to Aricent and is intended solely for the use of the individual to whom it is addressed. It may contain privileged or confidential information and should not be circulated or used for any purpose other than for what it is intended. If you have received this message in error, please notify the originator immediately. If you are not the intended recipient, you are notified that you are strictly prohibited from using, copying, altering, or disclosing the contents of this message. Aricent accepts no responsibility for loss or damage arising from the use of the information transmitted by this email including damage from virus." -- coreboot mailing list: coreboot(a)coreboot.org<mailto:coreboot@coreboot.org> https://www.coreboot.org/mailman/listinfo/coreboot -- David Hendricks (dhendrix) Systems Software Engineer, Google Inc. "DISCLAIMER: This message is proprietary to Aricent and is intended solely for the use of the individual to whom it is addressed. It may contain privileged or confidential information and should not be circulated or used for any purpose other than for what it is intended. If you have received this message in error, please notify the originator immediately. If you are not the intended recipient, you are notified that you are strictly prohibited from using, copying, altering, or disclosing the contents of this message. Aricent accepts no responsibility for loss or damage arising from the use of the information transmitted by this email including damage from virus." -- David Hendricks (dhendrix) Systems Software Engineer, Google Inc. "DISCLAIMER: This message is proprietary to Aricent and is intended solely for the use of the individual to whom it is addressed. It may contain privileged or confidential information and should not be circulated or used for any purpose other than for what it is intended. If you have received this message in error, please notify the originator immediately. If you are not the intended recipient, you are notified that you are strictly prohibited from using, copying, altering, or disclosing the contents of this message. Aricent accepts no responsibility for loss or damage arising from the use of the information transmitted by this email including damage from virus." -- coreboot mailing list: coreboot(a)coreboot.org<mailto:coreboot@coreboot.org> https://www.coreboot.org/mailman/listinfo/coreboot "DISCLAIMER: This message is proprietary to Aricent and is intended solely for the use of the individual to whom it is addressed. It may contain privileged or confidential information and should not be circulated or used for any purpose other than for what it is intended. If you have received this message in error, please notify the originator immediately. If you are not the intended recipient, you are notified that you are strictly prohibited from using, copying, altering, or disclosing the contents of this message. Aricent accepts no responsibility for loss or damage arising from the use of the information transmitted by this email including damage from virus."

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Re: [coreboot] SMBIOS table enablement in coreboot
by cheng yichen 25 Jan '17

25 Jan '17

Hi Mayuri I have the same question with braswell coreboot that the source code is got from intel. Intel source code don't implement smbios type 17. but you can get dimm information in HOB that is created in FSB image. If you use coreboot4.4 for your bay trail platform. I think the type 17 is created. Thank you 2017-01-25 17:48 GMT+08:00 Mayuri Tendulkar <mayuri.tendulkar(a)aricent.com>: > Hi David > > > > Thanks for response. > > > > So are there any other settings which enable Type 17 i.e. DDR data > information in SMBIOS? > > > > We don’t see this Type 17 information in our table. > > > > Regards > > Mayuri > > > > *From:* David Hendricks [mailto:dhendrix@google.com] > *Sent:* 18 January 2017 01:58 > > *To:* Mayuri Tendulkar <mayuri.tendulkar(a)aricent.com> > *Cc:* coreboot <coreboot(a)coreboot.org> > *Subject:* Re: [coreboot] SMBIOS table enablement in coreboot > > > > Hi Mayuri, > > > > On Sun, Jan 15, 2017 at 5:40 PM, Mayuri Tendulkar < > mayuri.tendulkar(a)aricent.com> wrote: > > Hi David > > > > Yes, below are settings for our system. As we are using Intel Baytrail, > does this SMBIOS manufacturer shd be Intel? > > > > That's up to you. Mainboard manufacturer, along with product name, serial > number, and version, are strings which are expected to be assigned by the > vendor. You may set these in your mainboard's Kconfig file. The Macbook 2.1 > port shows an example of how to do this: https://review.coreboot.org/ > cgit/coreboot.git/tree/src/mainboard/apple/macbook21/Kconfig#n32. > > > > Other SMBIOS tables such as memory info is generated automatically by > coreboot. For example, the type 4 table should have details about your > processor manufacturer (Intel) as well as information which implies > Baytrail (CPU family, model, and stepping). > > > > > > CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="xxxxx" > > # CONFIG_SMBIOS_PROVIDED_BY_MOBO is not set > > CONFIG_GENERATE_SMBIOS_TABLES=y > > CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="yyyy" > > > > Regards > > Mayuri > > > > *From:* David Hendricks [mailto:dhendrix@google.com] > *Sent:* 14 January 2017 08:19 > *To:* Mayuri Tendulkar <mayuri.tendulkar(a)aricent.com> > *Cc:* coreboot <coreboot(a)coreboot.org> > *Subject:* Re: [coreboot] SMBIOS table enablement in coreboot > > > > Hi Mayuri, > > Do you have GENERATE_SMBIOS_TABLES enabled in your config? > > > > On Fri, Jan 13, 2017 at 12:56 AM, Mayuri Tendulkar < > mayuri.tendulkar(a)aricent.com> wrote: > > Hi > > We are using coreboot for our board based on Intel Baytrail 3845. > > > > When we use *dmidecode –t *to get DDR details, we get empty. It means > data is missing in SMBIOS. > > > > Are there any settings in coreboot to enable this? > > > > Regards > > Mayuri > > "DISCLAIMER: This message is proprietary to Aricent and is intended solely > for the use of the individual to whom it is addressed. It may contain > privileged or confidential information and should not be circulated or used > for any purpose other than for what it is intended. If you have received > this message in error, please notify the originator immediately. If you are > not the intended recipient, you are notified that you are strictly > prohibited from using, copying, altering, or disclosing the contents of > this message. Aricent accepts no responsibility for loss or damage arising > from the use of the information transmitted by this email including damage > from virus." > > > -- > coreboot mailing list: coreboot(a)coreboot.org > https://www.coreboot.org/mailman/listinfo/coreboot > > > > > > -- > > David Hendricks (dhendrix) > Systems Software Engineer, Google Inc. > > "DISCLAIMER: This message is proprietary to Aricent and is intended solely > for the use of the individual to whom it is addressed. It may contain > privileged or confidential information and should not be circulated or used > for any purpose other than for what it is intended. If you have received > this message in error, please notify the originator immediately. If you are > not the intended recipient, you are notified that you are strictly > prohibited from using, copying, altering, or disclosing the contents of > this message. Aricent accepts no responsibility for loss or damage arising > from the use of the information transmitted by this email including damage > from virus." > > > > > > -- > > David Hendricks (dhendrix) > Systems Software Engineer, Google Inc. > "DISCLAIMER: This message is proprietary to Aricent and is intended solely > for the use of the individual to whom it is addressed. It may contain > privileged or confidential information and should not be circulated or used > for any purpose other than for what it is intended. If you have received > this message in error, please notify the originator immediately. If you are > not the intended recipient, you are notified that you are strictly > prohibited from using, copying, altering, or disclosing the contents of > this message. Aricent accepts no responsibility for loss or damage arising > from the use of the information transmitted by this email including damage > from virus." > > -- > coreboot mailing list: coreboot(a)coreboot.org > https://www.coreboot.org/mailman/listinfo/coreboot >

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Re: [coreboot] SMBIOS table enablement in coreboot
by Mayuri Tendulkar 25 Jan '17

25 Jan '17

Hi David Thanks for response. So are there any other settings which enable Type 17 i.e. DDR data information in SMBIOS? We don’t see this Type 17 information in our table. Regards Mayuri From: David Hendricks [mailto:dhendrix@google.com] Sent: 18 January 2017 01:58 To: Mayuri Tendulkar <mayuri.tendulkar(a)aricent.com> Cc: coreboot <coreboot(a)coreboot.org> Subject: Re: [coreboot] SMBIOS table enablement in coreboot Hi Mayuri, On Sun, Jan 15, 2017 at 5:40 PM, Mayuri Tendulkar <mayuri.tendulkar(a)aricent.com<mailto:mayuri.tendulkar@aricent.com>> wrote: Hi David Yes, below are settings for our system. As we are using Intel Baytrail, does this SMBIOS manufacturer shd be Intel? That's up to you. Mainboard manufacturer, along with product name, serial number, and version, are strings which are expected to be assigned by the vendor. You may set these in your mainboard's Kconfig file. The Macbook 2.1 port shows an example of how to do this: https://review.coreboot.org/cgit/coreboot.git/tree/src/mainboard/apple/macb…. Other SMBIOS tables such as memory info is generated automatically by coreboot. For example, the type 4 table should have details about your processor manufacturer (Intel) as well as information which implies Baytrail (CPU family, model, and stepping). CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="xxxxx" # CONFIG_SMBIOS_PROVIDED_BY_MOBO is not set CONFIG_GENERATE_SMBIOS_TABLES=y CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="yyyy" Regards Mayuri From: David Hendricks [mailto:dhendrix@google.com<mailto:dhendrix@google.com>] Sent: 14 January 2017 08:19 To: Mayuri Tendulkar <mayuri.tendulkar(a)aricent.com<mailto:mayuri.tendulkar@aricent.com>> Cc: coreboot <coreboot(a)coreboot.org<mailto:coreboot@coreboot.org>> Subject: Re: [coreboot] SMBIOS table enablement in coreboot Hi Mayuri, Do you have GENERATE_SMBIOS_TABLES enabled in your config? On Fri, Jan 13, 2017 at 12:56 AM, Mayuri Tendulkar <mayuri.tendulkar(a)aricent.com<mailto:mayuri.tendulkar@aricent.com>> wrote: Hi We are using coreboot for our board based on Intel Baytrail 3845. When we use dmidecode –t to get DDR details, we get empty. It means data is missing in SMBIOS. Are there any settings in coreboot to enable this? Regards Mayuri "DISCLAIMER: This message is proprietary to Aricent and is intended solely for the use of the individual to whom it is addressed. It may contain privileged or confidential information and should not be circulated or used for any purpose other than for what it is intended. If you have received this message in error, please notify the originator immediately. If you are not the intended recipient, you are notified that you are strictly prohibited from using, copying, altering, or disclosing the contents of this message. Aricent accepts no responsibility for loss or damage arising from the use of the information transmitted by this email including damage from virus." -- coreboot mailing list: coreboot(a)coreboot.org<mailto:coreboot@coreboot.org> https://www.coreboot.org/mailman/listinfo/coreboot -- David Hendricks (dhendrix) Systems Software Engineer, Google Inc. "DISCLAIMER: This message is proprietary to Aricent and is intended solely for the use of the individual to whom it is addressed. It may contain privileged or confidential information and should not be circulated or used for any purpose other than for what it is intended. If you have received this message in error, please notify the originator immediately. If you are not the intended recipient, you are notified that you are strictly prohibited from using, copying, altering, or disclosing the contents of this message. Aricent accepts no responsibility for loss or damage arising from the use of the information transmitted by this email including damage from virus." -- David Hendricks (dhendrix) Systems Software Engineer, Google Inc. "DISCLAIMER: This message is proprietary to Aricent and is intended solely for the use of the individual to whom it is addressed. It may contain privileged or confidential information and should not be circulated or used for any purpose other than for what it is intended. If you have received this message in error, please notify the originator immediately. If you are not the intended recipient, you are notified that you are strictly prohibited from using, copying, altering, or disclosing the contents of this message. Aricent accepts no responsibility for loss or damage arising from the use of the information transmitted by this email including damage from virus."

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payload build failure
by chitgope raghuveer 25 Jan '17

25 Jan '17

Hello, I am facing the below failure while attempting to build the payload-coreinfo. make: Entering directory '/home/raghuveer/CodeBase/coreboot/payloads/coreinfo' Building libpayload @ /home/raghuveer/CodeBase/coreboot/payloads/libpayload. *** Default configuration is based on 'configs/defconfig-tinycurses' # # configuration written to /home/raghuveer/CodeBase/coreboot/payloads/coreinfo/lp.config # # # configuration written to /home/raghuveer/CodeBase/coreboot/payloads/coreinfo/lp.config # CC libpci/libpci.libpci.o make[1]: MMD: Command not found AR /home/raghuveer/CodeBase/coreboot/payloads/coreinfo/lpbuild/libpci.a make[1]: rc: Command not found Makefile.inc:89: recipe for target '/home/raghuveer/CodeBase/coreboot/payloads/coreinfo/lpbuild/libpci.a' failed make[1]: *** [/home/raghuveer/CodeBase/coreboot/payloads/coreinfo/lpbuild/libpci.a] Error 127 Makefile:121: recipe for target 'libpayload' failed make: *** [libpayload] Error 2 make: Leaving directory '/home/raghuveer/CodeBase/coreboot/payloads/coreinfo' -- Raghuveer Chitgope.

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Re: [coreboot] Coreboot binary for ASUS F2A85-M
by Martin Roth 24 Jan '17

24 Jan '17

Using your ROM, I'm getting USB keyboard in both grub and linux. You might try setting SeaBIOS's usb-time-sigatt to something higher than 100: https://www.seabios.org/Runtime_config "The USB2 specification requires devices to signal that they are attached within 100ms of the USB port being powered on. Some USB devices are known to require more time. Prior to receiving an attachment signal there is no way to know if a USB port is empty or if it has a device attached. One may specify an amount of time here (in milliseconds, default 100) to wait for a USB device attachment signal. Increasing this value will also increase the overall machine bootup time." Here's the command to add a 200ms wait to your rom: cbfstool coreboot.rom add-int -i 200 -n "etc/usb-time-sigatt" Martin On Tue, Jan 24, 2017 at 9:55 AM, Maxim Gusev <mail(a)maximgusev.com> wrote: > Hi, Martin, Daniel, Kyösti, Loic, > Hi, friends > > The problem was in the programmer which programmed incorrectly. > Now I see the post codes and SeaBIOS works. > Also as you mentioned, it is important to put the memory in the slot > furthest away from the processor, > I have only one memory module and otherwise the system doesn't work. > > "As was mentioned by Daniel, you don't need the external > card's VBIOS built into the rom. If you're using SeaBIOS, it will > read the vbios directly from the card." > > You are right, in this case all is working, otherwise - doesn't (shouldn't > use VGAbios from the Internet in my case). > > Now my keyboard does not work (Logitech Y-UL76). I have tried in all slots > (even using 10 pin to usb adapter). > The power seems to be there, because the mouse once blinked when it was > connected-disconnected. > Usb settings enabled in config, as I understand. Please help to fix. > > Here is my config and binary (attached to the e-mail). > Config: http://pastebin.com/BYgiLabA > > Thank you very much! > Maxim > Tried in all slots (even using adapter 10 pin usb) > > -------- Original Message -------- > Subject: Re: [coreboot] Coreboot binary for ASUS F2A85-M > Local Time: 24 Января 2017 г. 3:29 ночи > UTC Time: 24 Января 2017 г. 00:29 > From: gaumless(a)gmail.com > To: Maxim Gusev <mail(a)maximgusev.com> > Daniel Kulesz <daniel.ina1(a)googlemail.com>, coreboot(a)coreboot.org > <coreboot(a)coreboot.org> > > Hi Maxim, > Try this: Remove all of the memory in the board except for one DIMM > in the slot furthest away from the processor. AGESA on this chip has > a requirement (that some vendors apparently worked around) that DIMMs > be populated from the furthest slot to the closest. > > It looks like the code to route Port 80h to PCI isn't in that > chipset. That's something we should check before giving that option. > > As was mentioned by Daniel, you don't need (or want) the external > card's VBIOS built into the rom. If you're using SeaBIOS, it will > read the vbios directly from the card. > > If these steps don't help, I'll work with you to get a rom that boots for > you. > > Martin > > On Mon, Jan 23, 2017 at 3:12 PM, Maxim Gusev via coreboot > <coreboot(a)coreboot.org> wrote: >> Thank you for advise about pc speaker console! I will try it today. >> I am using CH341A programmer and its soft of 1.18 version. Also i am using >> the original WINBOND W25Q64BV 8mb chip. >> Yes, if I flash back the original UEFI ROM onto the chip - the system >> start >> up again. >> >> Maxim >> >> >> -------- Original Message -------- >> Subject: Re: [coreboot] Coreboot binary for ASUS F2A85-M >> Local Time: 23 Января 2017 г. 11:03 вечера >> UTC Time: 23 Января 2017 г. 20:03 >> From: daniel.ina1(a)googlemail.com >> To: Maxim Gusev <mail(a)maximgusev.com> >> coreboot(a)coreboot.org <coreboot(a)coreboot.org> >> >> My F2A85-M is currently down, so I can't test it with your config - sorry >> (but maybe in two days or so). But one more thing you could try is the pc >> speaker console: >> >> https://www.coreboot.org/Spkmodem >> >> At least, if it starts beeping this would be already a good sign. >> >> Btw.: How did you actually flash coreboot onto the chip? And did you use >> the >> original BIOS chip? If not, did you make sure your other chip is also 8M >> in >> size? If you flash back the original ROM onto the chip - does the system >> start up again? >> >> Cheers, Daniel >> >> >> On Mon, 23 Jan 2017 14:16:25 -0500 >> Maxim Gusev <mail(a)maximgusev.com> wrote: >> >>> I tried different ways to initialize the VGA card - does not work. >>> I also tried with your config file - did not work (as I remember, it was >>> further suggested in the manual mode to complete the configuration). >>> Here is my config file: http://pastebin.com/RVLcGku8 >>> I have a feeling that coreboot is programmed or read (from the spi flash) >>> to the wrong address, >>> although it is unlikely because it is, as I understand it, is written in >>> the mainboard sources, and I never touched them. >>> >>> >>> >>> >>> -------- Original Message -------- >>> Subject: Re: [coreboot] Coreboot binary for ASUS F2A85-M >>> Local Time: 23 Января 2017 г. 10:01 вечера >>> UTC Time: 23 Января 2017 г. 19:01 >>> From: daniel.ina1(a)googlemail.com >>> To: Maxim Gusev <mail(a)maximgusev.com> >>> Kyösti Mälkki <kyosti.malkki(a)gmail.com>, coreboot(a)coreboot.org >>> <coreboot(a)coreboot.org> >>> >>> On Mon, 23 Jan 2017 15:51:16 +0200 >>> Kyösti Mälkki <kyosti.malkki(a)gmail.com> wrote: >>> >>> > On Mon, Jan 23, 2017 at 2:41 PM, Maxim Gusev via coreboot < >>> > coreboot(a)coreboot.org> wrote: >>> > >>> > > Hi Daniel, >>> > > >>> > > Now I have compiled coreboot 4.5 with the SeaBIOS 1.9.3 as a payload >>> > > and >>> > > the VGAbios: >>> > > I am using the Asus EN8600GT as a videocard (PCIe) and I took out the >>> > > binary here: >>> > > https://www.techpowerup.com/vgabios/?architecture=& >>> > > manufacturer=Asus&model=8600+GT&interface=PCI-E&memType=& >>> > > memSize=256&since= >>> > > >>> >>> To my understanding, when using an external graphics card you don't need >>> to extract or put any VGA blobs in. But you need to initialize the PCIe >>> video. Can you provide us with the full config you are using, please? Or >>> did >>> you try my config which I linked in my initial answer? (There, it should >>> be >>> already enabled as far as I remember) >>> >>> > > Also I have turned on in console settings "Show POST codes...", but >>> > > there >>> > > is nothing works:( >>> > > >>> > >>> > You probably also need POST_DEVICE_PCI_PCIE set in your .config. In >>> > menuconfig: "Device to send POST codes to" -> "PCI/PCIe". >>> > >>> > As for the serial port: I think this mainboard is not a retail version, >>> > but >>> > came from ASUS Essentio Desktop PC CM1745. >>> > >>> > >>> > http://www.ascendtech.us/asus-f2a85-m-cm1745-dp-motherboard_i_mb90mibiw5g0x… >>> > >>> > Looks like RS232 level translator ICs are also missing and some other >>> > differences on BOM too. >>> > >>> >>> Indeed, there seem to be different versions of the board then. I have the >>> retail version, and mine has the connectors soldered. Can someone update >>> the >>> wiki, please? >>> >>> Cheers, Daniel >> >> >> >> -- >> coreboot mailing list: coreboot(a)coreboot.org >> https://www.coreboot.org/mailman/listinfo/coreboot > >

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ASUS KFSN4-DRE Automated Test Failure [master]
by Raptor Engineering Automated Coreboot Test Stand 24 Jan '17

24 Jan '17

The ASUS KFSN4-DRE fails verification for branch master as of commit 0f6d10ba8f8f711f2ff7fa5c8f306e18a42b8974 The following tests failed: BOOT_FAILURE Commits since last successful test: 0f6d10b google/pyro: Update DPTF settings See attached log for details This message was automatically generated from Raptor Engineering's ASUS KFSN4-DRE test stand Want to test on your own equipment? Check out https://www.raptorengineering.com/content/REACTS/intro.html Raptor Engineering also offers coreboot consulting services! Please visit https://www.raptorengineering.com for more information Please contact Timothy Pearson at Raptor Engineering <tpearson(a)raptorengineering.com> regarding any issues stemming from this notification

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Re: [coreboot] Coreboot binary for ASUS F2A85-M
by Maxim Gusev 24 Jan '17

24 Jan '17

Hi, Martin, Daniel, Kyösti, Loic, Hi, friends The problem was in the programmer which programmed incorrectly. Now I see the post codes and SeaBIOS works. Also as you mentioned, it is important to put the memory in the slot furthest away from the processor, I have only one memory module and otherwise the system doesn't work. "As was mentioned by Daniel, you don't need the external card's VBIOS built into the rom. If you're using SeaBIOS, it will read the vbios directly from the card." You are right, in this case all is working, otherwise - doesn't (shouldn't use VGAbios from the Internet in my case). Now my keyboard does not work (Logitech Y-UL76). I have tried in all slots (even using 10 pin to usb adapter). The power seems to be there, because the mouse once blinked when it was connected-disconnected. Usb settings enabled in config, as I understand. Please help to fix. Here is my config and binary (attached to the e-mail). Config: http://pastebin.com/BYgiLabA Thank you very much! Maxim Tried in all slots (even using adapter 10 pin usb) -------- Original Message -------- Subject: Re: [coreboot] Coreboot binary for ASUS F2A85-M Local Time: 24 Января 2017 г. 3:29 ночи UTC Time: 24 Января 2017 г. 00:29 From: gaumless(a)gmail.com To: Maxim Gusev <mail(a)maximgusev.com> Daniel Kulesz <daniel.ina1(a)googlemail.com>, coreboot(a)coreboot.org <coreboot(a)coreboot.org> Hi Maxim, Try this: Remove all of the memory in the board except for one DIMM in the slot furthest away from the processor. AGESA on this chip has a requirement (that some vendors apparently worked around) that DIMMs be populated from the furthest slot to the closest. It looks like the code to route Port 80h to PCI isn't in that chipset. That's something we should check before giving that option. As was mentioned by Daniel, you don't need (or want) the external card's VBIOS built into the rom. If you're using SeaBIOS, it will read the vbios directly from the card. If these steps don't help, I'll work with you to get a rom that boots for you. Martin On Mon, Jan 23, 2017 at 3:12 PM, Maxim Gusev via coreboot <coreboot(a)coreboot.org> wrote: > Thank you for advise about pc speaker console! I will try it today. > I am using CH341A programmer and its soft of 1.18 version. Also i am using > the original WINBOND W25Q64BV 8mb chip. > Yes, if I flash back the original UEFI ROM onto the chip - the system start > up again. > > Maxim > > > -------- Original Message -------- > Subject: Re: [coreboot] Coreboot binary for ASUS F2A85-M > Local Time: 23 Января 2017 г. 11:03 вечера > UTC Time: 23 Января 2017 г. 20:03 > From: daniel.ina1(a)googlemail.com > To: Maxim Gusev <mail(a)maximgusev.com> > coreboot(a)coreboot.org <coreboot(a)coreboot.org> > > My F2A85-M is currently down, so I can't test it with your config - sorry > (but maybe in two days or so). But one more thing you could try is the pc > speaker console: > > https://www.coreboot.org/Spkmodem > > At least, if it starts beeping this would be already a good sign. > > Btw.: How did you actually flash coreboot onto the chip? And did you use the > original BIOS chip? If not, did you make sure your other chip is also 8M in > size? If you flash back the original ROM onto the chip - does the system > start up again? > > Cheers, Daniel > > > On Mon, 23 Jan 2017 14:16:25 -0500 > Maxim Gusev <mail(a)maximgusev.com> wrote: > >> I tried different ways to initialize the VGA card - does not work. >> I also tried with your config file - did not work (as I remember, it was >> further suggested in the manual mode to complete the configuration). >> Here is my config file: http://pastebin.com/RVLcGku8 >> I have a feeling that coreboot is programmed or read (from the spi flash) >> to the wrong address, >> although it is unlikely because it is, as I understand it, is written in >> the mainboard sources, and I never touched them. >> >> >> >> >> -------- Original Message -------- >> Subject: Re: [coreboot] Coreboot binary for ASUS F2A85-M >> Local Time: 23 Января 2017 г. 10:01 вечера >> UTC Time: 23 Января 2017 г. 19:01 >> From: daniel.ina1(a)googlemail.com >> To: Maxim Gusev <mail(a)maximgusev.com> >> Kyösti Mälkki <kyosti.malkki(a)gmail.com>, coreboot(a)coreboot.org >> <coreboot(a)coreboot.org> >> >> On Mon, 23 Jan 2017 15:51:16 +0200 >> Kyösti Mälkki <kyosti.malkki(a)gmail.com> wrote: >> >> > On Mon, Jan 23, 2017 at 2:41 PM, Maxim Gusev via coreboot < >> > coreboot(a)coreboot.org> wrote: >> > >> > > Hi Daniel, >> > > >> > > Now I have compiled coreboot 4.5 with the SeaBIOS 1.9.3 as a payload >> > > and >> > > the VGAbios: >> > > I am using the Asus EN8600GT as a videocard (PCIe) and I took out the >> > > binary here: >> > > https://www.techpowerup.com/vgabios/?architecture=& >> > > manufacturer=Asus&model=8600+GT&interface=PCI-E&memType=& >> > > memSize=256&since= >> > > >> >> To my understanding, when using an external graphics card you don't need >> to extract or put any VGA blobs in. But you need to initialize the PCIe >> video. Can you provide us with the full config you are using, please? Or did >> you try my config which I linked in my initial answer? (There, it should be >> already enabled as far as I remember) >> >> > > Also I have turned on in console settings "Show POST codes...", but >> > > there >> > > is nothing works:( >> > > >> > >> > You probably also need POST_DEVICE_PCI_PCIE set in your .config. In >> > menuconfig: "Device to send POST codes to" -> "PCI/PCIe". >> > >> > As for the serial port: I think this mainboard is not a retail version, >> > but >> > came from ASUS Essentio Desktop PC CM1745. >> > >> > http://www.ascendtech.us/asus-f2a85-m-cm1745-dp-motherboard_i_mb90mibiw5g0x… >> > >> > Looks like RS232 level translator ICs are also missing and some other >> > differences on BOM too. >> > >> >> Indeed, there seem to be different versions of the board then. I have the >> retail version, and mine has the connectors soldered. Can someone update the >> wiki, please? >> >> Cheers, Daniel > > > > -- > coreboot mailing list: coreboot(a)coreboot.org > https://www.coreboot.org/mailman/listinfo/coreboot

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docs about porting new arch
by Le Likele 24 Jan '17

24 Jan '17

Hello! I would like to port a new architecture to the coreboot. I have found a brief documentation about porting a new board or a new SoC. https://www.coreboot.org/git-docs/Intel/SoC/soc.html https://www.coreboot.org/git-docs/Intel/Board/board.html Is there the same docs about adding a new architecture to the coreboot? Thank you!

1 0

PECI temperature in lm-sensors
by Аладышев Константин 24 Jan '17

24 Jan '17

Does someone have any experience with enabling PECI monitoring on nuvoton SuperIOs ? I'm trying to enable it on board with Haswell+Lynxpoint CPU and NCT6776 SuperIO. But all I see in lm-sensors output for now is zero temperature for PECI Agent. Does coreboot have any SuperIO chips/Intel CPUs/motherboards, that have this functional enabled? What is usually need to be done to enable PECI monitoring?

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Re: [coreboot] Compiling coreboot with libgfxinit
by Nico Huber 24 Jan '17

24 Jan '17

Hi Mihail, On 24.01.2017 11:35, Mihail Tommonen wrote: > Hello Everyone, > > My intention is to get libgfxinit to work with Lenovo X230, but first > I'm trying to get it compiled for KONTRON KTQM77 as its seems to be > only board atm that has feature enabled in configs. > > Unfortunately I get a tons of "hw-time.ads:23:07: "Volatile_Function" > is not a valid aspect identifier" errors [1] while compling. sorry for that. It's a known problem (I was hoping to get the toolchain updated before anybody runs into this). Here's the fix[4], you can just remove all the `Volatile_Function` since it doesn't affect compilation. After applying, you have to put 3rdparty/libhwbase on the git index in the coreboot repo to prevent it from being reset on the next build. > > Because I do not have any experience with ada I'm not sure what to > blame: my toolchain or the code. Blame me. Nico [4] https://review.coreboot.org/#/c/17705/ > > What I did so far [2] and config file [3]. > > Does anyone have any clue what is the problem? > > Thanks, > > Mihail Tommonen > > > [1]http://paste.debian.net/910254/ > [2]http://paste.debian.net/910264/ > [3]http://paste.debian.net/910257/ >

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coreboot January 2017