coreboot August 2016

coreboot@coreboot.org

53 participants
132 discussions

Re: [coreboot] FS2 for anyone who can use it
by Nico Huber 10 Aug '16

10 Aug '16

On 10.08.2016 10:35, ron minnich wrote: > ah, no, those are not it. Sorry. I'll get you some pictures. Maybe [1] helps. It's my best FS2 shot for something coreboot related. Nico [1] http://web.archive.org/web/20080915062711/http://www.fs2.com/ > > ron > > > > On Wed, Aug 10, 2016 at 12:42 AM Zoran Stojsavljevic < > zoran.stojsavljevic(a)gmail.com> wrote: > >>> What's an FS2? >> >> http://www.notebookcheck.net/LG-FS2.7422.0.html >> http://www.notebookcheck.net/Intel-Pentium-Dual-Core-Processor.14045.0.html >> >> Zoran >> >> On Tue, Aug 9, 2016 at 3:30 PM, Jonathan Neuschäfer <j.neuschaefer(a)gmx.net >>> wrote: >> >>> On Sat, Aug 06, 2016 at 10:39:48PM +0000, ron minnich wrote: >>>> I have an FS2 if someone can use it. I may have mentioned this before. I >>>> can bring it to berlin with me if you will be at the meeting. >>> >>> Hi Ron, >>> >>> What's an FS2? >>> >>> >>> Jonathan >>>

2 1

Re: [coreboot] Where is the first instrucion?
by ron minnich 10 Aug '16

10 Aug '16

On Wed, Aug 10, 2016 at 3:34 AM Zoran Stojsavljevic < zoran.stojsavljevic(a)gmail.com> wrote: > > > Basically, in the classic car we got in 2005, the steps on x86 are: > > enable cache > *> do references to set tags* > > disable cache (really!) > > then cache as ram works. > > I am interested how this is implemented, in *RED* (if you can point to > some Coreboot implementation)? > >> >> It varies with CPU. In most cases, it involves enabling the cache, sometimes messing around with an MSR, then reading/writing memory which is not functional, but the write sets the tags, so later when you set CD you can use cache and it won't try to load lines/writeback lines. Some chipsets need to be told not to wedge or reset or go crazy when that happens, but it works one way or another. It's all very weird and not nearly as clean as the power pc. Power PC is where we first used CAR for linuxbios, ca. 2001. It took us another 4 years to learn how to do it on x86, and the vendors keep changing it on us :-) I like the ARM SRAM approach. I asked the RISCV vendors to do the same thing. As can be seen with the various x86 CPUs, CAR just gets messy over time. oh, and, that paper? https://www.coreboot.org/images/6/6c/LBCar.pdf It's a great writeup. See page 21. Note how simple that code is. Compare it to the newer chipsets. Note that CD really means "no fill". At the same I commented that the words "Cache Disable" were, to many, evocative of "disabling the cache". My bet is CD used to mean cache disable, and the alternative meaning came later when CAR was implemented. ron

1 0

Re: [coreboot] Where is the first instrucion?
by Zoran Stojsavljevic 10 Aug '16

10 Aug '16

Hello Ron, These are the excellent points! I did not know/had no clue this myself. It is a good remark, I would not know to search/discover for this!? The other good point is that CAR/NEM was developed by student in INTEL, doing his internship (which I always asked myself why such major things were developed by students???)?! ;-) I have one question here: > Basically, in the classic car we got in 2005, the steps on x86 are: > enable cache *> do references to set tags* > disable cache (really!) > then cache as ram works. I am interested how this is implemented, in *RED* (if you can point to some Coreboot implementation)? Hello Qureshi, Any quick points about *do reference to set tags *(implementation wise)? Thank you all, Zoran On Tue, Aug 9, 2016 at 6:44 PM, ron minnich <rminnich(a)gmail.com> wrote: > I have not read this thread closely and maybe I'm telling you something > you know. But I want to warn you about CD. I know it is named 'cache > disabled' > but that's not quite what it means. > > I'm trying and failing to find the original slide deck from the UNM grad > student (and intel employee) who first implemented our cache as ram in > 2005. His point to me was that CD doesn't *really* mean cache hardware is > disabled, just that it changes cache hardware behavior such that refills > from memory are disabled. If there are valid tags in the cache then loads > that hit those tags will work. So the task for CAR on x86 is to create > valid tags, then set CD. His point was the breakthrough for me on > understanding CAR on x86. Ollie Lo and I had been stuck on this point for a > while, we kept thinking we could not set CD and have CAR work; in fact, > setting CD is part of ensuring CAR works. The Intel employee's point was > "you have to read between the lines in section III". > > you can > git grep DO.NOT.INVALIDATE > for a few comments on this and it may help. > > Basically, in the classic car we got in 2005, the steps on x86 are: > enable cache > do references to set tags > disable cache (really!) > then cache as ram works. > > Things have changed on some CPUs since then and we now even have > chipset-dependent x86 CAR code but I suspect the basic idea remains the > same on x86. > > You may already know this, just wanted to make sure. > > ron > > -- > coreboot mailing list: coreboot(a)coreboot.org > https://www.coreboot.org/mailman/listinfo/coreboot >

1 0

Re: [coreboot] FS2 for anyone who can use it
by ron minnich 10 Aug '16

10 Aug '16

ah, no, those are not it. Sorry. I'll get you some pictures. ron On Wed, Aug 10, 2016 at 12:42 AM Zoran Stojsavljevic < zoran.stojsavljevic(a)gmail.com> wrote: > > What's an FS2? > > http://www.notebookcheck.net/LG-FS2.7422.0.html > http://www.notebookcheck.net/Intel-Pentium-Dual-Core-Processor.14045.0.html > > Zoran > > On Tue, Aug 9, 2016 at 3:30 PM, Jonathan Neuschäfer <j.neuschaefer(a)gmx.net > > wrote: > >> On Sat, Aug 06, 2016 at 10:39:48PM +0000, ron minnich wrote: >> > I have an FS2 if someone can use it. I may have mentioned this before. I >> > can bring it to berlin with me if you will be at the meeting. >> >> Hi Ron, >> >> What's an FS2? >> >> >> Jonathan >> >> -- >> coreboot mailing list: coreboot(a)coreboot.org >> https://www.coreboot.org/mailman/listinfo/coreboot >> >

1 0

Re: [coreboot] FS2 for anyone who can use it
by Jonathan Neuschäfer 10 Aug '16

10 Aug '16

On Sat, Aug 06, 2016 at 10:39:48PM +0000, ron minnich wrote: > I have an FS2 if someone can use it. I may have mentioned this before. I > can bring it to berlin with me if you will be at the meeting. Hi Ron, What's an FS2? Jonathan

2 1

Re: [coreboot] Where is the first instrucion?
by Yaroslav K. 10 Aug '16

10 Aug '16

Hello! May I interfere as I have some interest in this topic too. Modern Intel CPUs have the special "no eviction mode" MSR which is used instead of CD bit to set up CAR. Am I understanding right that the purpose of it is to have the ability to use the caching for ROM along with CAR? -- Yaroslav

1 0

skylake support
by Neal Elliott 09 Aug '16

09 Aug '16

Hello to all, I really like coreboot and would like to use it on a current motherboard. the idea of having a open source alternative bios resonates with me. I would like to buy a motherboard with skylake chipsets that is supported by coreboot. does anyone recommend a supported skylake motherboard? Thanks in advance for your time, Neal

2 1

Re: [coreboot] Where is the first instrucion?
by Rafael Machado 09 Aug '16

09 Aug '16

Hi Ron I didn't know that and really appreciate all this information. I'll take a look at what you mentioned Thanks a lot! Em ter, 9 de ago de 2016 às 13:45, ron minnich <rminnich(a)gmail.com> escreveu: > I have not read this thread closely and maybe I'm telling you something > you know. But I want to warn you about CD. I know it is named 'cache > disabled' > but that's not quite what it means. > > I'm trying and failing to find the original slide deck from the UNM grad > student (and intel employee) who first implemented our cache as ram in > 2005. His point to me was that CD doesn't *really* mean cache hardware is > disabled, just that it changes cache hardware behavior such that refills > from memory are disabled. If there are valid tags in the cache then loads > that hit those tags will work. So the task for CAR on x86 is to create > valid tags, then set CD. His point was the breakthrough for me on > understanding CAR on x86. Ollie Lo and I had been stuck on this point for a > while, we kept thinking we could not set CD and have CAR work; in fact, > setting CD is part of ensuring CAR works. The Intel employee's point was > "you have to read between the lines in section III". > > you can > git grep DO.NOT.INVALIDATE > for a few comments on this and it may help. > > Basically, in the classic car we got in 2005, the steps on x86 are: > enable cache > do references to set tags > disable cache (really!) > then cache as ram works. > > Things have changed on some CPUs since then and we now even have > chipset-dependent x86 CAR code but I suspect the basic idea remains the > same on x86. > > You may already know this, just wanted to make sure. > > ron > -- > coreboot mailing list: coreboot(a)coreboot.org > https://www.coreboot.org/mailman/listinfo/coreboot

1 0

KGPE-D16 Black SATA2 ports do not work
by aether＠openmailbox.org 09 Aug '16

09 Aug '16

Hello, I have a small issue with KGPE-D16. The two black sata2 ports do not work. (The SATA2 red ones work fine. All SAS/SATA3 work fine as well with Pike 2008 card.) With Asus BIOS they work fine. I tried with several HDD just to make sure but they are not detected at all. Please find my coreboot config and cbmem dump : ---- coreboot config : # # Automatically generated file; DO NOT EDIT. # coreboot configuration # # # General setup # CONFIG_LOCALVERSION="" CONFIG_CBFS_PREFIX="fallback" # CONFIG_MULTIPLE_CBFS_INSTANCES is not set CONFIG_COMPILER_GCC=y # CONFIG_COMPILER_LLVM_CLANG is not set # CONFIG_ANY_TOOLCHAIN is not set # CONFIG_CCACHE is not set # CONFIG_FMD_GENPARSER is not set # CONFIG_SCONFIG_GENPARSER is not set # CONFIG_USE_OPTION_TABLE is not set # CONFIG_UNCOMPRESSED_RAMSTAGE is not set CONFIG_COMPRESS_RAMSTAGE=y CONFIG_INCLUDE_CONFIG_FILE=y # CONFIG_NO_XIP_EARLY_STAGES is not set CONFIG_EARLY_CBMEM_INIT=y # CONFIG_EARLY_CBMEM_LIST is not set # CONFIG_COLLECT_TIMESTAMPS is not set # CONFIG_USE_BLOBS is not set # CONFIG_COVERAGE is not set # CONFIG_RELOCATABLE_MODULES is not set # CONFIG_RELOCATABLE_RAMSTAGE is not set # CONFIG_NO_STAGE_CACHE is not set CONFIG_BOOTBLOCK_SIMPLE=y # CONFIG_BOOTBLOCK_NORMAL is not set CONFIG_BOOTBLOCK_CUSTOM=y CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" # CONFIG_C_ENVIRONMENT_BOOTBLOCK is not set # CONFIG_UPDATE_IMAGE is not set # CONFIG_GENERIC_GPIO_LIB is not set # CONFIG_BOARD_ID_AUTO is not set # CONFIG_BOARD_ID_MANUAL is not set CONFIG_DEVICETREE="devicetree.cb" # CONFIG_RAM_CODE_SUPPORT is not set # CONFIG_BOOTSPLASH_IMAGE is not set # # Mainboard # # CONFIG_VENDOR_A_TREND is not set # CONFIG_VENDOR_AAEON is not set # CONFIG_VENDOR_ABIT is not set # CONFIG_VENDOR_ADI is not set # CONFIG_VENDOR_ADLINK is not set # CONFIG_VENDOR_ADVANSUS is not set # CONFIG_VENDOR_AMD is not set # CONFIG_VENDOR_AOPEN is not set # CONFIG_VENDOR_APPLE is not set # CONFIG_VENDOR_ARTECGROUP is not set # CONFIG_VENDOR_ASROCK is not set CONFIG_VENDOR_ASUS=y # CONFIG_VENDOR_AVALUE is not set # CONFIG_VENDOR_AZZA is not set # CONFIG_VENDOR_BACHMANN is not set # CONFIG_VENDOR_BAP is not set # CONFIG_VENDOR_BCOM is not set # CONFIG_VENDOR_BIFFEROS is not set # CONFIG_VENDOR_BIOSTAR is not set # CONFIG_VENDOR_BROADCOM is not set # CONFIG_VENDOR_COMPAQ is not set # CONFIG_VENDOR_CUBIETECH is not set # CONFIG_VENDOR_DIGITALLOGIC is not set # CONFIG_VENDOR_DMP is not set # CONFIG_VENDOR_ECS is not set # CONFIG_VENDOR_EMULATION is not set # CONFIG_VENDOR_ESD is not set # CONFIG_VENDOR_GETAC is not set # CONFIG_VENDOR_GIGABYTE is not set # CONFIG_VENDOR_GIZMOSPHERE is not set # CONFIG_VENDOR_GOOGLE is not set # CONFIG_VENDOR_HP is not set # CONFIG_VENDOR_IBASE is not set # CONFIG_VENDOR_IEI is not set # CONFIG_VENDOR_INTEL is not set # CONFIG_VENDOR_IWAVE is not set # CONFIG_VENDOR_IWILL is not set # CONFIG_VENDOR_JETWAY is not set # CONFIG_VENDOR_KONTRON is not set # CONFIG_VENDOR_LANNER is not set # CONFIG_VENDOR_LENOVO is not set # CONFIG_VENDOR_LINUTOP is not set # CONFIG_VENDOR_LIPPERT is not set # CONFIG_VENDOR_MITAC is not set # CONFIG_VENDOR_MSI is not set # CONFIG_VENDOR_NEC is not set # CONFIG_VENDOR_NOKIA is not set # CONFIG_VENDOR_NVIDIA is not set # CONFIG_VENDOR_PACKARDBELL is not set # CONFIG_VENDOR_PCENGINES is not set # CONFIG_VENDOR_PURISM is not set # CONFIG_VENDOR_RCA is not set # CONFIG_VENDOR_RODA is not set # CONFIG_VENDOR_SAMSUNG is not set # CONFIG_VENDOR_SIEMENS is not set # CONFIG_VENDOR_SOYO is not set # CONFIG_VENDOR_SUNW is not set # CONFIG_VENDOR_SUPERMICRO is not set # CONFIG_VENDOR_TECHNEXION is not set # CONFIG_VENDOR_THOMSON is not set # CONFIG_VENDOR_TI is not set # CONFIG_VENDOR_TRAVERSE is not set # CONFIG_VENDOR_TYAN is not set # CONFIG_VENDOR_VIA is not set # CONFIG_VENDOR_WINENT is not set # CONFIG_VENDOR_WYSE is not set CONFIG_BOARD_SPECIFIC_OPTIONS=y CONFIG_MAINBOARD_DIR="asus/kgpe-d16" CONFIG_MAINBOARD_PART_NUMBER="KGPE-D16" CONFIG_IRQ_SLOT_COUNT=13 CONFIG_MAINBOARD_VENDOR="ASUS" CONFIG_MAX_CPUS=32 CONFIG_CACHE_ROM_SIZE_OVERRIDE=0 CONFIG_CBFS_SIZE=0x800000 CONFIG_PAYLOAD_CONFIGFILE="" CONFIG_APIC_ID_OFFSET=0 CONFIG_HW_MEM_HOLE_SIZEK=0x100000 CONFIG_MAX_PHYSICAL_CPUS=4 # CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC is not set CONFIG_HT_CHAIN_END_UNITID_BASE=0x20 CONFIG_HT_CHAIN_UNITID_BASE=0x0 # CONFIG_ONBOARD_VGA_IS_PRIMARY is not set # CONFIG_VGA_BIOS is not set CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" CONFIG_DCACHE_RAM_BASE=0xc2000 CONFIG_DCACHE_RAM_SIZE=0x1e000 CONFIG_MMCONF_BASE_ADDRESS=0xc0000000 CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="ASUS" # CONFIG_BOARD_ASUS_A8N_E is not set # CONFIG_BOARD_ASUS_A8N_SLI is not set # CONFIG_BOARD_ASUS_A8V_E_DELUXE is not set # CONFIG_BOARD_ASUS_A8V_E_SE is not set # CONFIG_BOARD_ASUS_DSBF is not set # CONFIG_BOARD_ASUS_F2A85_M is not set # CONFIG_BOARD_ASUS_F2A85_M_LE is not set # CONFIG_BOARD_ASUS_K8V_X is not set # CONFIG_BOARD_ASUS_KCMA_D8 is not set # CONFIG_BOARD_ASUS_KFSN4_DRE is not set # CONFIG_BOARD_ASUS_KFSN4_DRE_K8 is not set CONFIG_BOARD_ASUS_KGPE_D16=y # CONFIG_BOARD_ASUS_M2N_E is not set # CONFIG_BOARD_ASUS_M2V_MX_SE is not set # CONFIG_BOARD_ASUS_M2V is not set # CONFIG_BOARD_ASUS_M4A78_EM is not set # CONFIG_BOARD_ASUS_M4A785M is not set # CONFIG_BOARD_ASUS_M4A785TM is not set # CONFIG_BOARD_ASUS_M5A88_V is not set # CONFIG_BOARD_ASUS_MEW_AM is not set # CONFIG_BOARD_ASUS_MEW_VM is not set # CONFIG_BOARD_ASUS_P2B_D is not set # CONFIG_BOARD_ASUS_P2B_DS is not set # CONFIG_BOARD_ASUS_P2B_F is not set # CONFIG_BOARD_ASUS_P2B_LS is not set # CONFIG_BOARD_ASUS_P2B is not set # CONFIG_BOARD_ASUS_P3B_F is not set CONFIG_POST_IO=y CONFIG_AGP_APERTURE_SIZE=0x4000000 CONFIG_BOOTBLOCK_MAINBOARD_INIT="mainboard/asus/kgpe-d16/bootblock.c" CONFIG_SOUTHBRIDGE_AMD_SB700_SATA_PORT_COUNT_BITFIELD=0x3f CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL=y CONFIG_MAX_REBOOT_CNT=10 CONFIG_ID_SECTION_OFFSET=0x80 CONFIG_POST_DEVICE=y CONFIG_BOOT_MEDIA_SPI_BUS=0 # CONFIG_DRIVERS_PS2_KEYBOARD is not set # CONFIG_CONSOLE_POST is not set # CONFIG_DRIVERS_UART_8250IO is not set CONFIG_UDELAY_LAPIC_FIXED_FSB=200 CONFIG_SEABIOS_PS2_TIMEOUT=0 CONFIG_CPU_ADDR_BITS=48 CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 # CONFIG_USBDEBUG is not set CONFIG_MAINBOARD_VERSION="1.0" # CONFIG_NO_POST is not set CONFIG_BOARD_ROMSIZE_KB_2048=y # CONFIG_COREBOOT_ROMSIZE_KB_64 is not set # CONFIG_COREBOOT_ROMSIZE_KB_128 is not set # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set # CONFIG_COREBOOT_ROMSIZE_KB_512 is not set # CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set # CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set # CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set CONFIG_COREBOOT_ROMSIZE_KB_8192=y # CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set # CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set # CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set # CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set CONFIG_COREBOOT_ROMSIZE_KB=8192 CONFIG_ROM_SIZE=0x800000 CONFIG_FMDFILE="" # CONFIG_MAINBOARD_HAS_TPM2 is not set # CONFIG_SYSTEM_TYPE_LAPTOP is not set # CONFIG_CBFS_AUTOGEN_ATTRIBUTES is not set # # Chipset # # # SoC # # CONFIG_SOC_BROADCOM_CYGNUS is not set CONFIG_DCACHE_BSP_STACK_SIZE=0x4000 CONFIG_C_ENV_BOOTBLOCK_SIZE=0x10000 CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y CONFIG_ROMSTAGE_ADDR=0x2000000 CONFIG_VERSTAGE_ADDR=0x2000000 CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT="northbridge/amd/amdfam10/bootblock.c" CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT="southbridge/amd/sb700/bootblock.c" CONFIG_EHCI_BAR=0xfef00000 CONFIG_RAMTOP=0x400000 CONFIG_HEAP_SIZE=0xc0000 CONFIG_CONSOLE_CBMEM=y CONFIG_UART_PCI_ADDR=0 CONFIG_HPET_MIN_TICKS=0x14 # CONFIG_SOC_MARVELL_ARMADA38X is not set # CONFIG_SOC_MARVELL_BG4CD is not set # CONFIG_SOC_MEDIATEK_MT8173 is not set # CONFIG_SOC_NVIDIA_TEGRA124 is not set # CONFIG_SOC_NVIDIA_TEGRA210 is not set # CONFIG_SOC_QC_IPQ40XX is not set # CONFIG_SOC_QC_IPQ806X is not set # CONFIG_SOC_ROCKCHIP_RK3288 is not set # CONFIG_SOC_ROCKCHIP_RK3399 is not set # CONFIG_CPU_SAMSUNG_EXYNOS5250 is not set # CONFIG_CPU_SAMSUNG_EXYNOS5420 is not set # CONFIG_SOC_UCB_RISCV is not set # # CPU # # CONFIG_CPU_ALLWINNER_A10 is not set CONFIG_DCACHE_BSP_STACK_SLUSH=0x4000 CONFIG_DCACHE_AP_STACK_SIZE=0x500 CONFIG_CPU_SOCKET_TYPE=0x15 # CONFIG_EXT_RT_TBL_SUPPORT is not set CONFIG_CBB=0x0 CONFIG_CDB=0x18 CONFIG_XIP_ROM_SIZE=0x80000 CONFIG_CPU_AMD_SOCKET_G34_NON_AGESA=y CONFIG_DIMM_SUPPORT=0x0005 CONFIG_LIFT_BSP_APIC_ID=y CONFIG_SET_FIDVID=y CONFIG_SET_FIDVID_DEBUG=y # CONFIG_SET_FIDVID_CORE0_ONLY is not set CONFIG_SET_FIDVID_STORE_AP_APICID_AT_FIRST=y CONFIG_CPU_AMD_MODEL_10XXX=y CONFIG_USE_LARGE_DCACHE=y CONFIG_NUM_IPI_STARTS=1 CONFIG_SET_FIDVID_CORE_RANGE=0 # CONFIG_CPU_AMD_AGESA is not set CONFIG_S3_DATA_POS=0x0 CONFIG_S3_DATA_SIZE=32768 # CONFIG_CPU_AMD_PI is not set CONFIG_EXT_CONF_SUPPORT=y # CONFIG_CPU_ARMLTD_CORTEX_A9 is not set CONFIG_SSE2=y # CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE is not set # CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED is not set # CONFIG_CPU_TI_AM335X is not set CONFIG_PARALLEL_CPU_INIT=y # CONFIG_PARALLEL_MP is not set # CONFIG_UDELAY_IO is not set CONFIG_UDELAY_LAPIC=y # CONFIG_LAPIC_MONOTONIC_TIMER is not set # CONFIG_UDELAY_TSC is not set # CONFIG_UDELAY_TIMER2 is not set CONFIG_TSC_SYNC_LFENCE=y # CONFIG_TSC_SYNC_MFENCE is not set # CONFIG_NO_FIXED_XIP_ROM_SIZE is not set CONFIG_LOGICAL_CPUS=y # CONFIG_SMM_TSEG is not set # CONFIG_SMM_LAPIC_REMAP_MITIGATION is not set # CONFIG_SERIALIZED_SMM_INITIALIZATION is not set CONFIG_X86_AMD_FIXED_MTRRS=y # CONFIG_PLATFORM_USES_FSP1_0 is not set # CONFIG_MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING is not set # CONFIG_SOC_SETS_MSRS is not set CONFIG_CACHE_AS_RAM=y CONFIG_SMP=y CONFIG_AP_SIPI_VECTOR=0xfffff000 CONFIG_SSE=y CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y # CONFIG_USES_MICROCODE_HEADER_FILES is not set # CONFIG_CPU_MICROCODE_CBFS_GENERATE is not set # CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set CONFIG_CPU_MICROCODE_CBFS_NONE=y # # Northbridge # # CONFIG_NORTHBRIDGE_AMD_AGESA is not set CONFIG_S3_VGA_ROM_RUN=y CONFIG_MMCONF_BUS_NUMBER=256 CONFIG_NORTHBRIDGE_AMD_AMDFAM10=y CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=y # CONFIG_HT_CHAIN_DISTRIBUTE is not set # CONFIG_DIMM_FBDIMM is not set # CONFIG_DIMM_DDR2 is not set CONFIG_DIMM_DDR3=y CONFIG_DIMM_REGISTERED=y CONFIG_DIMM_VOLTAGE_SET_SUPPORT=y # CONFIG_SVI_HIGH_FREQ is not set # # HyperTransport setup # # CONFIG_LIMIT_HT_DOWN_WIDTH_8 is not set CONFIG_LIMIT_HT_DOWN_WIDTH_16=y # CONFIG_LIMIT_HT_UP_WIDTH_8 is not set CONFIG_LIMIT_HT_UP_WIDTH_16=y # CONFIG_AMD_NB_CIMX is not set # CONFIG_NORTHBRIDGE_AMD_CIMX_RD890 is not set CONFIG_VIDEO_MB=0 # CONFIG_NORTHBRIDGE_AMD_PI is not set CONFIG_RAMBASE=0x100000 # CONFIG_NORTHBRIDGE_INTEL_COMMON_MRC_CACHE is not set CONFIG_HPET_ADDRESS=0xfed00000 CONFIG_MAX_PIRQ_LINKS=4 # # Southbridge # # CONFIG_AMD_SB_CIMX is not set # CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set # CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set CONFIG_SOUTHBRIDGE_AMD_SB700=y CONFIG_SOUTHBRIDGE_SPECIFIC_OPTIONS=y CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100=y # CONFIG_SOUTHBRIDGE_AMD_SB700_SKIP_ISA_DMA_INIT is not set CONFIG_SOUTHBRIDGE_AMD_SB700_DISABLE_ISA_DMA=y CONFIG_SOUTHBRIDGE_AMD_SR5650=y # CONFIG_SOUTHBRIDGE_INTEL_COMMON is not set # CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO is not set # # Super I/O # CONFIG_SUPERIO_WINBOND_COMMON_ROMSTAGE=y CONFIG_SUPERIO_WINBOND_W83667HG_A=y # # Embedded Controllers # CONFIG_VBOOT_VBNV_OFFSET=0x26 # CONFIG_VBOOT_VBNV_CMOS is not set # CONFIG_VBOOT_VBNV_EC is not set # CONFIG_VBOOT_VBNV_FLASH is not set # CONFIG_VBOOT is not set # CONFIG_MAINBOARD_HAS_CHROMEOS is not set # CONFIG_UEFI_2_4_BINDING is not set # CONFIG_USE_SIEMENS_HWILIB is not set # CONFIG_ARCH_ARM is not set # CONFIG_ARCH_BOOTBLOCK_ARM is not set # CONFIG_ARCH_VERSTAGE_ARM is not set # CONFIG_ARCH_ROMSTAGE_ARM is not set # CONFIG_ARCH_RAMSTAGE_ARM is not set # CONFIG_ARCH_BOOTBLOCK_ARMV4 is not set # CONFIG_ARCH_VERSTAGE_ARMV4 is not set # CONFIG_ARCH_ROMSTAGE_ARMV4 is not set # CONFIG_ARCH_RAMSTAGE_ARMV4 is not set # CONFIG_ARCH_BOOTBLOCK_ARMV7 is not set # CONFIG_ARCH_VERSTAGE_ARMV7 is not set # CONFIG_ARCH_ROMSTAGE_ARMV7 is not set # CONFIG_ARCH_RAMSTAGE_ARMV7 is not set # CONFIG_ARCH_BOOTBLOCK_ARMV7_M is not set # CONFIG_ARCH_VERSTAGE_ARMV7_M is not set # CONFIG_ARM_LPAE is not set # CONFIG_ARCH_ARM64 is not set # CONFIG_ARCH_BOOTBLOCK_ARM64 is not set # CONFIG_ARCH_VERSTAGE_ARM64 is not set # CONFIG_ARCH_ROMSTAGE_ARM64 is not set # CONFIG_ARCH_RAMSTAGE_ARM64 is not set # CONFIG_ARCH_BOOTBLOCK_ARMV8_64 is not set # CONFIG_ARCH_VERSTAGE_ARMV8_64 is not set # CONFIG_ARCH_ROMSTAGE_ARMV8_64 is not set # CONFIG_ARCH_RAMSTAGE_ARMV8_64 is not set # CONFIG_ARM64_A53_ERRATUM_843419 is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_BOOTBLOCK_MIPS is not set # CONFIG_ARCH_VERSTAGE_MIPS is not set # CONFIG_ARCH_ROMSTAGE_MIPS is not set # CONFIG_ARCH_RAMSTAGE_MIPS is not set # CONFIG_ARCH_POWER8 is not set # CONFIG_ARCH_BOOTBLOCK_POWER8 is not set # CONFIG_ARCH_VERSTAGE_POWER8 is not set # CONFIG_ARCH_ROMSTAGE_POWER8 is not set # CONFIG_ARCH_RAMSTAGE_POWER8 is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_BOOTBLOCK_RISCV is not set # CONFIG_ARCH_VERSTAGE_RISCV is not set # CONFIG_ARCH_ROMSTAGE_RISCV is not set # CONFIG_ARCH_RAMSTAGE_RISCV is not set CONFIG_ARCH_X86=y CONFIG_ARCH_BOOTBLOCK_X86_32=y CONFIG_ARCH_VERSTAGE_X86_32=y CONFIG_ARCH_ROMSTAGE_X86_32=y CONFIG_ARCH_RAMSTAGE_X86_32=y # CONFIG_ARCH_BOOTBLOCK_X86_64 is not set # CONFIG_ARCH_VERSTAGE_X86_64 is not set # CONFIG_ARCH_ROMSTAGE_X86_64 is not set # CONFIG_ARCH_RAMSTAGE_X86_64 is not set # CONFIG_USE_MARCH_586 is not set # CONFIG_AP_IN_SIPI_WAIT is not set # CONFIG_SIPI_VECTOR_IN_ROM is not set # CONFIG_ROMCC is not set # CONFIG_LATE_CBMEM_INIT is not set CONFIG_PC80_SYSTEM=y # CONFIG_BOOTBLOCK_DEBUG_SPINLOOP is not set # CONFIG_BOOTBLOCK_SAVE_BIST_AND_TIMESTAMP is not set CONFIG_HAVE_CMOS_DEFAULT=y CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" CONFIG_IOAPIC_INTERRUPTS_ON_FSB=y # CONFIG_IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS is not set # CONFIG_POSTCAR_STAGE is not set # CONFIG_VERSTAGE_DEBUG_SPINLOOP is not set # CONFIG_ROMSTAGE_DEBUG_SPINLOOP is not set # # Devices # # CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT is not set CONFIG_NATIVE_VGA_INIT_USE_EDID=y CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG=y CONFIG_VGA_ROM_RUN=y # CONFIG_ALWAYS_LOAD_OPROM is not set # CONFIG_ON_DEVICE_ROM_LOAD is not set CONFIG_PCI_OPTION_ROM_RUN_REALMODE=y # CONFIG_PCI_OPTION_ROM_RUN_YABEL is not set # CONFIG_MULTIPLE_VGA_ADAPTERS is not set CONFIG_SMBUS_HAS_AUX_CHANNELS=y # CONFIG_SPD_CACHE is not set CONFIG_PCI=y CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT=y CONFIG_PCIX_PLUGIN_SUPPORT=y CONFIG_PCIEXP_PLUGIN_SUPPORT=y CONFIG_CARDBUS_PLUGIN_SUPPORT=y # CONFIG_AZALIA_PLUGIN_SUPPORT is not set CONFIG_PCIEXP_COMMON_CLOCK=y CONFIG_PCIEXP_ASPM=y CONFIG_PCIEXP_CLK_PM=y # CONFIG_EARLY_PCI_BRIDGE is not set CONFIG_PCIEXP_L1_SUB_STATE=y CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 # CONFIG_SOFTWARE_I2C is not set # # Display # # CONFIG_FRAMEBUFFER_SET_VESA_MODE is not set # CONFIG_FRAMEBUFFER_KEEP_VESA_MODE is not set # # Generic Drivers # # CONFIG_DRIVERS_AS3722_RTC is not set # CONFIG_ELOG is not set # CONFIG_GIC is not set # CONFIG_IPMI_KCS is not set # CONFIG_DRIVERS_LENOVO_WACOM is not set # CONFIG_DRIVERS_LENOVO_HYBRID_GRAPHICS is not set # CONFIG_REALTEK_8168_RESET is not set CONFIG_SPI_FLASH=y CONFIG_SPI_ATOMIC_SEQUENCING=y CONFIG_SPI_FLASH_MEMORY_MAPPED=y # CONFIG_SPI_FLASH_NO_FAST_READ is not set CONFIG_SPI_FLASH_ADESTO=y CONFIG_SPI_FLASH_AMIC=y CONFIG_SPI_FLASH_ATMEL=y CONFIG_SPI_FLASH_EON=y CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_SST=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_WINBOND=y # CONFIG_SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B is not set # CONFIG_HAVE_SPI_CONSOLE_SUPPORT is not set # CONFIG_DRIVERS_UART is not set # CONFIG_NO_UART_ON_SUPERIO is not set # CONFIG_UART_OVERRIDE_INPUT_CLOCK_DIVIDER is not set # CONFIG_UART_OVERRIDE_REFCLK is not set # CONFIG_DRIVERS_UART_8250MEM is not set # CONFIG_DRIVERS_UART_8250MEM_32 is not set # CONFIG_HAVE_UART_SPECIAL is not set # CONFIG_DRIVERS_UART_OXPCIE is not set # CONFIG_DRIVERS_UART_PL011 is not set # CONFIG_UART_USE_REFCLK_AS_INPUT_CLOCK is not set CONFIG_HAVE_USBDEBUG=y CONFIG_HAVE_USBDEBUG_OPTIONS=y CONFIG_DRIVERS_ASPEED_AST2050=y CONFIG_DRIVERS_ASPEED_AST_COMMON=y # CONFIG_SMBIOS_PROVIDED_BY_MOBO is not set # CONFIG_DRIVERS_I2C_PCF8523 is not set # CONFIG_DRIVERS_I2C_RTD2132 is not set CONFIG_DRIVERS_I2C_W83795=y # CONFIG_INTEL_DP is not set # CONFIG_INTEL_DDI is not set # CONFIG_INTEL_EDID is not set # CONFIG_INTEL_INT15 is not set # CONFIG_INTEL_GMA_ACPI is not set # CONFIG_DRIVER_INTEL_I210 is not set # CONFIG_DRIVERS_INTEL_WIFI is not set # CONFIG_DRIVER_MAXIM_MAX77686 is not set # CONFIG_DRIVER_PARADE_PS8625 is not set # CONFIG_DRIVER_PARADE_PS8640 is not set CONFIG_DRIVERS_MC146818=y # CONFIG_MAINBOARD_HAS_LPC_TPM is not set # CONFIG_DRIVERS_RICOH_RCE822 is not set # CONFIG_DRIVER_SIEMENS_NC_FPGA is not set # CONFIG_DRIVERS_SIL_3114 is not set # CONFIG_DRIVER_TI_TPS65090 is not set # CONFIG_DRIVERS_TI_TPS65913 is not set # CONFIG_DRIVERS_TI_TPS65913_RTC is not set # CONFIG_DRIVER_XPOWERS_AXP209 is not set # CONFIG_ACPI_SATA_GENERATOR is not set # CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES is not set # CONFIG_RTC is not set # CONFIG_TPM is not set CONFIG_STACK_SIZE=0x1000 CONFIG_MMCONF_SUPPORT_DEFAULT=y CONFIG_MMCONF_SUPPORT=y # # Console # CONFIG_SQUELCH_EARLY_SMP=y # CONFIG_SPKMODEM is not set # CONFIG_CONSOLE_NE2K is not set CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 # CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set # CONFIG_CMOS_POST is not set CONFIG_POST_DEVICE_NONE=y # CONFIG_POST_DEVICE_LPC is not set # CONFIG_POST_DEVICE_PCI_PCIE is not set CONFIG_POST_IO_PORT=0x80 # CONFIG_NO_EARLY_BOOTBLOCK_POSTCODES is not set CONFIG_HAVE_ACPI_RESUME=y CONFIG_RESUME_PATH_SAME_AS_BOOT=y CONFIG_HAVE_HARD_RESET=y CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK=y CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK=y CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK=y CONFIG_HAVE_MONOTONIC_TIMER=y # CONFIG_GENERIC_UDELAY is not set # CONFIG_TIMER_QUEUE is not set CONFIG_HAVE_OPTION_TABLE=y # CONFIG_PIRQ_ROUTE is not set # CONFIG_HAVE_SMI_HANDLER is not set CONFIG_PCI_IO_CFG_EXT=y CONFIG_IOAPIC=y # CONFIG_USE_WATCHDOG_ON_BOOT is not set CONFIG_VGA=y # CONFIG_GFXUMA is not set CONFIG_HAVE_ACPI_TABLES=y CONFIG_HAVE_MP_TABLE=y CONFIG_HAVE_PIRQ_TABLE=y # CONFIG_COMMON_FADT is not set # CONFIG_ACPI_NHLT is not set # # System tables # CONFIG_GENERATE_MP_TABLE=y CONFIG_GENERATE_PIRQ_TABLE=y CONFIG_GENERATE_SMBIOS_TABLES=y CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="KGPE-D16" # # Payload # # CONFIG_PAYLOAD_NONE is not set # CONFIG_PAYLOAD_ELF is not set # CONFIG_PAYLOAD_FILO is not set # CONFIG_PAYLOAD_GRUB2 is not set CONFIG_PAYLOAD_SEABIOS=y # CONFIG_PAYLOAD_UBOOT is not set # CONFIG_PAYLOAD_LINUX is not set # CONFIG_PAYLOAD_TIANOCORE is not set CONFIG_PAYLOAD_FILE="payloads/external/SeaBIOS/seabios/out/bios.bin.elf" CONFIG_SEABIOS_STABLE=y # CONFIG_SEABIOS_MASTER is not set # CONFIG_SEABIOS_REVISION is not set # CONFIG_SEABIOS_THREAD_OPTIONROMS is not set # CONFIG_SEABIOS_VGA_COREBOOT is not set CONFIG_SEABIOS_BOOTORDER_FILE="" CONFIG_PAYLOAD_OPTIONS="" # CONFIG_PXE is not set CONFIG_COMPRESSED_PAYLOAD_LZMA=y # CONFIG_PAYLOAD_IS_FLAT_BINARY is not set # # Secondary Payloads # # CONFIG_COREINFO_SECONDARY_PAYLOAD is not set # CONFIG_MEMTEST_SECONDARY_PAYLOAD is not set # CONFIG_NVRAMCUI_SECONDARY_PAYLOAD is not set # CONFIG_TINT_SECONDARY_PAYLOAD is not set # # Debugging # # CONFIG_FATAL_ASSERTS is not set # CONFIG_DEBUG_CBFS is not set CONFIG_HAVE_DEBUG_RAM_SETUP=y # CONFIG_DEBUG_RAM_SETUP is not set CONFIG_HAVE_DEBUG_CAR=y # CONFIG_DEBUG_CAR is not set # CONFIG_DEBUG_PIRQ is not set CONFIG_HAVE_DEBUG_SMBUS=y # CONFIG_DEBUG_SMBUS is not set # CONFIG_DEBUG_MALLOC is not set # CONFIG_DEBUG_ACPI is not set # CONFIG_REALMODE_DEBUG is not set # CONFIG_DEBUG_SPI_FLASH is not set # CONFIG_TRACE is not set # CONFIG_DEBUG_BOOT_STATE is not set CONFIG_ENABLE_APIC_EXT_ID=y CONFIG_WARNINGS_ARE_ERRORS=y CONFIG_IASL_WARNINGS_ARE_ERRORS=y # CONFIG_POWER_BUTTON_DEFAULT_ENABLE is not set # CONFIG_POWER_BUTTON_DEFAULT_DISABLE is not set # CONFIG_POWER_BUTTON_FORCE_ENABLE is not set # CONFIG_POWER_BUTTON_FORCE_DISABLE is not set # CONFIG_POWER_BUTTON_IS_OPTIONAL is not set # CONFIG_REG_SCRIPT is not set # CONFIG_CREATE_BOARD_CHECKLIST is not set # CONFIG_MAKE_CHECKLIST_PUBLIC is not set ---- cbmem dump : coreboot-4.4-1158-g0b2cf17 Mon Aug 8 22:23:10 UTC 2016 romstage starting... Initial stack pointer: 000dff38 CPU APICID 00 start flag set BSP Family_Model: 00600f12 *sysinfo range: [000c2d40,000cd28c] bsp_apicid = 00 cpu_init_detectedx = 00000000 sb700 reset flags: 0004 CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 'microcode_amd.bin' CBFS: 'microcode_amd.bin' not found. [microcode] microcode file not found. Skipping updates. cpuSetAMDMSR done Enter amd_ht_init() AMD_CB_EventNotify(): INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 2 new node: 1 AMD_CB_EventNotify(): INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 0 new node: 2 AMD_CB_EventNotify(): INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 3 new node: 3 Forcing HT links to isochronous mode due to enabled IOMMU Exit amd_ht_init() amd_ht_fixup() amd_ht_fixup(): node 0 (internal node ID 0): disabling defective HT link (L3 connected: 1) amd_ht_fixup(): node 1 (internal node ID 1): disabling defective HT link (L3 connected: 1) amd_ht_fixup(): node 2 (internal node ID 0): disabling defective HT link (L3 connected: 1) amd_ht_fixup(): node 3 (internal node ID 1): disabling defective HT link (L3 connected: 1) cpuSetAMDPCI 00 done cpuSetAMDPCI 01 done cpuSetAMDPCI 02 done cpuSetAMDPCI 03 done Prep FID/VID Node:00 F3x80: e20be281 F3x84: 01e200e2 F3xD4: c3312f1a F3xD8: 03000016 F3xDC: 05475635 Prep FID/VID Node:01 F3x80: e20be281 F3x84: 01e200e2 F3xD4: c3312f1a F3xD8: 03000016 F3xDC: 05475635 Prep FID/VID Node:02 F3x80: e20be281 F3x84: 01e200e2 F3xD4: c3312f1a F3xD8: 03000016 F3xDC: 05475635 Prep FID/VID Node:03 F3x80: e20be281 F3x84: 01e200e2 F3xD4: c3312f1a F3xD8: 03000016 F3xDC: 05475635 setup_remote_node: 01 done Start node 01 done. setup_remote_node: 02 done Start node 02 done. setup_remote_node: 03 done Start node 03 done. core0 started: 01 02 03 sr5650_early_setup() get_cpu_rev EAX=0x600f12. CPU Rev is Fam 15. NB Revision is A12. fam10_optimization() sr5650_por_init Enabling IOMMU sb700_early_setup() sb700_devices_por_init() sb700_devices_por_init(): SMBus Device, BDF:0-20-0 SMBus controller enabled, sb revision is A15 sb700_devices_por_init: Disabling ISA DMA support sb700_devices_por_init(): IDE Device, BDF:0-20-1 sb700_devices_por_init(): LPC Device, BDF:0-20-3 sb700_devices_por_init(): P2P Bridge, BDF:0-20-4 sb700_devices_por_init(): SATA Device, BDF:0-17-0 sb700_pmio_por_init() start_other_cores() init node: 00 cores: 05 pass 1 Start other core - nodeid: 00 cores: 05 get_boot_apic_id: using 2 as APIC ID for node 0, core 2 get_boot_apic_id: using 4 as APIC ID for node 0, core 4 init node: 01 cores: 05 pass 1 Start other core - nodeid: 01 cores: 05 get_boot_apic_id: using 8 as APIC ID for node 1, core 2 get_boot_apic_id: using 10 as APIC ID for node 1, core 4 init node: 02 cores: 05 pass 1 Start other core - nodeid: 02 cores: 05 get_boot_apic_id: using 34 as APIC ID for node 2, core 2 get_boot_apic_ *** Log truncated, F45840 characters dropped. *** amdmct_cbmem_store_info: Storing AMDMCT configuration in CBMEM disable_spd() CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 'fallback/ramstage' CBFS: Found @ offset 3ff00 size 1507c coreboot-4.4-1158-g0b2cf17 Mon Aug 8 22:23:10 UTC 2016 ramstage starting... Moving GDT to bfffe9e0...ok Normal boot. BS: BS_PRE_DEVICE times (us): entry 0 run 1 exit 0 BS: BS_DEV_INIT_CHIPS times (us): entry 0 run 2 exit 0 Enumerating buses... Show all devs... Before device enumeration. Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 DOMAIN: 0000: enabled 1 PCI: 00:18.0: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:00.1: enabled 1 PCI: 00:00.2: enabled 1 PCI: 00:02.0: enabled 1 PCI: 00:03.0: enabled 0 PCI: 00:04.0: enabled 1 PCI: 00:05.0: enabled 0 PCI: 00:06.0: enabled 0 PCI: 00:07.0: enabled 0 PCI: 00:08.0: enabled 0 PCI: 00:09.0: enabled 1 PCI: 00:0a.0: enabled 1 PCI: 00:0b.0: enabled 1 PCI: 00:0c.0: enabled 1 PCI: 00:0d.0: enabled 1 PCI: 00:11.0: enabled 1 PCI: 00:12.0: enabled 1 PCI: 00:12.1: enabled 1 PCI: 00:12.2: enabled 1 PCI: 00:13.0: enabled 1 PCI: 00:13.1: enabled 1 PCI: 00:13.2: enabled 1 PCI: 00:14.0: enabled 1 I2C: 00:50: enabled 1 I2C: 00:51: enabled 1 I2C: 00:52: enabled 1 I2C: 00:53: enabled 1 I2C: 00:54: enabled 1 I2C: 00:55: enabled 1 I2C: 00:56: enabled 1 I2C: 00:57: enabled 1 I2C: 00:2f: enabled 1 PCI: 00:14.1: enabled 1 PCI: 00:14.2: enabled 1 PCI: 00:14.3: enabled 1 PNP: 002e.0: enabled 0 PNP: 002e.1: enabled 0 PNP: 002e.2: enabled 1 PNP: 002e.3: enabled 1 PNP: 002e.5: enabled 1 PNP: 002e.106: enabled 0 PNP: 002e.107: enabled 0 PNP: 002e.207: enabled 0 PNP: 002e.307: enabled 0 PNP: 002e.407: enabled 0 PNP: 002e.8: enabled 0 PNP: 002e.108: enabled 0 PNP: 002e.9: enabled 0 PNP: 002e.109: enabled 0 PNP: 002e.209: enabled 0 PNP: 002e.309: enabled 0 PNP: 002e.a: enabled 1 PNP: 002e.b: enabled 1 PNP: 002e.c: enabled 0 PNP: 002e.d: enabled 0 PNP: 002e.f: enabled 0 PCI: 00:14.4: enabled 1 PCI: 00:01.0: enabled 1 PCI: 00:02.0: enabled 1 PCI: 00:03.0: enabled 1 PCI: 00:14.5: enabled 1 PCI: 00:18.1: enabled 1 PCI: 00:18.2: enabled 1 PCI: 00:18.3: enabled 1 PCI: 00:18.4: enabled 1 PCI: 00:18.5: enabled 1 PCI: 00:19.0: enabled 1 PCI: 00:19.1: enabled 1 PCI: 00:19.2: enabled 1 PCI: 00:19.3: enabled 1 PCI: 00:19.4: enabled 1 PCI: 00:19.5: enabled 1 PCI: 00:1a.0: enabled 1 PCI: 00:1a.1: enabled 1 PCI: 00:1a.2: enabled 1 PCI: 00:1a.3: enabled 1 PCI: 00:1a.4: enabled 1 PCI: 00:1a.5: enabled 1 PCI: 00:1b.0: enabled 1 PCI: 00:1b.1: enabled 1 PCI: 00:1b.2: enabled 1 PCI: 00:1b.3: enabled 1 PCI: 00:1b.4: enabled 1 PCI: 00:1b.5: enabled 1 Compare with tree... Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 DOMAIN: 0000: enabled 1 PCI: 00:18.0: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:00.1: enabled 1 PCI: 00:00.2: enabled 1 PCI: 00:02.0: enabled 1 PCI: 00:03.0: enabled 0 PCI: 00:04.0: enabled 1 PCI: 00:05.0: enabled 0 PCI: 00:06.0: enabled 0 PCI: 00:07.0: enabled 0 PCI: 00:08.0: enabled 0 PCI: 00:09.0: enabled 1 PCI: 00:0a.0: enabled 1 PCI: 00:0b.0: enabled 1 PCI: 00:0c.0: enabled 1 PCI: 00:0d.0: enabled 1 PCI: 00:11.0: enabled 1 PCI: 00:12.0: enabled 1 PCI: 00:12.1: enabled 1 PCI: 00:12.2: enabled 1 PCI: 00:13.0: enabled 1 PCI: 00:13.1: enabled 1 PCI: 00:13.2: enabled 1 PCI: 00:14.0: enabled 1 I2C: 00:50: enabled 1 I2C: 00:51: enabled 1 I2C: 00:52: enabled 1 I2C: 00:53: enabled 1 I2C: 00:54: enabled 1 I2C: 00:55: enabled 1 I2C: 00:56: enabled 1 I2C: 00:57: enabled 1 I2C: 00:2f: enabled 1 PCI: 00:14.1: enabled 1 PCI: 00:14.2: enabled 1 PCI: 00:14.3: enabled 1 PNP: 002e.0: enabled 0 PNP: 002e.1: enabled 0 PNP: 002e.2: enabled 1 PNP: 002e.3: enabled 1 PNP: 002e.5: enabled 1 PNP: 002e.106: enabled 0 PNP: 002e.107: enabled 0 PNP: 002e.207: enabled 0 PNP: 002e.307: enabled 0 PNP: 002e.407: enabled 0 PNP: 002e.8: enabled 0 PNP: 002e.108: enabled 0 PNP: 002e.9: enabled 0 PNP: 002e.109: enabled 0 PNP: 002e.209: enabled 0 PNP: 002e.309: enabled 0 PNP: 002e.a: enabled 1 PNP: 002e.b: enabled 1 PNP: 002e.c: enabled 0 PNP: 002e.d: enabled 0 PNP: 002e.f: enabled 0 PCI: 00:14.4: enabled 1 PCI: 00:01.0: enabled 1 PCI: 00:02.0: enabled 1 PCI: 00:03.0: enabled 1 PCI: 00:14.5: enabled 1 PCI: 00:18.1: enabled 1 PCI: 00:18.2: enabled 1 PCI: 00:18.3: enabled 1 PCI: 00:18.4: enabled 1 PCI: 00:18.5: enabled 1 PCI: 00:19.0: enabled 1 PCI: 00:19.1: enabled 1 PCI: 00:19.2: enabled 1 PCI: 00:19.3: enabled 1 PCI: 00:19.4: enabled 1 PCI: 00:19.5: enabled 1 PCI: 00:1a.0: enabled 1 PCI: 00:1a.1: enabled 1 PCI: 00:1a.2: enabled 1 PCI: 00:1a.3: enabled 1 PCI: 00:1a.4: enabled 1 PCI: 00:1a.5: enabled 1 PCI: 00:1b.0: enabled 1 PCI: 00:1b.1: enabled 1 PCI: 00:1b.2: enabled 1 PCI: 00:1b.3: enabled 1 PCI: 00:1b.4: enabled 1 PCI: 00:1b.5: enabled 1 Mainboard KGPE-D16 Enable. dev=0x0012d260 mainboard_enable, TOP MEM: msr.lo = 0xc0000000, msr.hi = 0x00000000 mainboard_enable, TOP MEM2: msr2.lo = 0x40000000, msr2.hi = 0x00000008 Root Device scanning... root_dev_scan_bus for Root Device setup_bsp_ramtop, TOP MEM: msr.lo = 0xc0000000, msr.hi = 0x00000000 setup_bsp_ramtop, TOP MEM2: msr.lo = 0x40000000, msr.hi = 0x00000008 CPU_CLUSTER: 0 enabled DOMAIN: 0000 enabled CPU_CLUSTER: 0 scanning... PCI: 00:18.5 siblings=5 CPU: APIC: 00 enabled CPU: APIC: 01 enabled CPU: APIC: 02 enabled CPU: APIC: 03 enabled CPU: APIC: 04 enabled CPU: APIC: 05 enabled PCI: 00:19.5 siblings=5 CPU: APIC: 06 enabled CPU: APIC: 07 enabled CPU: APIC: 08 enabled CPU: APIC: 09 enabled CPU: APIC: 0a enabled CPU: APIC: 0b enabled PCI: 00:1a.5 siblings=5 CPU: APIC: 20 enabled CPU: APIC: 21 enabled CPU: APIC: 22 enabled CPU: APIC: 23 enabled CPU: APIC: 24 enabled CPU: APIC: 25 enabled PCI: 00:1b.5 siblings=5 CPU: APIC: 26 enabled CPU: APIC: 27 enabled CPU: APIC: 28 enabled CPU: APIC: 29 enabled CPU: APIC: 2a enabled CPU: APIC: 2b enabled scan_bus: scanning of bus CPU_CLUSTER: 0 took 220 usecs DOMAIN: 0000 scanning... PCI: pci_scan_bus for bus 00 PCI: 00:18.0 [1022/1600] bus ops PCI: 00:18.0 [1022/1600] enabled PCI: 00:18.1 [1022/1601] enabled PCI: 00:18.2 [1022/1602] enabled PCI: 00:18.3 [1022/1603] ops PCI: 00:18.3 [1022/1603] enabled PCI: 00:18.4 [1022/1604] ops PCI: 00:18.4 [1022/1604] enabled PCI: 00:18.5 [1022/1605] ops PCI: 00:18.5 [1022/1605] enabled PCI: 00:19.0 [1022/1600] bus ops PCI: 00:19.0 [1022/1600] enabled PCI: 00:19.1 [1022/1601] enabled PCI: 00:19.2 [1022/1602] enabled PCI: 00:19.3 [1022/1603] ops PCI: 00:19.3 [1022/1603] enabled PCI: 00:19.4 [1022/1604] ops PCI: 00:19.4 [1022/1604] enabled PCI: 00:19.5 [1022/1605] ops PCI: 00:19.5 [1022/1605] enabled PCI: 00:1a.0 [1022/1600] bus ops PCI: 00:1a.0 [1022/1600] enabled PCI: 00:1a.1 [1022/1601] enabled PCI: 00:1a.2 [1022/1602] enabled PCI: 00:1a.3 [1022/1603] ops PCI: 00:1a.3 [1022/1603] enabled PCI: 00:1a.4 [1022/1604] ops PCI: 00:1a.4 [1022/1604] enabled PCI: 00:1a.5 [1022/1605] ops PCI: 00:1a.5 [1022/1605] enabled PCI: 00:1b.0 [1022/1600] bus ops PCI: 00:1b.0 [1022/1600] enabled PCI: 00:1b.1 [1022/1601] enabled PCI: 00:1b.2 [1022/1602] enabled PCI: 00:1b.3 [1022/1603] ops PCI: 00:1b.3 [1022/1603] enabled PCI: 00:1b.4 [1022/1604] ops PCI: 00:1b.4 [1022/1604] enabled PCI: 00:1b.5 [1022/1605] ops PCI: 00:1b.5 [1022/1605] enabled PCI: 00:18.0 scanning... do_hypertransport_scan_chain for bus 00 sr5650_enable: dev=0012fae0, VID_DID=0x5a101002 Bus-0, Dev-0, Fun-0. enable_pcie_bar3 sr5650_gpp_sb_init: nb_dev=0x0012fae0, dev=0x0012f540, port=0x8 PciePowerOffGppPorts() port 8 NB_PCI_REG04 = 2. NB_PCI_REG84 = 3000010. NB_PCI_REG4C = 52042. Sysmem TOM = 0_c0000000 Sysmem TOM2 = 8_40000000 PCI: 00:00.0 [1002/5a10] ops PCI: 00:00.0 [1002/5a10] enabled Capability: type 0x08 @ 0xf0 flags: 0xa803 Capability: type 0x08 @ 0xf0 Capability: type 0x08 @ 0xc4 flags: 0x0280 PCI: 00:00.0 count: 0014 static_count: 0015 PCI: 00:00.0 [1002/5a10] enabled next_unitid: 0015 PCI: pci_scan_bus for bus 00 sr5650_enable: dev=0012fae0, VID_DID=0x5a101002 Bus-0, Dev-0, Fun-0. enable_pcie_bar3 sr5650_gpp_sb_init: nb_dev=0x0012fae0, dev=0x0012f540, port=0x8 PciePowerOffGppPorts() port 8 NB_PCI_REG04 = 2. NB_PCI_REG84 = 3000010. NB_PCI_REG4C = 52042. Sysmem TOM = 0_c0000000 Sysmem TOM2 = 8_40000000 PCI: 00:00.0 [1002/5a10] enabled sr5650_enable: dev=0012fa40, VID_DID=0xffffffff Bus-0, Dev-0, Fun-1. PCI: Static device PCI: 00:00.1 not found, disabling it. sr5650_enable: dev=0012f9a0, VID_DID=0x5a231002 Bus-0, Dev-0, Fun-2. PCI: 00:00.2 [1002/5a23] ops PCI: 00:00.2 [1002/5a23] enabled sr5650_enable: dev=0012f900, VID_DID=0xffffffff Bus-0, Dev-2,3, Fun-0. enable=1 sr5650_gpp_sb_init: nb_dev=0x0012fae0, dev=0x0012f900, port=0x2 PcieLinkTraining port=2:lc current state=1020304 sr5650_gpp_sb_init: port=0x2 hw_port=0x2 result=0 PciePowerOffGppPorts() port 2 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 Capability: type 0x05 @ 0xa0 Capability: type 0x0d @ 0xb0 Capability: type 0x08 @ 0xb8 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 Capability: type 0x05 @ 0xa0 Capability: type 0x0d @ 0xb0 Capability: type 0x08 @ 0xb8 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 Capability: type 0x05 @ 0xa0 Capability: type 0x0d @ 0xb0 Capability: type 0x08 @ 0xb8 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 PCI: 00:02.0 subordinate bus PCI Express PCI: 00:02.0 [1002/5a16] enabled sr5650_enable: dev=0012f860, VID_DID=0xffffffff Bus-0, Dev-2,3, Fun-0. enable=0 sr5650_enable: dev=0012f7c0, VID_DID=0xffffffff enable_pcie_bar3 Bus-0, Dev-4,5,6,7, Fun-0. enable=1 sr5650_gpp_sb_init: nb_dev=0x0012fae0, dev=0x0012f7c0, port=0x4 PcieLinkTraining port=4:lc current state=a0b0f10 addr=c0000000,bus=0,devfn=20 PcieTrainPort reg=0x10000 sr5650_gpp_sb_init: port=0x4 hw_port=0x4 result=1 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 Capability: type 0x05 @ 0xa0 Capability: type 0x0d @ 0xb0 Capability: type 0x08 @ 0xb8 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 Capability: type 0x05 @ 0xa0 Capability: type 0x0d @ 0xb0 Capability: type 0x08 @ 0xb8 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 Capability: type 0x05 @ 0xa0 Capability: type 0x0d @ 0xb0 Capability: type 0x08 @ 0xb8 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 PCI: 00:04.0 subordinate bus PCI Express PCI: 00:04.0 [1002/5a18] enabled sr5650_enable: dev=0012f720, VID_DID=0xffffffff enable_pcie_bar3 Bus-0, Dev-4,5,6,7, Fun-0. enable=0 sr5650_enable: dev=0012f680, VID_DID=0xffffffff enable_pcie_bar3 Bus-0, Dev-4,5,6,7, Fun-0. enable=0 sr5650_enable: dev=0012f5e0, VID_DID=0xffffffff enable_pcie_bar3 Bus-0, Dev-4,5,6,7, Fun-0. enable=0 sr5650_enable: dev=0012f540, VID_DID=0xffffffff Bus-0, Dev-8, Fun-0. enable=0 disable_pcie_bar3 sr5650_enable: dev=0012f4a0, VID_DID=0xffffffff Bus-0, Dev-9, 10, Fun-0. enable=1 enable_pcie_bar3 sr5650_gpp_sb_init: nb_dev=0x0012fae0, dev=0x0012f4a0, port=0x9 PcieLinkTraining port=5:lc current state=a0b0f10 addr=c0000000,bus=0,devfn=48 PcieTrainPort reg=0x10000 sr5650_gpp_sb_init: port=0x9 hw_port=0x5 result=1 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 Capability: type 0x05 @ 0xa0 Capability: type 0x0d @ 0xb0 Capability: type 0x08 @ 0xb8 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 Capability: type 0x05 @ 0xa0 Capability: type 0x0d @ 0xb0 Capability: type 0x08 @ 0xb8 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 Capability: type 0x05 @ 0xa0 Capability: type 0x0d @ 0xb0 Capability: type 0x08 @ 0xb8 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 PCI: 00:09.0 subordinate bus PCI Express PCI: 00:09.0 [1002/5a1c] enabled sr5650_enable: dev=0012f400, VID_DID=0xffffffff Bus-0, Dev-9, 10, Fun-0. enable=1 enable_pcie_bar3 sr5650_gpp_sb_init: nb_dev=0x0012fae0, dev=0x0012f400, port=0xa PcieLinkTraining port=6:lc current state=a0b0f10 addr=c0000000,bus=0,devfn=50 PcieTrainPort reg=0x10000 sr5650_gpp_sb_init: port=0xa hw_port=0x6 result=1 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 Capability: type 0x05 @ 0xa0 Capability: type 0x0d @ 0xb0 Capability: type 0x08 @ 0xb8 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 Capability: type 0x05 @ 0xa0 Capability: type 0x0d @ 0xb0 Capability: type 0x08 @ 0xb8 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 Capability: type 0x05 @ 0xa0 Capability: type 0x0d @ 0xb0 Capability: type 0x08 @ 0xb8 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 PCI: 00:0a.0 subordinate bus PCI Express PCI: 00:0a.0 [1002/5a1d] enabled sr5650_enable: dev=0012f360, VID_DID=0xffffffff Bus-0, Dev-11,12, Fun-0. enable=1 sr5650_gpp_sb_init: nb_dev=0x0012fae0, dev=0x0012f360, port=0xb PcieLinkTraining port=b:lc current state=a0b0f10 addr=c0000000,bus=0,devfn=58 PcieTrainPort reg=0x10000 sr5650_gpp_sb_init: port=0xb hw_port=0xb result=1 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 Capability: type 0x05 @ 0xa0 Capability: type 0x0d @ 0xb0 Capability: type 0x08 @ 0xb8 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 Capability: type 0x05 @ 0xa0 Capability: type 0x0d @ 0xb0 Capability: type 0x08 @ 0xb8 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 Capability: type 0x05 @ 0xa0 Capability: type 0x0d @ 0xb0 Capability: type 0x08 @ 0xb8 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 PCI: 00:0b.0 subordinate bus PCI Express PCI: 00:0b.0 [1002/5a1f] enabled sr5650_enable: dev=0012f2c0, VID_DID=0xffffffff Bus-0, Dev-11,12, Fun-0. enable=1 sr5650_gpp_sb_init: nb_dev=0x0012fae0, dev=0x0012f2c0, port=0xc PcieLinkTraining port=c:lc current state=3050607 sr5650_gpp_sb_init: port=0xc hw_port=0xc result=1 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 Capability: type 0x05 @ 0xa0 Capability: type 0x0d @ 0xb0 Capability: type 0x08 @ 0xb8 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 Capability: type 0x05 @ 0xa0 Capability: type 0x0d @ 0xb0 Capability: type 0x08 @ 0xb8 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 Capability: type 0x05 @ 0xa0 Capability: type 0x0d @ 0xb0 Capability: type 0x08 @ 0xb8 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 PCI: 00:0c.0 subordinate bus PCI Express PCI: 00:0c.0 [1002/5a20] enabled sr5650_enable: dev=0012f220, VID_DID=0xffffffff sr5650_gpp_sb_init: nb_dev=0x0012fae0, dev=0x0012f220, port=0xd PcieLinkTraining port=d:lc current state=20212210 addr=c0000000,bus=0,devfn=68 PcieTrainPort reg=0x10000 sr5650_gpp_sb_init: port=0xd hw_port=0xd result=1 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 Capability: type 0x05 @ 0xa0 Capability: type 0x0d @ 0xb0 Capability: type 0x08 @ 0xb8 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 Capability: type 0x05 @ 0xa0 Capability: type 0x0d @ 0xb0 Capability: type 0x08 @ 0xb8 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 Capability: type 0x05 @ 0xa0 Capability: type 0x0d @ 0xb0 Capability: type 0x08 @ 0xb8 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 PCI: 00:0d.0 subordinate bus PCI Express PCI: 00:0d.0 [1002/5a1e] enabled sb7xx_51xx_enable() PCI: 00:11.0 [1002/4390] ops PCI: 00:11.0 [1002/4390] enabled sb7xx_51xx_enable() PCI: 00:12.0 [1002/4397] ops PCI: 00:12.0 [1002/4397] enabled sb7xx_51xx_enable() PCI: 00:12.1 [1002/4398] ops PCI: 00:12.1 [1002/4398] enabled sb7xx_51xx_enable() PCI: 00:12.2 [1002/4396] ops PCI: 00:12.2 [1002/4396] enabled sb7xx_51xx_enable() PCI: 00:13.0 [1002/4397] ops PCI: 00:13.0 [1002/4397] enabled sb7xx_51xx_enable() PCI: 00:13.1 [1002/4398] ops PCI: 00:13.1 [1002/4398] enabled sb7xx_51xx_enable() PCI: 00:13.2 [1002/4396] ops PCI: 00:13.2 [1002/4396] enabled sb7xx_51xx_enable() PCI: 00:14.0 [1002/4385] bus ops PCI: 00:14.0 [1002/4385] enabled sb7xx_51xx_enable() PCI: 00:14.1 [1002/439c] ops PCI: 00:14.1 [1002/439c] enabled sb7xx_51xx_enable() PCI: 00:14.2 [1002/4383] ops PCI: 00:14.2 [1002/4383] enabled sb7xx_51xx_enable() PCI: 00:14.3 [1002/439d] bus ops PCI: 00:14.3 [1002/439d] enabled sb7xx_51xx_enable() PCI: 00:14.4 [1002/4384] bus ops PCI: 00:14.4 [1002/4384] enabled sb7xx_51xx_enable() PCI: 00:14.5 [1002/4399] ops PCI: 00:14.5 [1002/4399] enabled PCI: 00:02.0 scanning... do_pci_scan_bridge for PCI: 00:02.0 PCI: pci_scan_bus for bus 01 scan_bus: scanning of bus PCI: 00:02.0 took 30 usecs PCI: 00:04.0 scanning... do_pci_scan_bridge for PCI: 00:04.0 PCI: pci_scan_bus for bus 02 PCI: 02:00.0 [1000/0072] enabled Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x68 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 Enabling Common Clock Configuration PCIE CLK PM is not supported by endpointASPM: Enabled None scan_bus: scanning of bus PCI: 00:04.0 took 128 usecs PCI: 00:09.0 scanning... do_pci_scan_bridge for PCI: 00:09.0 PCI: pci_scan_bus for bus 03 PCI: 03:00.0 [8086/10d3] enabled Capability: type 0x01 @ 0xc8 Capability: type 0x05 @ 0xd0 Capability: type 0x10 @ 0xe0 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 Enabling Common Clock Configuration PCIE CLK PM is not supported by endpointASPM: Enabled None scan_bus: scanning of bus PCI: 00:09.0 took 226 usecs PCI: 00:0a.0 scanning... do_pci_scan_bridge for PCI: 00:0a.0 PCI: pci_scan_bus for bus 04 PCI: 04:00.0 [8086/10d3] enabled Capability: type 0x01 @ 0xc8 Capability: type 0x05 @ 0xd0 Capability: type 0x10 @ 0xe0 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 Enabling Common Clock Configuration PCIE CLK PM is not supported by endpointASPM: Enabled None scan_bus: scanning of bus PCI: 00:0a.0 took 140 usecs PCI: 00:0b.0 scanning... do_pci_scan_bridge for PCI: 00:0b.0 PCI: pci_scan_bus for bus 05 PCI: 05:00.0 [10de/11c0] enabled PCI: 05:00.1 [10de/0e0b] enabled Capability: type 0x01 @ 0x60 Capability: type 0x05 @ 0x68 Capability: type 0x10 @ 0x78 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 Enabling Common Clock Configuration ASPM: Enabled L0s Capability: type 0x01 @ 0x60 Capability: type 0x05 @ 0x68 Capability: type 0x10 @ 0x78 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 Enabling Common Clock Configuration ASPM: Enabled L0s scan_bus: scanning of bus PCI: 00:0b.0 took 231 usecs PCI: 00:0c.0 scanning... do_pci_scan_bridge for PCI: 00:0c.0 PCI: pci_scan_bus for bus 06 scan_bus: scanning of bus PCI: 00:0c.0 took 29 usecs PCI: 00:0d.0 scanning... do_pci_scan_bridge for PCI: 00:0d.0 PCI: pci_scan_bus for bus 07 PCI: 07:00.0 [1106/3483] enabled Capability: type 0x01 @ 0x80 Capability: type 0x05 @ 0x90 Capability: type 0x10 @ 0xc4 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 Enabling Common Clock Configuration ASPM: Enabled None scan_bus: scanning of bus PCI: 00:0d.0 took 155 usecs PCI: 00:14.0 scanning... scan_smbus for PCI: 00:14.0 smbus: PCI: 00:14.0[0]->I2C: 01:50 enabled smbus: PCI: 00:14.0[0]->I2C: 01:51 enabled smbus: PCI: 00:14.0[0]->I2C: 01:52 enabled smbus: PCI: 00:14.0[0]->I2C: 01:53 enabled smbus: PCI: 00:14.0[0]->I2C: 01:54 enabled smbus: PCI: 00:14.0[0]->I2C: 01:55 enabled smbus: PCI: 00:14.0[0]->I2C: 01:56 enabled smbus: PCI: 00:14.0[0]->I2C: 01:57 enabled smbus: PCI: 00:14.0[0]->I2C: 01:2f enabled scan_smbus for PCI: 00:14.0 done scan_bus: scanning of bus PCI: 00:14.0 took 12 usecs PCI: 00:14.3 scanning... scan_lpc_bus for PCI: 00:14.3 PNP: 002e.0 disabled PNP: 002e.1 disabled PNP: 002e.2 enabled PNP: 002e.3 enabled PNP: 002e.5 enabled PNP: 002e.106 disabled PNP: 002e.107 disabled PNP: 002e.207 disabled PNP: 002e.307 disabled PNP: 002e.407 disabled PNP: 002e.8 disabled PNP: 002e.108 disabled PNP: 002e.9 disabled PNP: 002e.109 disabled PNP: 002e.209 disabled PNP: 002e.309 disabled PNP: 002e.a enabled PNP: 002e.b enabled PNP: 002e.c disabled PNP: 002e.d disabled PNP: 002e.f disabled scan_lpc_bus for PCI: 00:14.3 done scan_bus: scanning of bus PCI: 00:14.3 took 488 usecs PCI: 00:14.4 scanning... do_pci_scan_bridge for PCI: 00:14.4 PCI: pci_scan_bus for bus 08 sb7xx_51xx_enable() PCI: 08:01.0 [1a03/2000] ops PCI: 08:01.0 [1a03/2000] enabled sb7xx_51xx_enable() PCI: 08:02.0 [11c1/5811] enabled sb7xx_51xx_enable() PCI: Static device PCI: 08:03.0 not found, disabling it. scan_bus: scanning of bus PCI: 00:14.4 took 119 usecs scan_bus: scanning of bus PCI: 00:18.0 took 1049670 usecs PCI: 00:19.0 scanning... scan_bus: scanning of bus PCI: 00:19.0 took 1 usecs PCI: 00:1a.0 scanning... scan_bus: scanning of bus PCI: 00:1a.0 took 1 usecs PCI: 00:1b.0 scanning... scan_bus: scanning of bus PCI: 00:1b.0 took 1 usecs DOMAIN: 0000 passpw: enabled DOMAIN: 0000 passpw: enabled DOMAIN: 0000 passpw: enabled DOMAIN: 0000 passpw: enabled scan_bus: scanning of bus DOMAIN: 0000 took 1049873 usecs root_dev_scan_bus for Root Device done scan_bus: scanning of bus Root Device took 1050099 usecs done BS: BS_DEV_ENUMERATE times (us): entry 0 run 1050448 exit 0 found VGA at PCI: 08:01.0 found VGA at PCI: 05:00.0 Setting up VGA for PCI: 05:00.0 Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:0b.0 Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:18.0 Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device Allocating resources... Reading resources... Root Device read_resources bus 0 link: 0 CPU_CLUSTER: 0 read_resources bus 0 link: 0 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done DOMAIN: 0000 read_resources bus 0 link: 0 PCI: 00:18.0 read_resources bus 0 link: 2 PCI: 00:18.0 read_resources bus 0 link: 2 done PCI: 00:18.0 read_resources bus 0 link: 3 PCI: 00:18.0 read_resources bus 0 link: 3 done PCI: 00:18.0 read_resources bus 0 link: 0 PCI: 00:18.0 read_resources bus 0 link: 0 done PCI: 00:18.0 read_resources bus 0 link: 1 sr5690_read_resource: PCI: 00:00.0 PCI: 00:02.0 read_resources bus 1 link: 0 PCI: 00:02.0 read_resources bus 1 link: 0 done PCI: 00:04.0 read_resources bus 2 link: 0 PCI: 00:04.0 read_resources bus 2 link: 0 done PCI: 00:09.0 read_resources bus 3 link: 0 PCI: 00:09.0 read_resources bus 3 link: 0 done PCI: 00:0a.0 read_resources bus 4 link: 0 PCI: 00:0a.0 read_resources bus 4 link: 0 done PCI: 00:0b.0 read_resources bus 5 link: 0 PCI: 00:0b.0 read_resources bus 5 link: 0 done PCI: 00:0c.0 read_resources bus 6 link: 0 PCI: 00:0c.0 read_resources bus 6 link: 0 done PCI: 00:0d.0 read_resources bus 7 link: 0 PCI: 00:0d.0 read_resources bus 7 link: 0 done PCI: 00:14.0 read_resources bus 1 link: 0 I2C: 01:50 missing read_resources I2C: 01:51 missing read_resources I2C: 01:52 missing read_resources I2C: 01:53 missing read_resources I2C: 01:54 missing read_resources I2C: 01:55 missing read_resources I2C: 01:56 missing read_resources I2C: 01:57 missing read_resources PCI: 00:14.0 read_resources bus 1 link: 0 done PCI: 00:14.3 read_resources bus 0 link: 0 PCI: 00:14.3 read_resources bus 0 link: 0 done PCI: 00:14.4 read_resources bus 8 link: 0 PCI: 00:14.4 read_resources bus 8 link: 0 done PCI: 00:18.0 read_resources bus 0 link: 1 done PCI: 00:18.4 read_resources bus 0 link: 0 PCI: 00:18.4 read_resources bus 0 link: 0 done PCI: 00:18.4 read_resources bus 0 link: 1 PCI: 00:18.4 read_resources bus 0 link: 1 done PCI: 00:18.4 read_resources bus 0 link: 2 PCI: 00:18.4 read_resources bus 0 link: 2 done PCI: 00:18.4 read_resources bus 0 link: 3 PCI: 00:18.4 read_resources bus 0 link: 3 done PCI: 00:19.0 read_resources bus 0 link: 3 PCI: 00:19.0 read_resources bus 0 link: 3 done PCI: 00:19.0 read_resources bus 0 link: 2 PCI: 00:19.0 read_resources bus 0 link: 2 done PCI: 00:19.0 read_resources bus 0 link: 0 PCI: 00:19.0 read_resources bus 0 link: 0 done PCI: 00:19.0 read_resources bus 0 link: 1 PCI: 00:19.0 read_resources bus 0 link: 1 done PCI: 00:19.4 read_resources bus 0 link: 0 PCI: 00:19.4 read_resources bus 0 link: 0 done PCI: 00:19.4 read_resources bus 0 link: 1 PCI: 00:19.4 read_resources bus 0 link: 1 done PCI: 00:19.4 read_resources bus 0 link: 2 PCI: 00:19.4 read_resources bus 0 link: 2 done PCI: 00:19.4 read_resources bus 0 link: 3 PCI: 00:19.4 read_resources bus 0 link: 3 done PCI: 00:1a.0 read_resources bus 0 link: 3 PCI: 00:1a.0 read_resources bus 0 link: 3 done PCI: 00:1a.0 read_resources bus 0 link: 2 PCI: 00:1a.0 read_resources bus 0 link: 2 done PCI: 00:1a.0 read_resources bus 0 link: 0 PCI: 00:1a.0 read_resources bus 0 link: 0 done PCI: 00:1a.0 read_resources bus 0 link: 1 PCI: 00:1a.0 read_resources bus 0 link: 1 done PCI: 00:1a.4 read_resources bus 0 link: 0 PCI: 00:1a.4 read_resources bus 0 link: 0 done PCI: 00:1a.4 read_resources bus 0 link: 1 PCI: 00:1a.4 read_resources bus 0 link: 1 done PCI: 00:1a.4 read_resources bus 0 link: 2 PCI: 00:1a.4 read_resources bus 0 link: 2 done PCI: 00:1a.4 read_resources bus 0 link: 3 PCI: 00:1a.4 read_resources bus 0 link: 3 done PCI: 00:1b.0 read_resources bus 0 link: 3 PCI: 00:1b.0 read_resources bus 0 link: 3 done PCI: 00:1b.0 read_resources bus 0 link: 2 PCI: 00:1b.0 read_resources bus 0 link: 2 done PCI: 00:1b.0 read_resources bus 0 link: 0 PCI: 00:1b.0 read_resources bus 0 link: 0 done PCI: 00:1b.0 read_resources bus 0 link: 1 PCI: 00:1b.0 read_resources bus 0 link: 1 done PCI: 00:1b.4 read_resources bus 0 link: 0 PCI: 00:1b.4 read_resources bus 0 link: 0 done PCI: 00:1b.4 read_resources bus 0 link: 1 PCI: 00:1b.4 read_resources bus 0 link: 1 done PCI: 00:1b.4 read_resources bus 0 link: 2 PCI: 00:1b.4 read_resources bus 0 link: 2 done PCI: 00:1b.4 read_resources bus 0 link: 3 PCI: 00:1b.4 read_resources bus 0 link: 3 done DOMAIN: 0000 read_resources bus 0 link: 0 done Root Device read_resources bus 0 link: 0 done Done reading resources. Show resources in subtree (Root Device)...After reading. Root Device child on link 0 CPU_CLUSTER: 0 CPU_CLUSTER: 0 child on link 0 APIC: 00 APIC: 00 APIC: 01 APIC: 02 APIC: 03 APIC: 04 APIC: 05 APIC: 06 APIC: 07 APIC: 08 APIC: 09 APIC: 0a APIC: 0b APIC: 20 APIC: 21 APIC: 22 APIC: 23 APIC: 24 APIC: 25 APIC: 26 APIC: 27 APIC: 28 APIC: 29 APIC: 2a APIC: 2b DOMAIN: 0000 child on link 0 PCI: 00:18.0 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100 DOMAIN: 0000 resource base c0000000 size 10000000 align 28 gran 28 limit ffffffffffffffff flags f0000200 index c0010058 DOMAIN: 0000 resource base 0 size c0000000 align 0 gran 0 limit 0 flags e0004200 index 7 PCI: 00:18.0 PCI: 00:18.0 resource base 0 size 0 align 20 gran 20 limit ffffffffff flags 81200 index 110b0 PCI: 00:18.0 resource base 0 size 0 align 20 gran 20 limit ffffffffff flags 80200 index 110b8 PCI: 00:18.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80100 index 110d8 PCI: 00:00.0 PCI: 00:00.0 resource base 0 size 100 align 12 gran 8 limit ffffffff flags 1200 index fc PCI: 00:00.1 PCI: 00:00.2 PCI: 00:00.2 resource base 0 size 4000 align 14 gran 14 limit ffffffff flags 10000200 index 44 PCI: 00:02.0 PCI: 00:02.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c PCI: 00:02.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 PCI: 00:02.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 00:03.0 PCI: 00:04.0 child on link 0 PCI: 02:00.0 PCI: 00:04.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c PCI: 00:04.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 PCI: 00:04.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 02:00.0 PCI: 02:00.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 10 PCI: 02:00.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 14 PCI: 02:00.0 resource base 0 size 40000 align 18 gran 18 limit ffffffffffffffff flags 201 index 1c PCI: 02:00.0 resource base 0 size 80000 align 19 gran 19 limit ffffffff flags 2200 index 30 PCI: 00:05.0 PCI: 00:06.0 PCI: 00:07.0 PCI: 00:08.0 PCI: 00:09.0 child on link 0 PCI: 03:00.0 PCI: 00:09.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c PCI: 00:09.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 PCI: 00:09.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 03:00.0 PCI: 03:00.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 200 index 10 PCI: 03:00.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 18 PCI: 03:00.0 resource base 0 size 4000 align 14 gran 14 limit ffffffff flags 200 index 1c PCI: 00:0a.0 child on link 0 PCI: 04:00.0 PCI: 00:0a.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c PCI: 00:0a.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 PCI: 00:0a.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 04:00.0 PCI: 04:00.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 200 index 10 PCI: 04:00.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 18 PCI: 04:00.0 resource base 0 size 4000 align 14 gran 14 limit ffffffff flags 200 index 1c PCI: 00:0b.0 child on link 0 PCI: 05:00.0 PCI: 00:0b.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c PCI: 00:0b.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 PCI: 00:0b.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 05:00.0 PCI: 05:00.0 resource base 0 size 1000000 align 24 gran 24 limit ffffffff flags 200 index 10 PCI: 05:00.0 resource base 0 size 8000000 align 27 gran 27 limit ffffffffffffffff flags 1201 index 14 PCI: 05:00.0 resource base 0 size 2000000 align 25 gran 25 limit ffffffffffffffff flags 1201 index 1c PCI: 05:00.0 resource base 0 size 80 align 7 gran 7 limit ffff flags 100 index 24 PCI: 05:00.0 resource base 0 size 80000 align 19 gran 19 limit ffffffff flags 2200 index 30 PCI: 05:00.1 PCI: 05:00.1 resource base 0 size 4000 align 14 gran 14 limit ffffffff flags 200 index 10 PCI: 00:0c.0 PCI: 00:0c.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c PCI: 00:0c.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 PCI: 00:0c.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 00:0d.0 child on link 0 PCI: 07:00.0 PCI: 00:0d.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c PCI: 00:0d.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 PCI: 00:0d.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 07:00.0 PCI: 07:00.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10 PCI: 00:11.0 PCI: 00:11.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10 PCI: 00:11.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14 PCI: 00:11.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18 PCI: 00:11.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c PCI: 00:11.0 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20 PCI: 00:11.0 resource base 0 size 400 align 12 gran 10 limit ffffffff flags 200 index 24 PCI: 00:12.0 PCI: 00:12.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 PCI: 00:12.1 PCI: 00:12.1 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 PCI: 00:12.2 PCI: 00:12.2 resource base 0 size 100 align 12 gran 8 limit ffffffff flags 200 index 10 PCI: 00:13.0 PCI: 00:13.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 PCI: 00:13.1 PCI: 00:13.1 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 PCI: 00:13.2 PCI: 00:13.2 resource base 0 size 100 align 12 gran 8 limit ffffffff flags 200 index 10 PCI: 00:14.0 child on link 0 I2C: 01:50 PCI: 00:14.0 resource base fec00000 size 1000 align 8 gran 8 limit ffffffff flags d0000200 index 74 PCI: 00:14.0 resource base feb00000 size 1000 align 8 gran 8 limit ffffffff flags d0000200 index 9c PCI: 00:14.0 resource base fed00000 size 400 align 8 gran 8 limit ffffffff flags d0000200 index b4 PCI: 00:14.0 resource base b00 size 10 align 8 gran 8 limit ffff flags d0000100 index 90 PCI: 00:14.0 resource base b20 size 10 align 8 gran 8 limit ffff flags d0000100 index 58 I2C: 01:50 I2C: 01:51 I2C: 01:52 I2C: 01:53 I2C: 01:54 I2C: 01:55 I2C: 01:56 I2C: 01:57 I2C: 01:2f PCI: 00:14.1 PCI: 00:14.1 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10 PCI: 00:14.1 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14 PCI: 00:14.1 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18 PCI: 00:14.1 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c PCI: 00:14.1 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20 PCI: 00:14.2 PCI: 00:14.2 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10 PCI: 00:14.3 child on link 0 PNP: 002e.0 PCI: 00:14.3 resource base 0 size 1 align 12 gran 0 limit ffffffff flags 200 index a0 PCI: 00:14.3 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000 PCI: 00:14.3 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100 PCI: 00:14.3 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3 PNP: 002e.0 PNP: 002e.0 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 60 PNP: 002e.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 002e.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 PNP: 002e.1 PNP: 002e.1 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 60 PNP: 002e.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 002e.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 PNP: 002e.2 PNP: 002e.2 resource base 3f8 size 8 align 3 gran 3 limit fff flags c0000100 index 60 PNP: 002e.2 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.3 PNP: 002e.3 resource base 2f8 size 8 align 3 gran 3 limit fff flags c0000100 index 60 PNP: 002e.3 resource base 3 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.5 PNP: 002e.5 resource base 60 size 1 align 0 gran 0 limit ffffffff flags c0000100 index 60 PNP: 002e.5 resource base 64 size 1 align 0 gran 0 limit ffffffff flags c0000100 index 62 PNP: 002e.5 resource base 1 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.5 resource base c size 1 align 0 gran 0 limit 0 flags c0000400 index 72 PNP: 002e.106 PNP: 002e.106 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 62 PNP: 002e.107 PNP: 002e.207 PNP: 002e.307 PNP: 002e.407 PNP: 002e.8 PNP: 002e.108 PNP: 002e.9 PNP: 002e.109 PNP: 002e.209 PNP: 002e.309 PNP: 002e.a PNP: 002e.b PNP: 002e.b resource base 290 size 2 align 1 gran 1 limit fff flags c0000100 index 60 PNP: 002e.b resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 002e.c PNP: 002e.d PNP: 002e.f PCI: 00:14.4 child on link 0 PCI: 08:01.0 PCI: 00:14.4 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c PCI: 00:14.4 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 81202 index 24 PCI: 00:14.4 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 08:01.0 PCI: 08:01.0 resource base 0 size 800000 align 23 gran 23 limit ffffffff flags 200 index 10 PCI: 08:01.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 200 index 14 PCI: 08:01.0 resource base 0 size 80 align 7 gran 7 limit ffff flags 100 index 18 PCI: 08:02.0 PCI: 08:02.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 PCI: 08:03.0 PCI: 00:14.5 PCI: 00:14.5 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 PCI: 00:18.1 PCI: 00:18.2 PCI: 00:18.3 PCI: 00:18.3 resource base 0 size 4000000 align 26 gran 26 limit ffffffff flags 200 index 94 PCI: 00:18.4 PCI: 00:18.5 PCI: 00:19.0 PCI: 00:19.1 PCI: 00:19.2 PCI: 00:19.3 PCI: 00:19.4 PCI: 00:19.5 PCI: 00:1a.0 PCI: 00:1a.1 PCI: 00:1a.2 PCI: 00:1a.3 PCI: 00:1a.4 PCI: 00:1a.5 PCI: 00:1b.0 PCI: 00:1b.1 PCI: 00:1b.2 PCI: 00:1b.3 PCI: 00:1b.4 PCI: 00:1b.5 DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff PCI: 00:18.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff PCI: 00:02.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff PCI: 00:02.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done PCI: 00:04.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff PCI: 02:00.0 10 * [0x0 - 0xff] io PCI: 00:04.0 io: base: 100 size: 1000 align: 12 gran: 12 limit: ffff done PCI: 00:09.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff PCI: 03:00.0 18 * [0x0 - 0x1f] io PCI: 00:09.0 io: base: 20 size: 1000 align: 12 gran: 12 limit: ffff done PCI: 00:0a.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff PCI: 04:00.0 18 * [0x0 - 0x1f] io PCI: 00:0a.0 io: base: 20 size: 1000 align: 12 gran: 12 limit: ffff done PCI: 00:0b.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff PCI: 05:00.0 24 * [0x0 - 0x7f] io PCI: 00:0b.0 io: base: 80 size: 1000 align: 12 gran: 12 limit: ffff done PCI: 00:0c.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff PCI: 00:0c.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done PCI: 00:0d.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff PCI: 00:0d.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done PCI: 00:14.4 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff PCI: 08:01.0 18 * [0x0 - 0x7f] io PCI: 00:14.4 io: base: 80 size: 1000 align: 12 gran: 12 limit: ffff done PCI: 00:04.0 1c * [0x0 - 0xfff] io PCI: 00:09.0 1c * [0x1000 - 0x1fff] io PCI: 00:0a.0 1c * [0x2000 - 0x2fff] io PCI: 00:0b.0 1c * [0x3000 - 0x3fff] io PCI: 00:14.4 1c * [0x4000 - 0x4fff] io PCI: 00:11.0 20 * [0x5000 - 0x500f] io PCI: 00:14.1 20 * [0x5010 - 0x501f] io PCI: 00:11.0 10 * [0x5020 - 0x5027] io PCI: 00:11.0 18 * [0x5028 - 0x502f] io PCI: 00:14.1 10 * [0x5030 - 0x5037] io PCI: 00:14.1 18 * [0x5038 - 0x503f] io PCI: 00:11.0 14 * [0x5040 - 0x5043] io PCI: 00:11.0 1c * [0x5044 - 0x5047] io PCI: 00:14.1 14 * [0x5048 - 0x504b] io PCI: 00:14.1 1c * [0x504c - 0x504f] io PCI: 00:18.0 io: base: 5050 size: 6000 align: 12 gran: 12 limit: ffff done PCI: 00:18.0 110d8 * [0x0 - 0x5fff] io DOMAIN: 0000 io: base: 6000 size: 6000 align: 12 gran: 0 limit: ffff done DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff PCI: 00:18.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffff PCI: 00:02.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 00:02.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done PCI: 00:04.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 00:04.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done PCI: 00:09.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 00:09.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done PCI: 00:0a.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 00:0a.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done PCI: 00:0b.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 05:00.0 14 * [0x0 - 0x7ffffff] prefmem PCI: 05:00.0 1c * [0x8000000 - 0x9ffffff] prefmem PCI: 00:0b.0 prefmem: base: a000000 size: a000000 align: 27 gran: 20 limit: ffffffffffffffff done PCI: 00:0c.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 00:0c.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done PCI: 00:0d.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 00:0d.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done PCI: 00:14.4 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 00:14.4 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done PCI: 00:0b.0 24 * [0x0 - 0x9ffffff] prefmem PCI: 00:00.0 fc * [0xa000000 - 0xa0000ff] prefmem PCI: 00:18.0 prefmem: base: a000100 size: a100000 align: 27 gran: 20 limit: ffffffff done PCI: 00:18.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffff PCI: 00:02.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 00:02.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done PCI: 00:04.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 02:00.0 30 * [0x0 - 0x7ffff] mem PCI: 02:00.0 1c * [0x80000 - 0xbffff] mem PCI: 02:00.0 14 * [0xc0000 - 0xc3fff] mem PCI: 00:04.0 mem: base: c4000 size: 100000 align: 20 gran: 20 limit: ffffffff done PCI: 00:09.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 03:00.0 10 * [0x0 - 0x1ffff] mem PCI: 03:00.0 1c * [0x20000 - 0x23fff] mem PCI: 00:09.0 mem: base: 24000 size: 100000 align: 20 gran: 20 limit: ffffffff done PCI: 00:0a.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 04:00.0 10 * [0x0 - 0x1ffff] mem PCI: 04:00.0 1c * [0x20000 - 0x23fff] mem PCI: 00:0a.0 mem: base: 24000 size: 100000 align: 20 gran: 20 limit: ffffffff done PCI: 00:0b.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 05:00.0 10 * [0x0 - 0xffffff] mem PCI: 05:00.0 30 * [0x1000000 - 0x107ffff] mem PCI: 05:00.1 10 * [0x1080000 - 0x1083fff] mem PCI: 00:0b.0 mem: base: 1084000 size: 1100000 align: 24 gran: 20 limit: ffffffff done PCI: 00:0c.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 00:0c.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done PCI: 00:0d.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 07:00.0 10 * [0x0 - 0xfff] mem PCI: 00:0d.0 mem: base: 1000 size: 100000 align: 20 gran: 20 limit: ffffffff done PCI: 00:14.4 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 08:01.0 10 * [0x0 - 0x7fffff] mem PCI: 08:01.0 14 * [0x800000 - 0x81ffff] mem PCI: 08:02.0 10 * [0x820000 - 0x820fff] mem PCI: 00:14.4 mem: base: 821000 size: 900000 align: 23 gran: 20 limit: ffffffff done PCI: 00:0b.0 20 * [0x0 - 0x10fffff] mem PCI: 00:14.4 20 * [0x1800000 - 0x20fffff] mem PCI: 00:04.0 20 * [0x2100000 - 0x21fffff] mem PCI: 00:09.0 20 * [0x2200000 - 0x22fffff] mem PCI: 00:0a.0 20 * [0x2300000 - 0x23fffff] mem PCI: 00:0d.0 20 * [0x2400000 - 0x24fffff] mem PCI: 00:00.2 44 * [0x2500000 - 0x2503fff] mem PCI: 00:14.2 10 * [0x2504000 - 0x2507fff] mem PCI: 00:12.0 10 * [0x2508000 - 0x2508fff] mem PCI: 00:12.1 10 * [0x2509000 - 0x2509fff] mem PCI: 00:13.0 10 * [0x250a000 - 0x250afff] mem PCI: 00:13.1 10 * [0x250b000 - 0x250bfff] mem PCI: 00:14.5 10 * [0x250c000 - 0x250cfff] mem PCI: 00:11.0 24 * [0x250d000 - 0x250d3ff] mem PCI: 00:12.2 10 * [0x250e000 - 0x250e0ff] mem PCI: 00:13.2 10 * [0x250f000 - 0x250f0ff] mem PCI: 00:14.3 a0 * [0x2510000 - 0x2510000] mem PCI: 00:18.0 mem: base: 2510001 size: 2600000 align: 24 gran: 20 limit: ffffffff done PCI: 00:18.0 110b0 * [0x0 - 0xa0fffff] prefmem PCI: 00:18.3 94 * [0xc000000 - 0xfffffff] mem PCI: 00:18.0 110b8 * [0x10000000 - 0x125fffff] mem DOMAIN: 0000 mem: base: 12600000 size: 12600000 align: 27 gran: 0 limit: ffffffff done avoid_fixed_resources: DOMAIN: 0000 avoid_fixed_resources:@DOMAIN: 0000 10000000 limit 0000ffff avoid_fixed_resources:@DOMAIN: 0000 10000100 limit ffffffff constrain_resources: DOMAIN: 0000 c0010058 base c0000000 limit cfffffff mem (fixed) constrain_resources: DOMAIN: 0000 07 base 00000000 limit bfffffff mem (fixed) constrain_resources: PCI: 00:14.0 74 base fec00000 limit fec00fff mem (fixed) constrain_resources: PCI: 00:14.0 9c base feb00000 limit feb00fff mem (fixed) constrain_resources: PCI: 00:14.0 90 base 00000b00 limit 00000b0f io (fixed) constrain_resources: PCI: 00:14.0 58 base 00000b20 limit 00000b2f io (fixed) constrain_resources: PCI: 00:14.3 10000000 base 00000000 limit 00000fff io (fixed) avoid_fixed_resources:@DOMAIN: 0000 10000000 base 00001000 limit 0000ffff avoid_fixed_resources:@DOMAIN: 0000 10000100 base e8000000 limit feafffff Setting resources... DOMAIN: 0000 io: base:1000 size:6000 align:12 gran:0 limit:ffff PCI: 00:18.0 110d8 * [0x1000 - 0x6fff] io DOMAIN: 0000 io: next_base: 7000 size: 6000 align: 12 gran: 0 done PCI: 00:18.0 io: base:1000 size:6000 align:12 gran:12 limit:6fff PCI: 00:04.0 1c * [0x1000 - 0x1fff] io PCI: 00:09.0 1c * [0x2000 - 0x2fff] io PCI: 00:0a.0 1c * [0x3000 - 0x3fff] io PCI: 00:0b.0 1c * [0x4000 - 0x4fff] io PCI: 00:14.4 1c * [0x5000 - 0x5fff] io PCI: 00:11.0 20 * [0x6000 - 0x600f] io PCI: 00:14.1 20 * [0x6010 - 0x601f] io PCI: 00:11.0 10 * [0x6020 - 0x6027] io PCI: 00:11.0 18 * [0x6028 - 0x602f] io PCI: 00:14.1 10 * [0x6030 - 0x6037] io PCI: 00:14.1 18 * [0x6038 - 0x603f] io PCI: 00:11.0 14 * [0x6040 - 0x6043] io PCI: 00:11.0 1c * [0x6044 - 0x6047] io PCI: 00:14.1 14 * [0x6048 - 0x604b] io PCI: 00:14.1 1c * [0x604c - 0x604f] io PCI: 00:18.0 io: next_base: 6050 size: 6000 align: 12 gran: 12 done PCI: 00:02.0 io: base:6fff size:0 align:12 gran:12 limit:6fff PCI: 00:02.0 io: next_base: 6fff size: 0 align: 12 gran: 12 done PCI: 00:04.0 io: base:1000 size:1000 align:12 gran:12 limit:1fff PCI: 02:00.0 10 * [0x1000 - 0x10ff] io PCI: 00:04.0 io: next_base: 1100 size: 1000 align: 12 gran: 12 done PCI: 00:09.0 io: base:2000 size:1000 align:12 gran:12 limit:2fff PCI: 03:00.0 18 * [0x2000 - 0x201f] io PCI: 00:09.0 io: next_base: 2020 size: 1000 align: 12 gran: 12 done PCI: 00:0a.0 io: base:3000 size:1000 align:12 gran:12 limit:3fff PCI: 04:00.0 18 * [0x3000 - 0x301f] io PCI: 00:0a.0 io: next_base: 3020 size: 1000 align: 12 gran: 12 done PCI: 00:0b.0 io: base:4000 size:1000 align:12 gran:12 limit:4fff PCI: 05:00.0 24 * [0x4000 - 0x407f] io PCI: 00:0b.0 io: next_base: 4080 size: 1000 align: 12 gran: 12 done PCI: 00:0c.0 io: base:6fff size:0 align:12 gran:12 limit:6fff PCI: 00:0c.0 io: next_base: 6fff size: 0 align: 12 gran: 12 done PCI: 00:0d.0 io: base:6fff size:0 align:12 gran:12 limit:6fff PCI: 00:0d.0 io: next_base: 6fff size: 0 align: 12 gran: 12 done PCI: 00:14.4 io: base:5000 size:1000 align:12 gran:12 limit:5fff PCI: 08:01.0 18 * [0x5000 - 0x507f] io PCI: 00:14.4 io: next_base: 5080 size: 1000 align: 12 gran: 12 done DOMAIN: 0000 mem: base:e8000000 size:12600000 align:27 gran:0 limit:feafffff PCI: 00:18.0 110b0 * [0xe8000000 - 0xf20fffff] prefmem PCI: 00:18.3 94 * [0xf4000000 - 0xf7ffffff] mem PCI: 00:18.0 110b8 * [0xf8000000 - 0xfa5fffff] mem DOMAIN: 0000 mem: next_base: fa600000 size: 12600000 align: 27 gran: 0 done PCI: 00:18.0 prefmem: base:e8000000 size:a100000 align:27 gran:20 limit:f20fffff PCI: 00:0b.0 24 * [0xe8000000 - 0xf1ffffff] prefmem PCI: 00:00.0 fc * [0xf2000000 - 0xf20000ff] prefmem PCI: 00:18.0 prefmem: next_base: f2000100 size: a100000 align: 27 gran: 20 done PCI: 00:02.0 prefmem: base:f20fffff size:0 align:20 gran:20 limit:f20fffff PCI: 00:02.0 prefmem: next_base: f20fffff size: 0 align: 20 gran: 20 done PCI: 00:04.0 prefmem: base:f20fffff size:0 align:20 gran:20 limit:f20fffff PCI: 00:04.0 prefmem: next_base: f20fffff size: 0 align: 20 gran: 20 done PCI: 00:09.0 prefmem: base:f20fffff size:0 align:20 gran:20 limit:f20fffff PCI: 00:09.0 prefmem: next_base: f20fffff size: 0 align: 20 gran: 20 done PCI: 00:0a.0 prefmem: base:f20fffff size:0 align:20 gran:20 limit:f20fffff PCI: 00:0a.0 prefmem: next_base: f20fffff size: 0 align: 20 gran: 20 done PCI: 00:0b.0 prefmem: base:e8000000 size:a000000 align:27 gran:20 limit:f1ffffff PCI: 05:00.0 14 * [0xe8000000 - 0xefffffff] prefmem PCI: 05:00.0 1c * [0xf0000000 - 0xf1ffffff] prefmem PCI: 00:0b.0 prefmem: next_base: f2000000 size: a000000 align: 27 gran: 20 done PCI: 00:0c.0 prefmem: base:f20fffff size:0 align:20 gran:20 limit:f20fffff PCI: 00:0c.0 prefmem: next_base: f20fffff size: 0 align: 20 gran: 20 done PCI: 00:0d.0 prefmem: base:f20fffff size:0 align:20 gran:20 limit:f20fffff PCI: 00:0d.0 prefmem: next_base: f20fffff size: 0 align: 20 gran: 20 done PCI: 00:14.4 prefmem: base:f20fffff size:0 align:20 gran:20 limit:f20fffff PCI: 00:14.4 prefmem: next_base: f20fffff size: 0 align: 20 gran: 20 done PCI: 00:18.0 mem: base:f8000000 size:2600000 align:24 gran:20 limit:fa5fffff PCI: 00:0b.0 20 * [0xf8000000 - 0xf90fffff] mem PCI: 00:14.4 20 * [0xf9800000 - 0xfa0fffff] mem PCI: 00:04.0 20 * [0xfa100000 - 0xfa1fffff] mem PCI: 00:09.0 20 * [0xfa200000 - 0xfa2fffff] mem PCI: 00:0a.0 20 * [0xfa300000 - 0xfa3fffff] mem PCI: 00:0d.0 20 * [0xfa400000 - 0xfa4fffff] mem PCI: 00:00.2 44 * [0xfa500000 - 0xfa503fff] mem PCI: 00:14.2 10 * [0xfa504000 - 0xfa507fff] mem PCI: 00:12.0 10 * [0xfa508000 - 0xfa508fff] mem PCI: 00:12.1 10 * [0xfa509000 - 0xfa509fff] mem PCI: 00:13.0 10 * [0xfa50a000 - 0xfa50afff] mem PCI: 00:13.1 10 * [0xfa50b000 - 0xfa50bfff] mem PCI: 00:14.5 10 * [0xfa50c000 - 0xfa50cfff] mem PCI: 00:11.0 24 * [0xfa50d000 - 0xfa50d3ff] mem PCI: 00:12.2 10 * [0xfa50e000 - 0xfa50e0ff] mem PCI: 00:13.2 10 * [0xfa50f000 - 0xfa50f0ff] mem PCI: 00:14.3 a0 * [0xfa510000 - 0xfa510000] mem PCI: 00:18.0 mem: next_base: fa510001 size: 2600000 align: 24 gran: 20 done PCI: 00:02.0 mem: base:fa5fffff size:0 align:20 gran:20 limit:fa5fffff PCI: 00:02.0 mem: next_base: fa5fffff size: 0 align: 20 gran: 20 done PCI: 00:04.0 mem: base:fa100000 size:100000 align:20 gran:20 limit:fa1fffff PCI: 02:00.0 30 * [0xfa100000 - 0xfa17ffff] mem PCI: 02:00.0 1c * [0xfa180000 - 0xfa1bffff] mem PCI: 02:00.0 14 * [0xfa1c0000 - 0xfa1c3fff] mem PCI: 00:04.0 mem: next_base: fa1c4000 size: 100000 align: 20 gran: 20 done PCI: 00:09.0 mem: base:fa200000 size:100000 align:20 gran:20 limit:fa2fffff PCI: 03:00.0 10 * [0xfa200000 - 0xfa21ffff] mem PCI: 03:00.0 1c * [0xfa220000 - 0xfa223fff] mem PCI: 00:09.0 mem: next_base: fa224000 size: 100000 align: 20 gran: 20 done PCI: 00:0a.0 mem: base:fa300000 size:100000 align:20 gran:20 limit:fa3fffff PCI: 04:00.0 10 * [0xfa300000 - 0xfa31ffff] mem PCI: 04:00.0 1c * [0xfa320000 - 0xfa323fff] mem PCI: 00:0a.0 mem: next_base: fa324000 size: 100000 align: 20 gran: 20 done PCI: 00:0b.0 mem: base:f8000000 size:1100000 align:24 gran:20 limit:f90fffff PCI: 05:00.0 10 * [0xf8000000 - 0xf8ffffff] mem PCI: 05:00.0 30 * [0xf9000000 - 0xf907ffff] mem PCI: 05:00.1 10 * [0xf9080000 - 0xf9083fff] mem PCI: 00:0b.0 mem: next_base: f9084000 size: 1100000 align: 24 gran: 20 done PCI: 00:0c.0 mem: base:fa5fffff size:0 align:20 gran:20 limit:fa5fffff PCI: 00:0c.0 mem: next_base: fa5fffff size: 0 align: 20 gran: 20 done PCI: 00:0d.0 mem: base:fa400000 size:100000 align:20 gran:20 limit:fa4fffff PCI: 07:00.0 10 * [0xfa400000 - 0xfa400fff] mem PCI: 00:0d.0 mem: next_base: fa401000 size: 100000 align: 20 gran: 20 done PCI: 00:14.4 mem: base:f9800000 size:900000 align:23 gran:20 limit:fa0fffff PCI: 08:01.0 10 * [0xf9800000 - 0xf9ffffff] mem PCI: 08:01.0 14 * [0xfa000000 - 0xfa01ffff] mem PCI: 08:02.0 10 * [0xfa020000 - 0xfa020fff] mem PCI: 00:14.4 mem: next_base: fa021000 size: 900000 align: 23 gran: 20 done Root Device assign_resources, bus 0 link: 0 0: mmio_basek=00300000, basek=00400000, limitk=00900000 1: mmio_basek=00300000, basek=00900000, limitk=01100000 2: mmio_basek=00300000, basek=01100000, limitk=01900000 3: mmio_basek=00300000, basek=01900000, limitk=02100000 DOMAIN: 0000 assign_resources, bus 0 link: 0 VGA: PCI: 00:18.0 (aka node 0) link 1 has VGA device PCI: 00:18.0 111b8 <- [0x00000a0000 - 0x00000bffff] size 0x00020000 gran 0x00 mem <node 0 link 1> PCI: 00:18.0 110b0 <- [0x00e8000000 - 0x00f20fffff] size 0x0a100000 gran 0x14 prefmem <node 0 link 1> PCI: 00:18.0 110b8 <- [0x00f8000000 - 0x00fa5fffff] size 0x02600000 gran 0x14 mem <node 0 link 1> PCI: 00:18.0 110d8 <- [0x0000001000 - 0x0000006fff] size 0x00006000 gran 0x0c io <node 0 link 1> PCI: 00:18.0 assign_resources, bus 0 link: 1 PCI: 00:00.0 sr5690_set_resources sr5690_set_resources: PCI: 00:00.0[0x1c] base = c0000000 limit = cfffffff PCI: 00:00.0 c0010058 <- [0x00c0000000 - 0x00cfffffff] size 0x10000000 gran 0x1c mem <mmconfig> sr5690_set_resources: PCI: 00:18.1 <- index a8 base c00003 limit cfff90 PCI: 00:00.0 fc <- [0x00f2000000 - 0x00f20000ff] size 0x00000100 gran 0x08 prefmem PCI: 00:00.2 44 <- [0x00fa500000 - 0x00fa503fff] size 0x00004000 gran 0x0e mem PCI: 00:02.0 1c <- [0x0000006fff - 0x0000006ffe] size 0x00000000 gran 0x0c bus 01 io PCI: 00:02.0 24 <- [0x00f20fffff - 0x00f20ffffe] size 0x00000000 gran 0x14 bus 01 prefmem PCI: 00:02.0 20 <- [0x00fa5fffff - 0x00fa5ffffe] size 0x00000000 gran 0x14 bus 01 mem PCI: 00:04.0 1c <- [0x0000001000 - 0x0000001fff] size 0x00001000 gran 0x0c bus 02 io PCI: 00:04.0 24 <- [0x00f20fffff - 0x00f20ffffe] size 0x00000000 gran 0x14 bus 02 prefmem PCI: 00:04.0 20 <- [0x00fa100000 - 0x00fa1fffff] size 0x00100000 gran 0x14 bus 02 mem PCI: 00:04.0 assign_resources, bus 2 link: 0 PCI: 02:00.0 10 <- [0x0000001000 - 0x00000010ff] size 0x00000100 gran 0x08 io PCI: 02:00.0 14 <- [0x00fa1c0000 - 0x00fa1c3fff] size 0x00004000 gran 0x0e mem64 PCI: 02:00.0 1c <- [0x00fa180000 - 0x00fa1bffff] size 0x00040000 gran 0x12 mem64 PCI: 02:00.0 30 <- [0x00fa100000 - 0x00fa17ffff] size 0x00080000 gran 0x13 romem PCI: 00:04.0 assign_resources, bus 2 link: 0 PCI: 00:09.0 1c <- [0x0000002000 - 0x0000002fff] size 0x00001000 gran 0x0c bus 03 io PCI: 00:09.0 24 <- [0x00f20fffff - 0x00f20ffffe] size 0x00000000 gran 0x14 bus 03 prefmem PCI: 00:09.0 20 <- [0x00fa200000 - 0x00fa2fffff] size 0x00100000 gran 0x14 bus 03 mem PCI: 00:09.0 assign_resources, bus 3 link: 0 PCI: 03:00.0 10 <- [0x00fa200000 - 0x00fa21ffff] size 0x00020000 gran 0x11 mem PCI: 03:00.0 18 <- [0x0000002000 - 0x000000201f] size 0x00000020 gran 0x05 io PCI: 03:00.0 1c <- [0x00fa220000 - 0x00fa223fff] size 0x00004000 gran 0x0e mem PCI: 00:09.0 assign_resources, bus 3 link: 0 PCI: 00:0a.0 1c <- [0x0000003000 - 0x0000003fff] size 0x00001000 gran 0x0c bus 04 io PCI: 00:0a.0 24 <- [0x00f20fffff - 0x00f20ffffe] size 0x00000000 gran 0x14 bus 04 prefmem PCI: 00:0a.0 20 <- [0x00fa300000 - 0x00fa3fffff] size 0x00100000 gran 0x14 bus 04 mem PCI: 00:0a.0 assign_resources, bus 4 link: 0 PCI: 04:00.0 10 <- [0x00fa300000 - 0x00fa31ffff] size 0x00020000 gran 0x11 mem PCI: 04:00.0 18 <- [0x0000003000 - 0x000000301f] size 0x00000020 gran 0x05 io PCI: 04:00.0 1c <- [0x00fa320000 - 0x00fa323fff] size 0x00004000 gran 0x0e mem PCI: 00:0a.0 assign_resources, bus 4 link: 0 PCI: 00:0b.0 1c <- [0x0000004000 - 0x0000004fff] size 0x00001000 gran 0x0c bus 05 io PCI: 00:0b.0 24 <- [0x00e8000000 - 0x00f1ffffff] size 0x0a000000 gran 0x14 bus 05 prefmem PCI: 00:0b.0 20 <- [0x00f8000000 - 0x00f90fffff] size 0x01100000 gran 0x14 bus 05 mem PCI: 00:0b.0 assign_resources, bus 5 link: 0 PCI: 05:00.0 10 <- [0x00f8000000 - 0x00f8ffffff] size 0x01000000 gran 0x18 mem PCI: 05:00.0 14 <- [0x00e8000000 - 0x00efffffff] size 0x08000000 gran 0x1b prefmem64 PCI: 05:00.0 1c <- [0x00f0000000 - 0x00f1ffffff] size 0x02000000 gran 0x19 prefmem64 PCI: 05:00.0 24 <- [0x0000004000 - 0x000000407f] size 0x00000080 gran 0x07 io PCI: 05:00.0 30 <- [0x00f9000000 - 0x00f907ffff] size 0x00080000 gran 0x13 romem PCI: 05:00.1 10 <- [0x00f9080000 - 0x00f9083fff] size 0x00004000 gran 0x0e mem PCI: 00:0b.0 assign_resources, bus 5 link: 0 PCI: 00:0c.0 1c <- [0x0000006fff - 0x0000006ffe] size 0x00000000 gran 0x0c bus 06 io PCI: 00:0c.0 24 <- [0x00f20fffff - 0x00f20ffffe] size 0x00000000 gran 0x14 bus 06 prefmem PCI: 00:0c.0 20 <- [0x00fa5fffff - 0x00fa5ffffe] size 0x00000000 gran 0x14 bus 06 mem PCI: 00:0d.0 1c <- [0x0000006fff - 0x0000006ffe] size 0x00000000 gran 0x0c bus 07 io PCI: 00:0d.0 24 <- [0x00f20fffff - 0x00f20ffffe] size 0x00000000 gran 0x14 bus 07 prefmem PCI: 00:0d.0 20 <- [0x00fa400000 - 0x00fa4fffff] size 0x00100000 gran 0x14 bus 07 mem PCI: 00:0d.0 assign_resources, bus 7 link: 0 PCI: 07:00.0 10 <- [0x00fa400000 - 0x00fa400fff] size 0x00001000 gran 0x0c mem64 PCI: 00:0d.0 assign_resources, bus 7 link: 0 PCI: 00:11.0 10 <- [0x0000006020 - 0x0000006027] size 0x00000008 gran 0x03 io PCI: 00:11.0 14 <- [0x0000006040 - 0x0000006043] size 0x00000004 gran 0x02 io PCI: 00:11.0 18 <- [0x0000006028 - 0x000000602f] size 0x00000008 gran 0x03 io PCI: 00:11.0 1c <- [0x0000006044 - 0x0000006047] size 0x00000004 gran 0x02 io PCI: 00:11.0 20 <- [0x0000006000 - 0x000000600f] size 0x00000010 gran 0x04 io PCI: 00:11.0 24 <- [0x00fa50d000 - 0x00fa50d3ff] size 0x00000400 gran 0x0a mem PCI: 00:12.0 10 <- [0x00fa508000 - 0x00fa508fff] size 0x00001000 gran 0x0c mem PCI: 00:12.1 10 <- [0x00fa509000 - 0x00fa509fff] size 0x00001000 gran 0x0c mem PCI: 00:12.2 10 <- [0x00fa50e000 - 0x00fa50e0ff] size 0x00000100 gran 0x08 mem PCI: 00:13.0 10 <- [0x00fa50a000 - 0x00fa50afff] size 0x00001000 gran 0x0c mem PCI: 00:13.1 10 <- [0x00fa50b000 - 0x00fa50bfff] size 0x00001000 gran 0x0c mem PCI: 00:13.2 10 <- [0x00fa50f000 - 0x00fa50f0ff] size 0x00000100 gran 0x08 mem PCI: 00:14.0 assign_resources, bus 1 link: 0 PCI: 00:14.0 assign_resources, bus 1 link: 0 PCI: 00:14.1 10 <- [0x0000006030 - 0x0000006037] size 0x00000008 gran 0x03 io PCI: 00:14.1 14 <- [0x0000006048 - 0x000000604b] size 0x00000004 gran 0x02 io PCI: 00:14.1 18 <- [0x0000006038 - 0x000000603f] size 0x00000008 gran 0x03 io PCI: 00:14.1 1c <- [0x000000604c - 0x000000604f] size 0x00000004 gran 0x02 io PCI: 00:14.1 20 <- [0x0000006010 - 0x000000601f] size 0x00000010 gran 0x04 io PCI: 00:14.2 10 <- [0x00fa504000 - 0x00fa507fff] size 0x00004000 gran 0x0e mem64 PCI: 00:14.3 a0 <- [0x00fa510000 - 0x00fa510000] size 0x00000001 gran 0x00 mem PCI: 00:14.3 assign_resources, bus 0 link: 0 PNP: 002e.2 60 <- [0x00000003f8 - 0x00000003ff] size 0x00000008 gran 0x03 io PNP: 002e.2 70 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 irq PNP: 002e.3 60 <- [0x00000002f8 - 0x00000002ff] size 0x00000008 gran 0x03 io PNP: 002e.3 70 <- [0x0000000003 - 0x0000000003] size 0x00000001 gran 0x00 irq PNP: 002e.5 60 <- [0x0000000060 - 0x0000000060] size 0x00000001 gran 0x00 io PNP: 002e.5 62 <- [0x0000000064 - 0x0000000064] size 0x00000001 gran 0x00 io PNP: 002e.5 70 <- [0x0000000001 - 0x0000000001] size 0x00000001 gran 0x00 irq PNP: 002e.5 72 <- [0x000000000c - 0x000000000c] size 0x00000001 gran 0x00 irq PNP: 002e.b 60 <- [0x0000000290 - 0x0000000291] size 0x00000002 gran 0x01 io ERROR: PNP: 002e.b 70 irq size: 0x0000000001 not assigned PCI: 00:14.3 assign_resources, bus 0 link: 0 PCI: 00:14.4 1c <- [0x0000005000 - 0x0000005fff] size 0x00001000 gran 0x0c bus 08 io PCI: 00:14.4 24 <- [0x00f20fffff - 0x00f20ffffe] size 0x00000000 gran 0x14 bus 08 prefmem PCI: 00:14.4 20 <- [0x00f9800000 - 0x00fa0fffff] size 0x00900000 gran 0x14 bus 08 mem PCI: 00:14.4 assign_resources, bus 8 link: 0 PCI: 08:01.0 10 <- [0x00f9800000 - 0x00f9ffffff] size 0x00800000 gran 0x17 mem PCI: 08:01.0 14 <- [0x00fa000000 - 0x00fa01ffff] size 0x00020000 gran 0x11 mem PCI: 08:01.0 18 <- [0x0000005000 - 0x000000507f] size 0x00000080 gran 0x07 io PCI: 08:02.0 10 <- [0x00fa020000 - 0x00fa020fff] size 0x00001000 gran 0x0c mem PCI: 00:14.4 assign_resources, bus 8 link: 0 PCI: 00:14.5 10 <- [0x00fa50c000 - 0x00fa50cfff] size 0x00001000 gran 0x0c mem PCI: 00:18.0 assign_resources, bus 0 link: 1 PCI: 00:18.3 94 <- [0x00f4000000 - 0x00f7ffffff] size 0x04000000 gran 0x1a mem <gart> PCI: 00:19.3 94 <- [0x00f4000000 - 0x00f7ffffff] size 0x04000000 gran 0x1a mem <gart> PCI: 00:1a.3 94 <- [0x00f4000000 - 0x00f7ffffff] size 0x04000000 gran 0x1a mem <gart> PCI: 00:1b.3 94 <- [0x00f4000000 - 0x00f7ffffff] size 0x04000000 gran 0x1a mem <gart> DOMAIN: 0000 assign_resources, bus 0 link: 0 Root Device assign_resources, bus 0 link: 0 Done setting resources. Show resources in subtree (Root Device)...After assigning values. Root Device child on link 0 CPU_CLUSTER: 0 CPU_CLUSTER: 0 child on link 0 APIC: 00 APIC: 00 APIC: 01 APIC: 02 APIC: 03 APIC: 04 APIC: 05 APIC: 06 APIC: 07 APIC: 08 APIC: 09 APIC: 0a APIC: 0b APIC: 20 APIC: 21 APIC: 22 APIC: 23 APIC: 24 APIC: 25 APIC: 26 APIC: 27 APIC: 28 APIC: 29 APIC: 2a APIC: 2b DOMAIN: 0000 child on link 0 PCI: 00:18.0 DOMAIN: 0000 resource base 1000 size 6000 align 12 gran 0 limit ffff flags 40040100 index 10000000 DOMAIN: 0000 resource base e8000000 size 12600000 align 27 gran 0 limit feafffff flags 40040200 index 10000100 DOMAIN: 0000 resource base c0000000 size 10000000 align 28 gran 28 limit ffffffffffffffff flags f0000200 index c0010058 DOMAIN: 0000 resource base 0 size c0000000 align 0 gran 0 limit 0 flags e0004200 index 7 DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 10 DOMAIN: 0000 resource base c0000 size bff40000 align 0 gran 0 limit 0 flags e0004200 index 20 DOMAIN: 0000 resource base 100000000 size 140000000 align 0 gran 0 limit 0 flags e0004200 index 30 DOMAIN: 0000 resource base 240000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 41 DOMAIN: 0000 resource base 440000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 52 DOMAIN: 0000 resource base 640000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 63 PCI: 00:18.0 PCI: 00:18.0 resource base e8000000 size a100000 align 27 gran 20 limit f20fffff flags 60081200 index 110b0 PCI: 00:18.0 resource base f8000000 size 2600000 align 24 gran 20 limit fa5fffff flags 60080200 index 110b8 PCI: 00:18.0 resource base 1000 size 6000 align 12 gran 12 limit 6fff flags 60080100 index 110d8 PCI: 00:18.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags e0000200 index 111b8 PCI: 00:00.0 PCI: 00:00.0 resource base f2000000 size 100 align 12 gran 8 limit f20000ff flags 60001200 index fc PCI: 00:00.1 PCI: 00:00.2 PCI: 00:00.2 resource base fa500000 size 4000 align 14 gran 14 limit fa503fff flags 70000200 index 44 PCI: 00:02.0 PCI: 00:02.0 resource base 6fff size 0 align 12 gran 12 limit 6fff flags 60080102 index 1c PCI: 00:02.0 resource base f20fffff size 0 align 20 gran 20 limit f20fffff flags 60081202 index 24 PCI: 00:02.0 resource base fa5fffff size 0 align 20 gran 20 limit fa5fffff flags 60080202 index 20 PCI: 00:03.0 PCI: 00:04.0 child on link 0 PCI: 02:00.0 PCI: 00:04.0 resource base 1000 size 1000 align 12 gran 12 limit 1fff flags 60080102 index 1c PCI: 00:04.0 resource base f20fffff size 0 align 20 gran 20 limit f20fffff flags 60081202 index 24 PCI: 00:04.0 resource base fa100000 size 100000 align 20 gran 20 limit fa1fffff flags 60080202 index 20 PCI: 02:00.0 PCI: 02:00.0 resource base 1000 size 100 align 8 gran 8 limit 10ff flags 60000100 index 10 PCI: 02:00.0 resource base fa1c0000 size 4000 align 14 gran 14 limit fa1c3fff flags 60000201 index 14 PCI: 02:00.0 resource base fa180000 size 40000 align 18 gran 18 limit fa1bffff flags 60000201 index 1c PCI: 02:00.0 resource base fa100000 size 80000 align 19 gran 19 limit fa17ffff flags 60002200 index 30 PCI: 00:05.0 PCI: 00:06.0 PCI: 00:07.0 PCI: 00:08.0 PCI: 00:09.0 child on link 0 PCI: 03:00.0 PCI: 00:09.0 resource base 2000 size 1000 align 12 gran 12 limit 2fff flags 60080102 index 1c PCI: 00:09.0 resource base f20fffff size 0 align 20 gran 20 limit f20fffff flags 60081202 index 24 PCI: 00:09.0 resource base fa200000 size 100000 align 20 gran 20 limit fa2fffff flags 60080202 index 20 PCI: 03:00.0 PCI: 03:00.0 resource base fa200000 size 20000 align 17 gran 17 limit fa21ffff flags 60000200 index 10 PCI: 03:00.0 resource base 2000 size 20 align 5 gran 5 limit 201f flags 60000100 index 18 PCI: 03:00.0 resource base fa220000 size 4000 align 14 gran 14 limit fa223fff flags 60000200 index 1c PCI: 00:0a.0 child on link 0 PCI: 04:00.0 PCI: 00:0a.0 resource base 3000 size 1000 align 12 gran 12 limit 3fff flags 60080102 index 1c PCI: 00:0a.0 resource base f20fffff size 0 align 20 gran 20 limit f20fffff flags 60081202 index 24 PCI: 00:0a.0 resource base fa300000 size 100000 align 20 gran 20 limit fa3fffff flags 60080202 index 20 PCI: 04:00.0 PCI: 04:00.0 resource base fa300000 size 20000 align 17 gran 17 limit fa31ffff flags 60000200 index 10 PCI: 04:00.0 resource base 3000 size 20 align 5 gran 5 limit 301f flags 60000100 index 18 PCI: 04:00.0 resource base fa320000 size 4000 align 14 gran 14 limit fa323fff flags 60000200 index 1c PCI: 00:0b.0 child on link 0 PCI: 05:00.0 PCI: 00:0b.0 resource base 4000 size 1000 align 12 gran 12 limit 4fff flags 60080102 index 1c PCI: 00:0b.0 resource base e8000000 size a000000 align 27 gran 20 limit f1ffffff flags 60081202 index 24 PCI: 00:0b.0 resource base f8000000 size 1100000 align 24 gran 20 limit f90fffff flags 60080202 index 20 PCI: 05:00.0 PCI: 05:00.0 resource base f8000000 size 1000000 align 24 gran 24 limit f8ffffff flags 60000200 index 10 PCI: 05:00.0 resource base e8000000 size 8000000 align 27 gran 27 limit efffffff flags 60001201 index 14 PCI: 05:00.0 resource base f0000000 size 2000000 align 25 gran 25 limit f1ffffff flags 60001201 index 1c PCI: 05:00.0 resource base 4000 size 80 align 7 gran 7 limit 407f flags 60000100 index 24 PCI: 05:00.0 resource base f9000000 size 80000 align 19 gran 19 limit f907ffff flags 60002200 index 30 PCI: 05:00.1 PCI: 05:00.1 resource base f9080000 size 4000 align 14 gran 14 limit f9083fff flags 60000200 index 10 PCI: 00:0c.0 PCI: 00:0c.0 resource base 6fff size 0 align 12 gran 12 limit 6fff flags 60080102 index 1c PCI: 00:0c.0 resource base f20fffff size 0 align 20 gran 20 limit f20fffff flags 60081202 index 24 PCI: 00:0c.0 resource base fa5fffff size 0 align 20 gran 20 limit fa5fffff flags 60080202 index 20 PCI: 00:0d.0 child on link 0 PCI: 07:00.0 PCI: 00:0d.0 resource base 6fff size 0 align 12 gran 12 limit 6fff flags 60080102 index 1c PCI: 00:0d.0 resource base f20fffff size 0 align 20 gran 20 limit f20fffff flags 60081202 index 24 PCI: 00:0d.0 resource base fa400000 size 100000 align 20 gran 20 limit fa4fffff flags 60080202 index 20 PCI: 07:00.0 PCI: 07:00.0 resource base fa400000 size 1000 align 12 gran 12 limit fa400fff flags 60000201 index 10 PCI: 00:11.0 PCI: 00:11.0 resource base 6020 size 8 align 3 gran 3 limit 6027 flags 60000100 index 10 PCI: 00:11.0 resource base 6040 size 4 align 2 gran 2 limit 6043 flags 60000100 index 14 PCI: 00:11.0 resource base 6028 size 8 align 3 gran 3 limit 602f flags 60000100 index 18 PCI: 00:11.0 resource base 6044 size 4 align 2 gran 2 limit 6047 flags 60000100 index 1c PCI: 00:11.0 resource base 6000 size 10 align 4 gran 4 limit 600f flags 60000100 index 20 PCI: 00:11.0 resource base fa50d000 size 400 align 12 gran 10 limit fa50d3ff flags 60000200 index 24 PCI: 00:12.0 PCI: 00:12.0 resource base fa508000 size 1000 align 12 gran 12 limit fa508fff flags 60000200 index 10 PCI: 00:12.1 PCI: 00:12.1 resource base fa509000 size 1000 align 12 gran 12 limit fa509fff flags 60000200 index 10 PCI: 00:12.2 PCI: 00:12.2 resource base fa50e000 size 100 align 12 gran 8 limit fa50e0ff flags 60000200 index 10 PCI: 00:13.0 PCI: 00:13.0 resource base fa50a000 size 1000 align 12 gran 12 limit fa50afff flags 60000200 index 10 PCI: 00:13.1 PCI: 00:13.1 resource base fa50b000 size 1000 align 12 gran 12 limit fa50bfff flags 60000200 index 10 PCI: 00:13.2 PCI: 00:13.2 resource base fa50f000 size 100 align 12 gran 8 limit fa50f0ff flags 60000200 index 10 PCI: 00:14.0 child on link 0 I2C: 01:50 PCI: 00:14.0 resource base fec00000 size 1000 align 8 gran 8 limit ffffffff flags d0000200 index 74 PCI: 00:14.0 resource base feb00000 size 1000 align 8 gran 8 limit ffffffff flags d0000200 index 9c PCI: 00:14.0 resource base fed00000 size 400 align 8 gran 8 limit ffffffff flags d0000200 index b4 PCI: 00:14.0 resource base b00 size 10 align 8 gran 8 limit ffff flags d0000100 index 90 PCI: 00:14.0 resource base b20 size 10 align 8 gran 8 limit ffff flags d0000100 index 58 I2C: 01:50 I2C: 01:51 I2C: 01:52 I2C: 01:53 I2C: 01:54 I2C: 01:55 I2C: 01:56 I2C: 01:57 I2C: 01:2f PCI: 00:14.1 PCI: 00:14.1 resource base 6030 size 8 align 3 gran 3 limit 6037 flags 60000100 index 10 PCI: 00:14.1 resource base 6048 size 4 align 2 gran 2 limit 604b flags 60000100 index 14 PCI: 00:14.1 resource base 6038 size 8 align 3 gran 3 limit 603f flags 60000100 index 18 PCI: 00:14.1 resource base 604c size 4 align 2 gran 2 limit 604f flags 60000100 index 1c PCI: 00:14.1 resource base 6010 size 10 align 4 gran 4 limit 601f flags 60000100 index 20 PCI: 00:14.2 PCI: 00:14.2 resource base fa504000 size 4000 align 14 gran 14 limit fa507fff flags 60000201 index 10 PCI: 00:14.3 child on link 0 PNP: 002e.0 PCI: 00:14.3 resource base fa510000 size 1 align 12 gran 0 limit fa510000 flags 60000200 index a0 PCI: 00:14.3 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000 PCI: 00:14.3 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100 PCI: 00:14.3 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3 PNP: 002e.0 PNP: 002e.0 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 60 PNP: 002e.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 002e.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 PNP: 002e.1 PNP: 002e.1 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 60 PNP: 002e.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 002e.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 PNP: 002e.2 PNP: 002e.2 resource base 3f8 size 8 align 3 gran 3 limit fff flags e0000100 index 60 PNP: 002e.2 resource base 4 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 PNP: 002e.3 PNP: 002e.3 resource base 2f8 size 8 align 3 gran 3 limit fff flags e0000100 index 60 PNP: 002e.3 resource base 3 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 PNP: 002e.5 PNP: 002e.5 resource base 60 size 1 align 0 gran 0 limit ffffffff flags e0000100 index 60 PNP: 002e.5 resource base 64 size 1 align 0 gran 0 limit ffffffff flags e0000100 index 62 PNP: 002e.5 resource base 1 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 PNP: 002e.5 resource base c size 1 align 0 gran 0 limit 0 flags e0000400 index 72 PNP: 002e.106 PNP: 002e.106 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 62 PNP: 002e.107 PNP: 002e.207 PNP: 002e.307 PNP: 002e.407 PNP: 002e.8 PNP: 002e.108 PNP: 002e.9 PNP: 002e.109 PNP: 002e.209 PNP: 002e.309 PNP: 002e.a PNP: 002e.b PNP: 002e.b resource base 290 size 2 align 1 gran 1 limit fff flags e0000100 index 60 PNP: 002e.b resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 002e.c PNP: 002e.d PNP: 002e.f PCI: 00:14.4 child on link 0 PCI: 08:01.0 PCI: 00:14.4 resource base 5000 size 1000 align 12 gran 12 limit 5fff flags 60080102 index 1c PCI: 00:14.4 resource base f20fffff size 0 align 20 gran 20 limit f20fffff flags 60081202 index 24 PCI: 00:14.4 resource base f9800000 size 900000 align 23 gran 20 limit fa0fffff flags 60080202 index 20 PCI: 08:01.0 PCI: 08:01.0 resource base f9800000 size 800000 align 23 gran 23 limit f9ffffff flags 60000200 index 10 PCI: 08:01.0 resource base fa000000 size 20000 align 17 gran 17 limit fa01ffff flags 60000200 index 14 PCI: 08:01.0 resource base 5000 size 80 align 7 gran 7 limit 507f flags 60000100 index 18 PCI: 08:01.0 resource base a0000 size 1fc00 align 0 gran 0 limit 0 flags f0000200 index 3 PCI: 08:02.0 PCI: 08:02.0 resource base fa020000 size 1000 align 12 gran 12 limit fa020fff flags 60000200 index 10 PCI: 08:03.0 PCI: 00:14.5 PCI: 00:14.5 resource base fa50c000 size 1000 align 12 gran 12 limit fa50cfff flags 60000200 index 10 PCI: 00:18.1 PCI: 00:18.2 PCI: 00:18.3 PCI: 00:18.3 resource base f4000000 size 4000000 align 26 gran 26 limit f7ffffff flags 60000200 index 94 PCI: 00:18.4 PCI: 00:18.5 PCI: 00:19.0 PCI: 00:19.1 PCI: 00:19.2 PCI: 00:19.3 PCI: 00:19.4 PCI: 00:19.5 PCI: 00:1a.0 PCI: 00:1a.1 PCI: 00:1a.2 PCI: 00:1a.3 PCI: 00:1a.4 PCI: 00:1a.5 PCI: 00:1b.0 PCI: 00:1b.1 PCI: 00:1b.2 PCI: 00:1b.3 PCI: 00:1b.4 PCI: 00:1b.5 Done allocating resources. BS: BS_DEV_RESOURCES times (us): entry 0 run 3015 exit 0 Enabling resources... PCI: 00:18.0 cmd <- 00 PCI: 00:18.1 subsystem <- 1043/8163 PCI: 00:18.1 cmd <- 00 PCI: 00:18.2 subsystem <- 1043/8163 PCI: 00:18.2 cmd <- 00 PCI: 00:18.3 cmd <- 00 PCI: 00:18.4 cmd <- 00 PCI: 00:18.5 cmd <- 00 PCI: 00:19.0 cmd <- 00 PCI: 00:19.1 subsystem <- 1043/8163 PCI: 00:19.1 cmd <- 00 PCI: 00:19.2 subsystem <- 1043/8163 PCI: 00:19.2 cmd <- 00 PCI: 00:19.3 cmd <- 00 PCI: 00:19.4 cmd <- 00 PCI: 00:19.5 cmd <- 00 PCI: 00:1a.0 cmd <- 00 PCI: 00:1a.1 subsystem <- 1043/8163 PCI: 00:1a.1 cmd <- 00 PCI: 00:1a.2 subsystem <- 1043/8163 PCI: 00:1a.2 cmd <- 00 PCI: 00:1a.3 cmd <- 00 PCI: 00:1a.4 cmd <- 00 PCI: 00:1a.5 cmd <- 00 PCI: 00:1b.0 cmd <- 00 PCI: 00:1b.1 subsystem <- 1043/8163 PCI: 00:1b.1 cmd <- 00 PCI: 00:1b.2 subsystem <- 1043/8163 PCI: 00:1b.2 cmd <- 00 PCI: 00:1b.3 cmd <- 00 PCI: 00:1b.4 cmd <- 00 PCI: 00:1b.5 cmd <- 00 PCI: 00:00.0 subsystem <- 1043/8163 PCI: 00:00.0 cmd <- 02 Initializing IOMMU PCI: 00:02.0 bridge ctrl <- 0003 PCI: 00:02.0 cmd <- 00 PCI: 00:04.0 bridge ctrl <- 0003 PCI: 00:04.0 cmd <- 07 PCI: 00:09.0 bridge ctrl <- 0003 PCI: 00:09.0 cmd <- 07 PCI: 00:0a.0 bridge ctrl <- 0003 PCI: 00:0a.0 cmd <- 07 PCI: 00:0b.0 bridge ctrl <- 000b PCI: 00:0b.0 cmd <- 07 PCI: 00:0c.0 bridge ctrl <- 0003 PCI: 00:0c.0 cmd <- 00 PCI: 00:0d.0 bridge ctrl <- 0003 PCI: 00:0d.0 cmd <- 06 PCI: 00:11.0 subsystem <- 1043/8163 PCI: 00:11.0 cmd <- 03 PCI: 00:12.0 subsystem <- 1043/8163 PCI: 00:12.0 cmd <- 02 PCI: 00:12.1 subsystem <- 1043/8163 PCI: 00:12.1 cmd <- 02 PCI: 00:12.2 subsystem <- 1043/8163 PCI: 00:12.2 cmd <- 02 PCI: 00:13.0 subsystem <- 1043/8163 PCI: 00:13.0 cmd <- 02 PCI: 00:13.1 subsystem <- 1043/8163 PCI: 00:13.1 cmd <- 02 PCI: 00:13.2 subsystem <- 1043/8163 PCI: 00:13.2 cmd <- 02 PCI: 00:14.0 subsystem <- 1043/8163 PCI: 00:14.0 cmd <- 403 PCI: 00:14.1 subsystem <- 1043/8163 PCI: 00:14.1 cmd <- 01 PCI: 00:14.2 subsystem <- 1043/8163 PCI: 00:14.2 cmd <- 02 PCI: 00:14.3 subsystem <- 1043/8163 PCI: 00:14.3 cmd <- 0f sb700 lpc decode:PNP: 002e.2, base=0x000003f8, end=0x000003ff sb700 lpc decode:PNP: 002e.3, base=0x000002f8, end=0x000002ff sb700 lpc decode:PNP: 002e.5, base=0x00000060, end=0x00000060 sb700 lpc decode:PNP: 002e.5, base=0x00000064, end=0x00000064 sb700 lpc decode:PNP: 002e.b, base=0x00000290, end=0x00000291 PCI: 00:14.4 bridge ctrl <- 0003 PCI: 00:14.4 cmd <- 07 PCI: 00:14.5 subsystem <- 1043/8163 PCI: 00:14.5 cmd <- 02 PCI: 02:00.0 cmd <- 03 PCI: 03:00.0 cmd <- 03 PCI: 04:00.0 cmd <- 03 PCI: 05:00.0 cmd <- 03 PCI: 05:00.1 cmd <- 02 PCI: 07:00.0 cmd <- 02 PCI: 08:01.0 cmd <- 03 PCI: 08:02.0 subsystem <- 1043/8163 PCI: 08:02.0 cmd <- 02 done. BS: BS_DEV_ENABLE times (us): entry 0 run 349 exit 0 Initializing devices... Root Device init ... Root Device init finished in 0 usecs CPU_CLUSTER: 0 init ... Enabling probe filter Enabling ATM mode start_eip=0x00001000, code_size=0x00000031 CPU1: stack_base 00150000, stack_end 00150ff8 Asserting INIT. Waiting for send to finish... +Deasserting INIT. Waiting for send to finish... +#startup loops: 1. Sending STARTUP #1 to 1. After apic_write. Initializing CPU #1 CPU: vendor AMD device 600f12 CPU: family 15, model 01, stepping 02 Startup point 1. Waiting for send to finish... +nodeid = 00, coreid = 01 Enabling cache After Startup. CPU2: stack_base 0014f000, stack_end 0014fff8 Asserting INIT. Waiting for send to finish... +Deasserting INIT. Waiting for send to finish... +#startup loops: 1. Sending STARTUP #1 to 2. After apic_write. Startup point 1. Waiting for send to finish... +After Startup. CPU3: stack_base 0014e000, stack_end 0014eff8 Asserting INIT. Waiting for send to finish... +Deasserting INIT. Waiting for send to finish... +#startup loops: 1. Sending STARTUP #1 to 3. After apic_write. Startup point 1. Waiting for send to finish... +After Startup. CPU4: stack_base 0014d000, stack_end 0014dff8 Asserting INIT. Waiting for send to finish... +Deasserting INIT. Waiting for send to finish... +#startup loops: 1. Sending STARTUP #1 to 4. After apic_write. Startup point 1. Waiting for send to finish... +After Startup. CPU5: stack_base 0014c000, stack_end 0014cff8 Asserting INIT. Waiting for send to finish... +Deasserting INIT. Waiting for send to finish... +#startup loops: 1. Sending STARTUP #1 to 5. After apic_write. Startup point 1. Waiting for send to finish... +After Startup. CPU6: stack_base 0014b000, stack_end 0014bff8 Asserting INIT. Waiting for send to finish... +Deasserting INIT. Waiting for send to finish... +#startup loops: 1. Sending STARTUP #1 to 6. After apic_write. Startup point 1. Waiting for send to finish... +After Startup. CPU7: stack_base 0014a000, stack_end 0014aff8 Asserting INIT. Waiting for send to finish... +Deasserting INIT. Waiting for send to finish... +#startup loops: 1. Sending STARTUP #1 to 7. After apic_write. Startup point 1. Waiting for send to finish... +After Startup. CPU8: stack_base 00149000, stack_end 00149ff8 Asserting INIT. Waiting for send to finish... +Deasserting INIT. Waiting for send to finish... +#startup loops: 1. Sending STARTUP #1 to 8. After apic_write. Startup point 1. Waiting for send to finish... +After Startup. CPU9: stack_base 00148000, stack_end 00148ff8 Asserting INIT. Waiting for send to finish... +Deasserting INIT. Waiting for send to finish... +#startup loops: 1. Sending STARTUP #1 to 9. After apic_write. Startup point 1. MTRR check Fixed MTRRs : Enabled Variable MTRRs: Waiting for send to finish... +After Startup. Enabled CPU10: stack_base 00147000, stack_end 00147ff8 MTRR check Fixed MTRRs : Asserting INIT. Enabled Variable MTRRs: Enabled Waiting for send to finish... +Deasserting INIT. Waiting for send to finish... +#startup loops: 1. Sending STARTUP #1 to 10. After apic_write. Startup point 1. Waiting for send to finish... +After Startup. CPU11: stack_base 00146000, stack_end 00146ff8 Asserting INIT. Waiting for send to finish... +Deasserting INIT. Waiting for send to finish... +#startup loops: 1. Sending STARTUP #1 to 11. After apic_write. Setting up local apic...Setting up local apic...Startup point 1. apic_id: 0x02 apic_id: 0x04 done. done. CPU model: AMD Opteron(TM) Processor 6238 CPU model: AMD Opteron(TM) Processor 6238 siblings = 11, siblings = 11, Waiting for send to finish... +Disabling SMM ASeg memory Disabling SMM ASeg memory MTRR check Fixed MTRRs : Enabled Variable MTRRs: After Startup. CPU #2 initialized Enabled CPU12: stack_base 00145000, stack_end 00145ff8 Asserting INIT. MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled Waiting for send to finish... +Deasserting INIT. Waiting for send to finish... +#startup loops: 1. Sending STARTUP #1 to 32. After apic_write. Startup point 1. Waiting for send to finish... +CPU #4 initialized After Startup. Setting up local apic...CPU13: stack_base 00144000, stack_end 00144ff8 apic_id: 0x05 done. CPU model: AMD Opteron(TM) Processor 6238 Asserting INIT. siblings = 11, Waiting for send to finish... +Disabling SMM ASeg memory CPU #5 initialized nabling cache Setting up local apic... MTRR check Fixed MTRRs : MTRR check apic_id: 0x03 Fixed MTRRs : Enabled Variable MTRRs: Enabled Deasserting INIT. done. Waiting for send to finish... +CPU: family 15, model 01, stepping 02 CPU model: AMD Opteron(TM) Processor 6238 siblings = 11, Disabling SMM ASeg memory #startup loops: 1. Sending STARTUP #1 to 33. After apic_write. CPU #3 initialized nodeid = 01, coreid = 03 Enabled Variable MTRRs: Enabled Startup point 1. Setting up local apic...Waiting for send to finish... + apic_id: 0x06 done. CPU model: AMD Opteron(TM) Processor 6238 siblings = 11, Disabling SMM ASeg memory CPU #6 initialized MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled After Startup. CPU14: stack_base 00143000, stack_end 00143ff8 Asserting INIT. Waiting for send to finish... +Deasserting INIT. Waiting for send to finish... +#startup loops: 1. Sending STARTUP #1 to 34. After apic_write. Startup point 1. Waiting for send to finish... +After Startup. CPU15: stack_base 00142000, stack_end 00142ff8 Asserting INIT. Waiting for send to finish... +Deasserting INIT. Waiting for send to finish... +Setting up local apic...Enabling cache apic_id: 0x08 done. CPU model: AMD Opteron(TM) Processor 6238 siblings = 11, Disabling SMM ASeg memory MTRR check CPU #8 initialized Fixed MTRRs : Enabled Variable MTRRs: Enabled #startup loops: 1. Sending STARTUP #1 to 35. After apic_write. Startup point 1. Setting up local apic...Waiting for send to finish... +After Startup. apic_id: 0x07 done. CPU16: stack_base 00141000, stack_end 00141ff8 Asserting INIT. CPU model: AMD Opteron(TM) Processor 6238 Waiting for send to finish... siblings = 11, +Deasserting INIT. Disabling SMM ASeg memory Waiting for send to finish... +CPU #7 initialized #startup loops: 1. Setting up local apic...Sending STARTUP #1 to 36. After apic_write. apic_id: 0x09 done. CPU model: AMD Opteron(TM) Processor 6238 siblings = 11, Disabling SMM ASeg memory CPU #9 initialized Startup point 1. Waiting for send to finish... +After Startup. CPU17: stack_base 00140000, stack_end 00140ff8 Asserting INIT. Waiting for send to finish... +Deasserting INIT. Waiting for send to finish... +#startup loops: 1. Sending STARTUP #1 to 37. After apic_write. Startup point 1. Waiting for send to finish... +After Startup. CPU18: stack_base 0013f000, stack_end 0013fff8 nodeid = 01, coreid = 05 Asserting INIT. MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled Waiting for send to finish... +Deasserting INIT. Waiting for send to finish... +#startup loops: 1. Sending STARTUP #1 to 38. After apic_write. Startup point 1. Waiting for send to finish... +Enabling cache Setting up local apic...After Startup. apic_id: 0x0a done. CPU19: stack_base 0013e000, stack_end 0013eff8 CPU model: AMD Opteron(TM) Processor 6238 Asserting INIT. Waiting for send to finish... +siblings = 11, Disabling SMM ASeg memory Deasserting INIT. Waiting for send to finish... MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled +#startup loops: 1. Sending STARTUP #1 to 39. After apic_write. Startup point 1. Setting up local apic...CPU #10 initialized Waiting for send to finish... apic_id: 0x0b done. MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled +After Startup. CPU20: stack_base 0013d000, stack_end 0013dff8 CPU model: AMD Opteron(TM) Processor 6238 Asserting INIT. siblings = 11, Waiting for send to finish... + MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled Disabling SMM ASeg memory Setting up local apic...CPU #11 initialized apic_id: 0x20 done. CPU model: AMD Opteron(TM) Processor 6238 siblings = 11, Disabling SMM ASeg memory CPU #12 initialized MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled Deasserting INIT. Waiting for send to finish... +#startup loops: 1. Sending STARTUP #1 to 40. After apic_write. Startup point 1. Setting up local apic...Waiting for send to finish... apic_id: 0x21 done. +After Startup. CPU model: AMD Opteron(TM) Processor 6238 CPU21: stack_base 0013c000, stack_end 0013cff8 siblings = 11, Enabling cache Asserting INIT. Setting up local apic...Disabling SMM ASeg memory Waiting for send to finish... apic_id: 0x22 done. CPU #13 initialized +Deasserting INIT. CPU model: AMD Opteron(TM) Processor 6238 Waiting for send to finish... +siblings = 11, #startup loops: 1. Disabling SMM ASeg memory Sending STARTUP #1 to 41. MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled After apic_write. CPU #14 initialized Setting up local apic...Startup point 1. Waiting for send to finish... + apic_id: 0x23 done. CPU model: AMD Opteron(TM) Processor 6238 After Startup. siblings = 11, CPU22: stack_base 0013b000, stack_end 0013bff8 MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled Disabling SMM ASeg memory CPU #15 initialized Asserting INIT. Waiting for send to finish... +Deasserting INIT. Waiting for send to finish... +#startup loops: 1. Sending STARTUP #1 to 42. After apic_write. Startup point 1. Waiting for send to finish... +After Startup. CPU23: stack_base 0013a000, stack_end 0013aff8 Asserting INIT. Waiting for send to finish... +Deasserting INIT. Waiting for send to finish... +#startup loops: 1. Sending STARTUP #1 to 43. After apic_write. Startup point 1. Waiting for send to finish... +After Startup. Initializing CPU #0 CPU: vendor AMD device 600f12 CPU: family 15, model 01, stepping 02 nodeid = 00, coreid = 00 Enabling cache Enabling cache Setting up local apic...nodeid = 03, coreid = 01 apic_id: 0x24 done. CPU model: AMD Opteron(TM) Processor 6238 Enabling cache siblings = 11, MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled Disabling SMM ASeg memory CPU #16 initialized MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled CPU ID 0x80000001: 600f12 CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB Setting up local apic...Setting up local apic... apic_id: 0x26 done. apic_id: 0x25 done. CPU model: AMD Opteron(TM) Processor 6238 CPU model: AMD Opteron(TM) Processor 6238 siblings = 11, Disabling SMM ASeg memory siblings = 11, CPU #18 initialized MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled Disabling SMM ASeg memory CPU #17 initialized odeid = 03, coreid = 03 104 bytes lost ---- Thanks for your help.

2 1

Re: [coreboot] Where is the first instrucion?
by ron minnich 09 Aug '16

09 Aug '16

I have not read this thread closely and maybe I'm telling you something you know. But I want to warn you about CD. I know it is named 'cache disabled' but that's not quite what it means. I'm trying and failing to find the original slide deck from the UNM grad student (and intel employee) who first implemented our cache as ram in 2005. His point to me was that CD doesn't *really* mean cache hardware is disabled, just that it changes cache hardware behavior such that refills from memory are disabled. If there are valid tags in the cache then loads that hit those tags will work. So the task for CAR on x86 is to create valid tags, then set CD. His point was the breakthrough for me on understanding CAR on x86. Ollie Lo and I had been stuck on this point for a while, we kept thinking we could not set CD and have CAR work; in fact, setting CD is part of ensuring CAR works. The Intel employee's point was "you have to read between the lines in section III". you can git grep DO.NOT.INVALIDATE for a few comments on this and it may help. Basically, in the classic car we got in 2005, the steps on x86 are: enable cache do references to set tags disable cache (really!) then cache as ram works. Things have changed on some CPUs since then and we now even have chipset-dependent x86 CAR code but I suspect the basic idea remains the same on x86. You may already know this, just wanted to make sure. ron

1 0

← Newer
1
...
5
6
7
8
9
10
11
...
14
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

coreboot August 2016