coreboot August 2016

coreboot@coreboot.org

53 participants
132 discussions

Re: [coreboot] Baytrail MMC ACPI mode
by Matt DeVillier 11 Aug '16

11 Aug '16

HI Alex, assuming you are using the 'baytrail_fsp' SoC, you might take a look at the 'baytrail' soc used by the Baytrail Google ChromeOS devices. All of them use the eMMC in ACPI mode, and the SoC code for doing so might need to be added to the baytrail_fsp SoC if not already present (or at least give you a starting point to investigate) cheers, Matt On Thu, Aug 11, 2016 at 2:00 AM, Zoran Stojsavljevic < zoran.stojsavljevic(a)gmail.com> wrote: > Hello/Privet Alex, > > I'll try to help you, since I am not too much familiar with the eMMC > drivers in Coreboot. I bet there are none, but there must be BCT support as > you outlined it: *"Enable PCI mode for SCC devices" > (PcdSccEnablePciMode)"*. > > I never tried to set eMMC on BayTrail on Coreboot (in fact, I never tried > BayTrail with Coreboot, but I did try others' companies Coreboot images on > once upon a time BayleyBay Fab.3 E3826 (dual Core) CRB). But I did try all > of (and more) what you are writing here with various INTEL and AMI BIOSes. > It is off topic. > > Here is what I did try on some other customized platform, using E3845 B3 > and D0 steppings, and AMI BIOS. This is how I did setup with South Bridge, > SCC controller: > > [image: Inline image 1] > > Indeed, I was able to install Linux on eMMC (it was eMMC 5.0 compliant, > 32GB size, paired with BYT-I as written above, which supports up to eMMC > 4.51), namely Fedora 21 (if I recall correctly), and it worked seamlessly. > > I admit, I never tried WIN, but I do know that there are special INTEL > drivers developed for embedded WIN (for WEC 7 and WEC 2013). I am not sure > if such amenities exist for WES 7 (indirectly for WIN 7), you should check > these yourself: http://www.intel.com/content/www/us/en/embedded/ > products/bay-trail/software-and-drivers.html > > Maybe you can find some WIN eMMC driver support on this site. At least I > hope. Hope dies last. ;-) > > Hope this helps/nadejus6 eto pomozet, > Zoran > > On Tue, Aug 9, 2016 at 11:10 AM, szr <iszr(a)yandex.ru> wrote: > >> Hello. >> >> I have the board with Intel Baytrail E3845 and eMMC card v4.41, use >> coreboot 4.4, seabios 1.9.1. In PCI mode eMMC work, I can install and boot >> Ubuntu. The problem in Windows 8/10, which see card as "removable" disk, >> and therefore, do not allow to install on it. >> >> Excuse me, I have the simple question. How switch the MMC controller to >> ACPI mode? If set "Enable PCI mode for SCC devices" (PcdSccEnablePciMode) = >> Disabled in BCT, a controller be lost in lspci, but system no detect a ACPI >> device (checked in Ubuntu). >> >> I would be grateful for any help. >> >> Thanks, >> Alex. >> >> -- >> coreboot mailing list: coreboot(a)coreboot.org >> https://www.coreboot.org/mailman/listinfo/coreboot >> > > > -- > coreboot mailing list: coreboot(a)coreboot.org > https://www.coreboot.org/mailman/listinfo/coreboot >

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Re: [coreboot] Measuring the bootblock and adding a verstage
by Zaolin 11 Aug '16

11 Aug '16

On 08/11/2016 05:33 PM, Trammell Hudson wrote: > On Thu, Aug 11, 2016 at 05:00:00PM +0200, Zaolin wrote: >> The whole TPM stack needs to be reworked until it can used for a >> measured boot. > Is it necessary to import the entire complexity of TSS for the measured > boot task of hashing the various components? Once the Linux payload > starts up it can implement the more complex parts, as long as the > bootblock (with appropriate WP# and BP bits set on the ROM) can setup > the root of trust and the romstage/ramstage/payload loading process can > maintain the chain. I am not talking about the whole TSS. Google implements only a small parts of it. Currently there are two tss in coreboot. I wanted refactor and merge them. In order to provide a trusted/measured boot we need measurement functions which are actually missing and tcpa acpi log for PCR information. Also a good documentation should be the way to go. If you want to help out feel free to work with me together on it. :) Best Regards

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Re: [coreboot] Measuring the bootblock and adding a verstage
by Zaolin 11 Aug '16

11 Aug '16

Hey Trammell, No not really. Take a look at following patches: https://review.coreboot.org/#/c/10542/ https://review.coreboot.org/#/c/14038/ https://review.coreboot.org/#/c/14009/ https://review.coreboot.org/#/c/14134/ https://review.coreboot.org/#/c/14137/ https://review.coreboot.org/#/c/14135/ The whole TPM stack needs to be reworked until it can used for a measured boot. Best Regards Philipp On 08/11/2016 04:49 PM, Trammell Hudson wrote: > I'd like to add a tlcl_measure() function to hash a region of code > and extend a PCR with the result. I see that the Chromebook systems use > a verstage that links in src/lib/tlcl.c and there are sha1 functions in > 3rdparty/chromeec/common/sha1.c, but neither of these are available from > the romstage on other boards. > > For testing I've modified my romstage to include lib/tlcl.c and copied > sha1.c into lib. This allows me to measure the bootblock and the romstage > from the romstage as soon as pch_enable_lpc() has been called, but it's > not clear to me how to enable verstage on other mainboards (like the > sandybridge in my x230). Is there a guide or more documentation somewhere? >

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Measuring the bootblock and adding a verstage
by Trammell Hudson 11 Aug '16

11 Aug '16

I'd like to add a tlcl_measure() function to hash a region of code and extend a PCR with the result. I see that the Chromebook systems use a verstage that links in src/lib/tlcl.c and there are sha1 functions in 3rdparty/chromeec/common/sha1.c, but neither of these are available from the romstage on other boards. For testing I've modified my romstage to include lib/tlcl.c and copied sha1.c into lib. This allows me to measure the bootblock and the romstage from the romstage as soon as pch_enable_lpc() has been called, but it's not clear to me how to enable verstage on other mainboards (like the sandybridge in my x230). Is there a guide or more documentation somewhere? -- Trammell

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Baytrail MMC ACPI mode
by szr 11 Aug '16

11 Aug '16

Hello. I have the board with Intel Baytrail E3845 and eMMC card v4.41, use coreboot 4.4, seabios 1.9.1. In PCI mode eMMC work, I can install and boot Ubuntu. The problem in Windows 8/10, which see card as "removable" disk, and therefore, do not allow to install on it. Excuse me, I have the simple question. How switch the MMC controller to ACPI mode? If set "Enable PCI mode for SCC devices" (PcdSccEnablePciMode) = Disabled in BCT, a controller be lost in lspci, but system no detect a ACPI device (checked in Ubuntu). I would be grateful for any help. Thanks, Alex.

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Re: [coreboot] FS2 for anyone who can use it
by ron minnich 10 Aug '16

10 Aug '16

no problem, send me your address off list ron On Wed, Aug 10, 2016 at 6:36 PM Gregg Levine <gregg.drwho8(a)gmail.com> wrote: > Hello! > Ron how hard would it be to ship the gadget to NYC? > ----- > Gregg C Levine gregg.drwho8(a)gmail.com > "This signature fought the Time Wars, time and again." > > > On Wed, Aug 10, 2016 at 5:01 PM, ron minnich <rminnich(a)gmail.com> wrote: > > oh, thanks, Marshall, for some reason I confused FS2 and HDT. > > > > darn. Well, if nobody wants this thing ... into the black hole with it. > > > > ron > > > > -- > > coreboot mailing list: coreboot(a)coreboot.org > > https://www.coreboot.org/mailman/listinfo/coreboot >

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Re: [coreboot] FS2 for anyone who can use it
by Gregg Levine 10 Aug '16

10 Aug '16

Hello! Ron how hard would it be to ship the gadget to NYC? ----- Gregg C Levine gregg.drwho8(a)gmail.com "This signature fought the Time Wars, time and again." On Wed, Aug 10, 2016 at 5:01 PM, ron minnich <rminnich(a)gmail.com> wrote: > oh, thanks, Marshall, for some reason I confused FS2 and HDT. > > darn. Well, if nobody wants this thing ... into the black hole with it. > > ron > > -- > coreboot mailing list: coreboot(a)coreboot.org > https://www.coreboot.org/mailman/listinfo/coreboot

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Re: [coreboot] FS2 for anyone who can use it
by ron minnich 10 Aug '16

10 Aug '16

oh, thanks, Marshall, for some reason I confused FS2 and HDT. darn. Well, if nobody wants this thing ... into the black hole with it. ron

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Re: [coreboot] FS2 for anyone who can use it
by Marshall Dawson 10 Aug '16

10 Aug '16

FS2s were for Geode GX and LX only. Support was dropped perhaps 10+ years ago, but if the original CD is there, you should have some capabilities. I don't recall how buggy that original release was. AMD received periodic software updates, but good luck finding anyone who knows where to look for them. For Opteron support, Ron you're probably thinking about the HDT. (The two aren't interchangeable, of course.) I'd assume HDT units can still be borrowed or purchased from AMD by certain customers. Thanks, Marshall > Thanks Nico that's it. It's a nice debugger for opterons. > > If somebody wants it let me know and I'll bring it to berlin. > > ron > > On Wed, Aug 10, 2016 at 3:08 AM Nico Huber <nico.huber(a)secunet.com> wrote: > > > On 10.08.2016 10:35, ron minnich wrote: > > > ah, no, those are not it. Sorry. I'll get you some pictures. > > Maybe [1] helps. It's my best FS2 shot for something coreboot related. > > > > Nico > > > > [1] http://web.archive.org/web/20080915062711/http://www.fs2.com/ > > > > > > > > ron > > > > > > > > > > > > On Wed, Aug 10, 2016 at 12:42 AM Zoran Stojsavljevic < > > > zoran.stojsavljevic(a)gmail.com> wrote: > > > > > >>> What's an FS2? > > >> > > >> http://www.notebookcheck.net/LG-FS2.7422.0.html > > >> > > http://www.notebookcheck.net/Intel-Pentium-Dual-Core- > Processor.14045.0.html > > >> > > >> Zoran > > >> > > >> On Tue, Aug 9, 2016 at 3:30 PM, Jonathan Neusch?fer < > > j.neuschaefer(a)gmx.net > > >>> wrote: > > >> > > >>> On Sat, Aug 06, 2016 at 10:39:48PM +0000, ron minnich wrote: > > >>>> I have an FS2 if someone can use it. I may have mentioned this > > before. I > > >>>> can bring it to berlin with me if you will be at the meeting. > > >>> > > >>> Hi Ron, > > >>> > > >>> What's an FS2? > > >>> > > >>> > > >>> Jonathan > > >>> > > > >

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ASUS KFSN4-DRE (K8) Automated Test Failure [master]
by Raptor Engineering Automated Coreboot Test Stand 10 Aug '16

10 Aug '16

The ASUS KFSN4-DRE (K8) fails verification for branch master as of commit a46ee4d34d6b7ce7d47882779c7fb36270ccbda1 The following tests failed: BOOT_FAILURE Commits since last successful test: a46ee4d elog: Ensure eventlog will always get initialized when configured in eec1c28 drivers/elog: provide return status for all operations 18fedb3 drivers/elog: clean up SMBIOS related code 367f2b9 drivers/elog: consolidate checks in elog_find_flash() 4884c5d google/gru: Fix rk3399-gru write protect <80 commits skipped> d1a0051 google/gale: Add more board ID variants 40d62f3 google/gru: Add code to support I2C TPM for Kevin 5e6771b google/gru: Add support for Gru rev1 47ca65a payloads/coreinfo: Set KCONFIG_CONFIG value 5fafc6a soc/intel/quark: Support access to CPU CR registers See attached log for details This message was automatically generated from Raptor Engineering's ASUS KFSN4-DRE (K8) test stand Want to test on your own equipment? Check out https://www.raptorengineering.com/content/REACTS/intro.html Raptor Engineering also offers coreboot consulting services! Please visit https://www.raptorengineering.com for more information Please contact Timothy Pearson at Raptor Engineering <tpearson(a)raptorengineering.com> regarding any issues stemming from this notification

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coreboot August 2016