Hi Patrick,
On 08.04.2016 09:57, Patrick Georgi via coreboot wrote:
> 2016-04-08 9:51 GMT+02:00 rajashaker Goud <rajashakergoudranga(a)gmail.com>:
>> I have build coreboot with release payload.
>
> [ stripped to list only the empty regions]
>> Name Offset Type Size
>> (empty) 0xd8380 null 48152
>> (empty) 0x105840 null 1880
>> (empty) 0x10e000 null 8088
>> (empty) 0x150000 null 311192
>> (empty) 0x1e8c00 null 58200
>> (empty) 0x1ff9c0 null 536
> That makes approx. 450K of free space in your image
>
>> but when i build debug am facing space issue:
>> E: Could not add [payloads/external/uefi/UEFIPAYLOAD.fd, 886346 bytes (865
>> KB)@0x0]; too big?
> This is indicates a 865K image. How is that supposed to fit?
you also stripped:
fallback/payload 0x1b140 payload 769955
I guess he means that a fresh build with a bigger (865KiB instead of
752KiB) payload fails.
Nico
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M. Sc. Nico Huber
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Hi Rajashaker,
On 08.04.2016 09:51, rajashaker Goud wrote:
> So in my case i need to adjust the offset coz after config i have empty
> space available.
> please help me in changing the offset.
> i dont have idea regarding which part of code need to change to adjust
> offset.
I don't know how to change the offsets. Some might not be chosen
arbitrarily at all. But maybe there is another simple option: Did you
already try to increase the size of your CBFS (CONFIG_CBFS_SIZE)? It
may be as large as the "bios" partition of your flash chip.
Hope that helps,
Nico
--
M. Sc. Nico Huber
Senior Berater SINA-Softwareentwicklung
Netzwerk- & Client-Sicherheit / Network & Client Security
Division Öffentliche Auftraggeber / Public Authorities
secunet Security Networks AG
Tel.: +49-201-5454-3635, Fax: +49-201-5454-1325
E-Mail: nico.huber(a)secunet.com
Mergenthalerallee 77, 65760 Eschborn, Deutschland
www.secunet.com
______________________________________________________________________
Sitz: Kronprinzenstraße 30, 45128 Essen, Deutschland
Amtsgericht Essen HRB 13615
Vorstand: Dr. Rainer Baumgart (Vors.), Thomas Pleines
Aufsichtsratsvorsitzender: Dr. Peter Zattler
______________________________________________________________________
2016-04-08 9:51 GMT+02:00 rajashaker Goud <rajashakergoudranga(a)gmail.com>:
> I have build coreboot with release payload.
[ stripped to list only the empty regions]
> Name Offset Type Size
> (empty) 0xd8380 null 48152
> (empty) 0x105840 null 1880
> (empty) 0x10e000 null 8088
> (empty) 0x150000 null 311192
> (empty) 0x1e8c00 null 58200
> (empty) 0x1ff9c0 null 536
That makes approx. 450K of free space in your image
> but when i build debug am facing space issue:
> E: Could not add [payloads/external/uefi/UEFIPAYLOAD.fd, 886346 bytes (865
> KB)@0x0]; too big?
This is indicates a 865K image. How is that supposed to fit?
Patrick
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Registergericht und -nummer: Hamburg, HRB 86891, Sitz der Gesellschaft: Hamburg
Geschäftsführer: Matthew Scott Sucherman, Paul Terence Manicle
Hi All,
I have build coreboot with release payload.
Name Offset Type Size
bootsplash.img 0x0 bootsplash 37443
cmos_layout.bin 0x9280 cmos_layout 1132
fspd.bin 0x9740 (unknown) 4608
fallback/ramstage 0xa980 stage 67423
fallback/payload 0x1b140 payload 769955
config 0xd7140 raw 4623
(empty) 0xd8380 null 48152
cpu_microcode_blob.bin 0xe3fc0 microcode 137232
(empty) 0x105840 null 1880
mrc.cache 0x105fc0 (unknown) 32768
(empty) 0x10e000 null 8088
uefi_nvs.bin 0x10ffc0 (unknown) 262144
(empty) 0x150000 null 311192
fsp.bin 0x19bfc0 (unknown) 314368
(empty) 0x1e8c00 null 58200
fallback/romstage 0x1f6f80 stage 35253
(empty) 0x1ff9c0 null 536
but when i build debug am facing space issue:
E: Could not add [payloads/external/uefi/UEFIPAYLOAD.fd, 886346 bytes (865
KB)@0x0]; too big?
E: Failed to add 'payloads/external/uefi/UEFIPAYLOAD.fd' into ROM image.
make: *** [build/coreboot.rom] Error 1
So in my case i need to adjust the offset coz after config i have empty
space available.
please help me in changing the offset.
i dont have idea regarding which part of code need to change to adjust
offset.
Thanks in advance.
--
Thanks,
Rajashaker Goud Ranga
Hi folks,
Paul and I came up with the idea of doing a coreboot community meeting
every 2 weeks. The plan for this meeting is to sync the development
state between us and provide some sort of better communication and
organization. Therefore we will provide an initial agenda which can
change and be improved by all.
The meeting will be announced two weeks before the next via coreboot ml
so that you have time to do your planning. The meeting room is provided
by discordapp (the next solution), you need to use chrome/chromium or
install a desktop app. The channel can be accessed via link:
https://discord.gg/0vhZlDE5b2njfGK7
Every meeting will be documented by a report. The report is published
after the meeting via a link the coreboot wiki.
More information can be found under the following link:
https://www.coreboot.org/Coreboot_community_meeting
The only rule in this meeting is to be kind to each other.
### So no flamewar, offence or individual criticism ! ###
2nd Coreboot Community Meeting
====================================================
Date: 18.04.2016
San Francisco time: Begin at 09.00 a.m.
Berlin time: Begin at 18.00 p.m.
Meeting time: Max. 1 hour.
Who is invited: Everyone who is or intends to
become developer !
Agenda:
-----------
1) Introduction
-> Everyone introduces themselves (Only for new developers).
Every developer gives a short overview what he did the last
two weeks and what he want to do the next two weeks.
(max. 5 min. per person, daily scrum like).
2) News
-> Developers with interesting news keep the other
up-to-date but no discussion.
3) Maintainer Orga
-> Issues
-> Requests
4) Project Orga
-> Gather topics which need to be discussed or improve
the project itself.
-> Find tasks and developer which a responsible for a task.
5) Admin Orga
-> Access requests
-> Questions
-> Issues
6) GSoC Orga
7) Other topics which are not on the agenda.
99) Developer Topics / Split Up / Have fun to discuss your idea
-> Gather developer topics which seem to be important and
interesting to solve.
-> Gather groups of developers who are interested in the same topic.
-> For deeper information exchange split up in different jitsi meet
channels and close meeting.
100) End
=====================================================
Best Regards
Zaolin
I have a toshiba chromebook 2 with a intel celeron, with oviously linux
installed and coreboot/seabios so is there a way to add a overclocking
feature or how can i add one myself, or is there a posibility of
overclocking in linux?
Thanks in advance Jean