This is a recently added warning (see
https://review.coreboot.org/13949) that tells you that you are trying
to use a payload which would overlap the parts of coreboot that are
loading it (risking random corruption errors and such). The fix is to
link your payload to a different base address which does not overlap
the POSTRAM_CBFS_CACHE region in the memlayout.ld of your
board/chipset.
Which board are you building for and which payload are you trying to use?
Hello,
While compiling coreboot, I get the following error - any ideas on how to
address this:
Performing operation on 'BOOTBLOCK' region...
W: Written area will abut bottom of target region: any unused space will
keep its current contents
Performing operation on 'COREBOOT' region...
Performing operation on 'COREBOOT' region...
CBFS fallback/romstage
Performing operation on 'COREBOOT' region...
CBFS fallback/ramstage
Performing operation on 'COREBOOT' region...
CBFS fallback/payload
Performing operation on 'COREBOOT' region...
CBFS config
Performing operation on 'COREBOOT' region...
CBFS revision
Performing operation on 'COREBOOT' region...
CBFS payload_config
Performing operation on 'COREBOOT' region...
CBFS payload_revision
Performing operation on 'COREBOOT' region...
Performing operation on 'COREBOOT' region...
ERROR: Ramstage region _postram_cbfs_cache overlapped by: fallback/payload
make: *** [check-ramstage-overlaps] Error 1
Thanks
Sid
Hi,
with the Richland-patches being available, did someone already try to run one of the "high-end" Richland APUs like the A10-6800k in the F2A85-M with Coreboot?
Cheers, Daniel
I recently worked with Kyosti to update the EHCI Debug cable.
You can find an updated version of the cable here, under examples/debugdev_full_duplex.
https://github.com/night199uk/fx2lib <https://github.com/night199uk/fx2lib>
There is a .PDF with a build spec based on the newer version of the FX2LP boards that are easily available from taobao or eBay. It should work with the old ones too. It is a slightly modified version of Kyosti’s original (excellent) spec that got me started.
The new cable/firmware complies with the 8-byte packet requirement of the EHCI Debug Device specification to avoid overrunning the EHCI Debug port buffers. Also in theory it should be faster (perhaps if you remove the 8-byte packetization) due to the use of GPIF streaming.
The EHCI Debug cable implements the CDC ACM spec - I didn’t modify that part at all, but in theory it should appear as a standard serial port under Windows. I’ve tested it with Linux and OS X and both support it natively through CDC ACM drivers and I believe a friend of mine tested it working as such.
Also EDK2 supports it for SourceLevelDebugPkg. That needs some minor patches as EDK2 hard-codes the USB endpoint numbers for Ajays - I may contribute back patches to read those from the descriptor at some point but it’s an easy modification to make manually.
Regards,
Chris.
> On 4 Apr 2016, at 13:00, Kyösti Mälkki <kyosti.malkki(a)gmail.com> wrote:
>
>
> ---------- Forwarded message ----------
> From: Zheng Bao <fishbaoz(a)hotmail.com <mailto:fishbaoz@hotmail.com>>
> Date: Fri, Mar 18, 2016 at 4:01 PM
> Subject: [coreboot] Is windows driver for EHCI DEBUG available.
> To: "coreboot(a)coreboot.org <mailto:coreboot@coreboot.org>" <coreboot(a)coreboot.org <mailto:coreboot@coreboot.org>>
>
>
> Hi, all,
> http://www.coreboot.org/DIY_EHCI_debug_dongle <https://www.coreboot.org/DIY_EHCI_debug_dongle>
> http://www.coreboot.org/EHCI_debug_dongle <https://www.coreboot.org/EHCI_debug_dongle>
> I want to build a EHCI debug dongle based on above links.
> I am wondering if the windows driver of the dongle is available.
> I google it but can not find it. I assume it is a generic driver.
> Who knows about that?
>
> Thanks.
>
> Zheng
>
> --
> coreboot mailing list: coreboot(a)coreboot.org <mailto:coreboot@coreboot.org>
> https://www.coreboot.org/mailman/listinfo/coreboot <https://www.coreboot.org/mailman/listinfo/coreboot>
>
DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866 unit
7-7-7 9-9-9 11-11-11 13-13-13
nRFC-1 Gb 59 74 88 103 nCK
nRFC- 2 Gb 86 107 128 150 nCK
nRFC- 4 Gb 160 200 240 281 nCK
nRFC- 8 Gb 187 234 280 328 nCK
Hi, All,
Above text is extracted from the spec of a DDR3 chip.
I am trying to decide the Trfc.
What does "-x Gb" mean? How do I know which row in the table I should use?
Thanks.
Zheng
Hi,
Please find the latest report on new defect(s) introduced to coreboot found with Coverity Scan.
2 new defect(s) introduced to coreboot found with Coverity Scan.
334 defect(s), reported by Coverity Scan earlier, were marked fixed in the recent build analyzed by Coverity Scan.
New defect(s) Reported-by: Coverity Scan
Showing 2 of 2 defect(s)
** CID 1353736: Control flow issues (NO_EFFECT)
/3rdparty/arm-trusted-firmware/plat/mediatek/mt8173/plat_pm.c: 386 in plat_affinst_suspend()
________________________________________________________________________________________________________
*** CID 1353736: Control flow issues (NO_EFFECT)
/3rdparty/arm-trusted-firmware/plat/mediatek/mt8173/plat_pm.c: 386 in plat_affinst_suspend()
380
381 mmio_write_32(rv, sec_entrypoint);
382
383 if (afflvl < MPIDR_AFFLVL2)
384 spm_mcdi_prepare_for_off_state(mpidr, afflvl);
385
>>> CID 1353736: Control flow issues (NO_EFFECT)
>>> This greater-than-or-equal-to-zero comparison of an unsigned value is always true. "afflvl >= 0U".
386 if (afflvl >= MPIDR_AFFLVL0)
387 mt_platform_save_context(mpidr);
388
389 /* Perform the common cluster specific operations */
390 if (afflvl >= MPIDR_AFFLVL1) {
391 /* Disable coherency if this cluster is to be turned off */
** CID 1353737: Control flow issues (NO_EFFECT)
/3rdparty/arm-trusted-firmware/plat/mediatek/mt8173/plat_pm.c: 459 in plat_affinst_suspend_finish()
________________________________________________________________________________________________________
*** CID 1353737: Control flow issues (NO_EFFECT)
/3rdparty/arm-trusted-firmware/plat/mediatek/mt8173/plat_pm.c: 459 in plat_affinst_suspend_finish()
453 /* Perform the common cluster specific operations */
454 if (afflvl >= MPIDR_AFFLVL1) {
455 /* Enable coherency if this cluster was off */
456 plat_cci_enable();
457 }
458
>>> CID 1353737: Control flow issues (NO_EFFECT)
>>> This greater-than-or-equal-to-zero comparison of an unsigned value is always true. "afflvl >= 0U".
459 if (afflvl >= MPIDR_AFFLVL0)
460 mt_platform_restore_context(mpidr);
461
462 if (afflvl < MPIDR_AFFLVL2)
463 spm_mcdi_finish_for_on_state(mpidr, afflvl);
464
________________________________________________________________________________________________________
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