coreboot March 2016

coreboot@coreboot.org

43 participants
117 discussions

Re: [coreboot] Memtest86 SPD/DMI popups broken

by Ben Gardner

Yes, lets revert it. The popups work again after reverting commit 03e81e1 (https://review.coreboot.org/#/c/13900). The other one (https://review.coreboot.org/#/c/13901/) doesn't make a difference on my board. Probably because I have VGA. I suppose that one can stay. On Wed, Mar 9, 2016 at 1:57 PM, Martin Roth <gaumless(a)gmail.com> wrote: > Do you think we should revert those patches until we can get them fixed? > > On Wed, Mar 9, 2016 at 11:56 AM, Ben Gardner <gardner.ben(a)gmail.com> wrote: >> FYI - >> >> I just tried memtest86 with the popup patches that were added to coreboot. >> I'm seeing issues with clearing the background before drawing the SPD popup. >> >> When I hit "c", the "settings" popup shows on both serial and VGA >> properly. VGA has a black background and serial clears the area. >> >> When I select "display SPD data", it doesn't clear the background >> before drawing the data and doesn't restore what was under when the >> popup is lowered. >> >> Below is the output from the serial port when displaying the SPD data. >> View in a fixed width font. >> >> ----- >> Memtest86+ 5.01 coreboot 001| Intel(R) Atom(TM) CPU E3845 @ 1.91GHz >> CLK: 1917 MHz (X64 Mode) | Pass 0% >> L1 CSPD Data: Slot 095 MB/s | Test 50% ################### >> L2 Cache: 1024K 22030 MB/s | Test #2 [Address test, own address Parallel] >> L3 Cac92:13N0be03 04 19 02 02 03s11n01 0820a 001fe600 1965M of 4013M >> Memory69:78069M3c 69811M18s81 20t08r3c 3ca01r40s83 05 | Time: 0:00:01 >> ------00-00-00-00-00-00-00-00-00-84-00-00-00-00-00-00------------------------- >> Core#:00 00M00 00s00l00)00|00C00 00m00 00R0f:01102M00 (DDR3-833) - BCLK: 83 >> State:00 00 00 00 00 00 00 00 00 00 00 00 00 00s00C00 9-9-9-10 @ 64-bit Mode >> Cores:00100 00 00 00 00 00 00 00 00 00 00 00 00 00 000 Errors: 0 >> ------00-00 00 00 00 00 00 00 00 00 00 00 00 00-00-00------------------------- >> 00 00 00 00 00 80 2c 00 00 00 00 00 00 00 c4 b1 >> Memory34P4b 54 46 32 35 36 36 34 48 5a 2d 31 47 36 45 >> ------31-45 31 80 2c 00 00 00 00 00 00 00 00 00 00 00 >> - Sl00 00 00 00 00 00 00 00 00 00 00 00 00 00600ZffG6E1E >> - Sl57 50 4e 3a 33 34 32 35 36 20 52 45 56 3a641ZffG6E1E >> 32 30 34 38 20 4d 42 59 54 45 ff ff ff ff ff ff >> ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff >> ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff >> ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff >> >> >> >> Wabtec CPU-1900 >> (ESC)exit (c)configuration (SP)scroll_lock (CR)scroll_unlock >> ----- >> >> And what is shown after returning to the settings menu. >> >> ----- >> Memtest86+ 5.01 coreboot 001| Intel(R) Atom(TM) CPU E3845 @ 1.91GHz >> CLK: 1917 MHz (X64 Mode) | Pass 0% >> L1 CSPD Data: Slot 195 MB/s | Test 88% ################################## >> L2 CaNo valid DMI Memory Devices info founding inversions, 1s & 0s Parallel] >> L3 Cac92:13N0be03 04 19 02 02 03s11n01 0890a 006fe400 2048M of 4013M >> Memory69:78069M3c 69811M18s81 20t08r3c 3cf01f40f83 05 | Time: 0:05:38 >> ------00-00-00-00-00-00-00-00-00-84-00-00-00-00-00-00------------------------- >> Core#:00 00M00 00s00l00)00|00C00 00m00 00R0f:01102M00 (DDR3-833) - BCLK: 83 >> State:00 00 00s00C00 9-9-9-10 @ 64-bit Mode >> Cores:00100 Settings: 00 00 000 Errors: 0 >> ------00-00 00-00-00------------------------- >> 00 00 (1) Test Selection 00 c4 b1 >> Memory34P4b (2) Address Range 47 36 45 >> ------31-45 (3) Error Report Mode 00 00 00 >> - Sl00 00 (4) Core Selection 00600ZffG6E1E >> - Sl57 50 (5) Refresh Screen 3a641ZffG6E1E >> 32 30 (6) Display DMI Data ff ff ff >> ff ff (7) Display SPD Data ff ff ff >> ff ff ff ff ff >> ff ff (0) Continue ff ff ff >> >> >> >> Wabtec CPU-1900 >> (ESC)exit (c)configuration (SP)scroll_lock (CR)scroll_unlock >> ----- >> >> Not sure what is going on here. >> I don't have this issue without the popup patches. >> I'll look into it a bit more. >> >> Ben >> >> -- >> coreboot mailing list: coreboot(a)coreboot.org >> https://www.coreboot.org/mailman/listinfo/coreboot

5 years, 6 months

Re: [coreboot] Memtest86 SPD/DMI popups broken

by Martin Roth

Do you think we should revert those patches until we can get them fixed? On Wed, Mar 9, 2016 at 11:56 AM, Ben Gardner <gardner.ben(a)gmail.com> wrote: > FYI - > > I just tried memtest86 with the popup patches that were added to coreboot. > I'm seeing issues with clearing the background before drawing the SPD popup. > > When I hit "c", the "settings" popup shows on both serial and VGA > properly. VGA has a black background and serial clears the area. > > When I select "display SPD data", it doesn't clear the background > before drawing the data and doesn't restore what was under when the > popup is lowered. > > Below is the output from the serial port when displaying the SPD data. > View in a fixed width font. > > ----- > Memtest86+ 5.01 coreboot 001| Intel(R) Atom(TM) CPU E3845 @ 1.91GHz > CLK: 1917 MHz (X64 Mode) | Pass 0% > L1 CSPD Data: Slot 095 MB/s | Test 50% ################### > L2 Cache: 1024K 22030 MB/s | Test #2 [Address test, own address Parallel] > L3 Cac92:13N0be03 04 19 02 02 03s11n01 0820a 001fe600 1965M of 4013M > Memory69:78069M3c 69811M18s81 20t08r3c 3ca01r40s83 05 | Time: 0:00:01 > ------00-00-00-00-00-00-00-00-00-84-00-00-00-00-00-00------------------------- > Core#:00 00M00 00s00l00)00|00C00 00m00 00R0f:01102M00 (DDR3-833) - BCLK: 83 > State:00 00 00 00 00 00 00 00 00 00 00 00 00 00s00C00 9-9-9-10 @ 64-bit Mode > Cores:00100 00 00 00 00 00 00 00 00 00 00 00 00 00 000 Errors: 0 > ------00-00 00 00 00 00 00 00 00 00 00 00 00 00-00-00------------------------- > 00 00 00 00 00 80 2c 00 00 00 00 00 00 00 c4 b1 > Memory34P4b 54 46 32 35 36 36 34 48 5a 2d 31 47 36 45 > ------31-45 31 80 2c 00 00 00 00 00 00 00 00 00 00 00 > - Sl00 00 00 00 00 00 00 00 00 00 00 00 00 00600ZffG6E1E > - Sl57 50 4e 3a 33 34 32 35 36 20 52 45 56 3a641ZffG6E1E > 32 30 34 38 20 4d 42 59 54 45 ff ff ff ff ff ff > ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff > ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff > ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff > > > > Wabtec CPU-1900 > (ESC)exit (c)configuration (SP)scroll_lock (CR)scroll_unlock > ----- > > And what is shown after returning to the settings menu. > > ----- > Memtest86+ 5.01 coreboot 001| Intel(R) Atom(TM) CPU E3845 @ 1.91GHz > CLK: 1917 MHz (X64 Mode) | Pass 0% > L1 CSPD Data: Slot 195 MB/s | Test 88% ################################## > L2 CaNo valid DMI Memory Devices info founding inversions, 1s & 0s Parallel] > L3 Cac92:13N0be03 04 19 02 02 03s11n01 0890a 006fe400 2048M of 4013M > Memory69:78069M3c 69811M18s81 20t08r3c 3cf01f40f83 05 | Time: 0:05:38 > ------00-00-00-00-00-00-00-00-00-84-00-00-00-00-00-00------------------------- > Core#:00 00M00 00s00l00)00|00C00 00m00 00R0f:01102M00 (DDR3-833) - BCLK: 83 > State:00 00 00s00C00 9-9-9-10 @ 64-bit Mode > Cores:00100 Settings: 00 00 000 Errors: 0 > ------00-00 00-00-00------------------------- > 00 00 (1) Test Selection 00 c4 b1 > Memory34P4b (2) Address Range 47 36 45 > ------31-45 (3) Error Report Mode 00 00 00 > - Sl00 00 (4) Core Selection 00600ZffG6E1E > - Sl57 50 (5) Refresh Screen 3a641ZffG6E1E > 32 30 (6) Display DMI Data ff ff ff > ff ff (7) Display SPD Data ff ff ff > ff ff ff ff ff > ff ff (0) Continue ff ff ff > > > > Wabtec CPU-1900 > (ESC)exit (c)configuration (SP)scroll_lock (CR)scroll_unlock > ----- > > Not sure what is going on here. > I don't have this issue without the popup patches. > I'll look into it a bit more. > > Ben > > -- > coreboot mailing list: coreboot(a)coreboot.org > https://www.coreboot.org/mailman/listinfo/coreboot

5 years, 6 months

Memtest86 SPD/DMI popups broken

by Ben Gardner

FYI - I just tried memtest86 with the popup patches that were added to coreboot. I'm seeing issues with clearing the background before drawing the SPD popup. When I hit "c", the "settings" popup shows on both serial and VGA properly. VGA has a black background and serial clears the area. When I select "display SPD data", it doesn't clear the background before drawing the data and doesn't restore what was under when the popup is lowered. Below is the output from the serial port when displaying the SPD data. View in a fixed width font. ----- Memtest86+ 5.01 coreboot 001| Intel(R) Atom(TM) CPU E3845 @ 1.91GHz CLK: 1917 MHz (X64 Mode) | Pass 0% L1 CSPD Data: Slot 095 MB/s | Test 50% ################### L2 Cache: 1024K 22030 MB/s | Test #2 [Address test, own address Parallel] L3 Cac92:13N0be03 04 19 02 02 03s11n01 0820a 001fe600 1965M of 4013M Memory69:78069M3c 69811M18s81 20t08r3c 3ca01r40s83 05 | Time: 0:00:01 ------00-00-00-00-00-00-00-00-00-84-00-00-00-00-00-00------------------------- Core#:00 00M00 00s00l00)00|00C00 00m00 00R0f:01102M00 (DDR3-833) - BCLK: 83 State:00 00 00 00 00 00 00 00 00 00 00 00 00 00s00C00 9-9-9-10 @ 64-bit Mode Cores:00100 00 00 00 00 00 00 00 00 00 00 00 00 00 000 Errors: 0 ------00-00 00 00 00 00 00 00 00 00 00 00 00 00-00-00------------------------- 00 00 00 00 00 80 2c 00 00 00 00 00 00 00 c4 b1 Memory34P4b 54 46 32 35 36 36 34 48 5a 2d 31 47 36 45 ------31-45 31 80 2c 00 00 00 00 00 00 00 00 00 00 00 - Sl00 00 00 00 00 00 00 00 00 00 00 00 00 00600ZffG6E1E - Sl57 50 4e 3a 33 34 32 35 36 20 52 45 56 3a641ZffG6E1E 32 30 34 38 20 4d 42 59 54 45 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff Wabtec CPU-1900 (ESC)exit (c)configuration (SP)scroll_lock (CR)scroll_unlock ----- And what is shown after returning to the settings menu. ----- Memtest86+ 5.01 coreboot 001| Intel(R) Atom(TM) CPU E3845 @ 1.91GHz CLK: 1917 MHz (X64 Mode) | Pass 0% L1 CSPD Data: Slot 195 MB/s | Test 88% ################################## L2 CaNo valid DMI Memory Devices info founding inversions, 1s & 0s Parallel] L3 Cac92:13N0be03 04 19 02 02 03s11n01 0890a 006fe400 2048M of 4013M Memory69:78069M3c 69811M18s81 20t08r3c 3cf01f40f83 05 | Time: 0:05:38 ------00-00-00-00-00-00-00-00-00-84-00-00-00-00-00-00------------------------- Core#:00 00M00 00s00l00)00|00C00 00m00 00R0f:01102M00 (DDR3-833) - BCLK: 83 State:00 00 00s00C00 9-9-9-10 @ 64-bit Mode Cores:00100 Settings: 00 00 000 Errors: 0 ------00-00 00-00-00------------------------- 00 00 (1) Test Selection 00 c4 b1 Memory34P4b (2) Address Range 47 36 45 ------31-45 (3) Error Report Mode 00 00 00 - Sl00 00 (4) Core Selection 00600ZffG6E1E - Sl57 50 (5) Refresh Screen 3a641ZffG6E1E 32 30 (6) Display DMI Data ff ff ff ff ff (7) Display SPD Data ff ff ff ff ff ff ff ff ff ff (0) Continue ff ff ff Wabtec CPU-1900 (ESC)exit (c)configuration (SP)scroll_lock (CR)scroll_unlock ----- Not sure what is going on here. I don't have this issue without the popup patches. I'll look into it a bit more. Ben

5 years, 6 months

Re: [coreboot] Is anyone working on FMAP support in SeaBIOS?

by Ben Gardner

It turned out to be a lot easier than I expected. A patch can be found here: https://www.coreboot.org/pipermail/seabios/2016-March/010551.html On Wed, Mar 9, 2016 at 10:40 AM, Ben Gardner <gardner.ben(a)gmail.com> wrote: > Hi All, > > Before I get too far investigating adding FMAP support to SeaBIOS, I > just wanted to check if anyone else is working on this or has done > this. > > The goal is to have SeaBIOS look in an alternate CBFS for bootable img/* items. > > The plan is to have SeaBIOS find the FMAP location via the > BOOT_MEDIA_PARAMS (0x30) CB tag and then scan all available CBFS in > cbfs_payload_setup(). > > Thanks, > Ben

5 years, 6 months

Is anyone working on FMAP support in SeaBIOS?

by Ben Gardner

Hi All, Before I get too far investigating adding FMAP support to SeaBIOS, I just wanted to check if anyone else is working on this or has done this. The goal is to have SeaBIOS look in an alternate CBFS for bootable img/* items. The plan is to have SeaBIOS find the FMAP location via the BOOT_MEDIA_PARAMS (0x30) CB tag and then scan all available CBFS in cbfs_payload_setup(). Thanks, Ben

5 years, 6 months

Re: [coreboot] [GSoC 2016] ROM-O-Matic project

by Yurii Shevtsov

I looked at sites you mentioned. I haven't any configuration feature on johnlewis.ie Instead it provides an instruction for running special shell script. But I much more liked original Rom-o-matic. I want do develop same thing, but with fancier design, if you mind) I have more questions: How important this project for coreboot community is? Do I have to fix some bugs or make any other sort of contribution, before submitting my proposal? Do you have a proposal template or some special requirments for it? What do you think about nodejs, as a backend? Thanks in advance! 2016-03-09 6:24 GMT+02:00 ron minnich <rminnich(a)gmail.com>: > yeah, we had something like this in the linuxbios days. I think you don't > want to build it on demand, but rather have a bunch of pre-built images > that are known good. > > Really, look at johnlewis.ie, that's the best thing I've seen. Have you > also seen the original Rom-o-matic from the etherboot (now gpxe or ipxe) > project? > > ron > > On Tue, Mar 8, 2016 at 7:35 PM Yurii Shevtsov <ungetch(a)gmail.com> wrote: > >> Hello) I want to be a GSoC 2016 student. I really liked the idea of >> ROM-O-Matic project. Also it's a nice name. So, as I understood, the end >> user should get a website with a ROM configurator and a big 'Download' >> button, right? >> >> I'm student of Odessa polytechnic university, computer science. I have a >> good as for student experience in system and web programming >> -- >> coreboot mailing list: coreboot(a)coreboot.org >> https://www.coreboot.org/mailman/listinfo/coreboot > >

5 years, 6 months

Re: [coreboot] Fwd: Aspirant for GSOC 2016 with coreboot for ARM64 qemu port

by Stefan Reinauer

I suggest you start looking at the progress made last year and try to reproduce it: http://blogs.coreboot.org/blog/author/namang/ On 03/08/2016 06:35 PM, Saket Sinha wrote: > Hi Stephan, > > Any update on this. > > > Regards, > Saket Sinha > > > On Mon, Mar 7, 2016 at 10:47 AM, Saket Sinha <saket.sinha89(a)gmail.com> wrote: >> Hi Stefan, >> >> Thanks for the reply. >> >> I am interested in working with the ARM64 support in coreboot which >> was developed on Qemu last year. I want to carry forward the project >> and bring the support over real ARM64 board(I would be having Rasberry >> PI3 available with me pretty soon) . >> >> Let me know how to get started on the same. >> >> >> Regards, >> Saket Sinha >> >> >> On Mon, Mar 7, 2016 at 4:10 AM, Stefan Reinauer >> <stefan.reinauer(a)coreboot.org> wrote: >>> Hi Saket! >>> >>> Welcome to coreboot! >>> >>> Please check out our GSoC page at https://www.coreboot.org/GSoC and have a >>> look at our three sub projects this year: coreboot, flashrom and SerialICE. >>> If you have specific questions, please don't hesitate to ask. >>> >>> Stefan >>> >>> >>> On 02/29/2016 11:38 AM, Saket Sinha wrote: >>>> Hi, >>>> >>>> Congratulations to the coreboot team for selection in GSOC 2016. >>>> >>>> I am looking forward to participate in GSOC 2016 with coreboot for >>>> ARM64 qemu port. >>>> >>>> I request you to guide me as where to start with to prepare for this >>>> project. >>>> >>>> Regards, >>>> Saket Sinha >>>> >>>> >>>> >>>> ---------- Forwarded message ---------- >>>> From: Saket Sinha <saket.sinha89(a)gmail.com> >>>> Date: Fri, Feb 12, 2016 at 10:24 AM >>>> Subject: Aspirant for GSOC 2016 with coreboot for ARM64 qemu port >>>> To: adurbin(a)chromium.org, coreboot(a)coreboot.org >>>> Cc: Patrick Georgi <pgeorgi(a)google.com> >>>> >>>> >>>> Hi, >>>> >>>> I think this is early for this but I am looking forward to participate >>>> in GSOC 2016 with coreboot for ARM64 qemu port. >>>> >>>> This is to discuss the idea further. >>>> >>>> I guess the project was a part of last year GSOC as well so we already >>>> have some base-work to start with. >>>> >>>> I request you to guide me as where to start with to prepare for this >>>> project. >>>> >>>> >>>> Regards, >>>> Saket Sinha >>>> >>> >>> -- >>> coreboot mailing list: coreboot(a)coreboot.org >>> https://www.coreboot.org/mailman/listinfo/coreboot

5 years, 6 months

Re: [coreboot] [GSoC 2016] ROM-O-Matic project

by ron minnich

yeah, we had something like this in the linuxbios days. I think you don't want to build it on demand, but rather have a bunch of pre-built images that are known good. Really, look at johnlewis.ie, that's the best thing I've seen. Have you also seen the original Rom-o-matic from the etherboot (now gpxe or ipxe) project? ron On Tue, Mar 8, 2016 at 7:35 PM Yurii Shevtsov <ungetch(a)gmail.com> wrote: > Hello) I want to be a GSoC 2016 student. I really liked the idea of > ROM-O-Matic project. Also it's a nice name. So, as I understood, the end > user should get a website with a ROM configurator and a big 'Download' > button, right? > > I'm student of Odessa polytechnic university, computer science. I have a > good as for student experience in system and web programming > -- > coreboot mailing list: coreboot(a)coreboot.org > https://www.coreboot.org/mailman/listinfo/coreboot

5 years, 6 months

Query

by Damany Reid

Good Day, My name is Damany and I’m new to the area of open source software contributing. I learnt of the opportunities afforded through Google Summer of Code and I’m just wondering if I’m qualified enough to participate in your project. Im first year in university learning c which i would have completed it by the end of this semester, before summer. Thanks in advance, Damany

5 years, 6 months

Re: [coreboot] Fwd: Aspirant for GSOC 2016 with coreboot for ARM64 qemu port

by Saket Sinha

Hi Stephan, Any update on this. Regards, Saket Sinha On Mon, Mar 7, 2016 at 10:47 AM, Saket Sinha <saket.sinha89(a)gmail.com> wrote: > Hi Stefan, > > Thanks for the reply. > > I am interested in working with the ARM64 support in coreboot which > was developed on Qemu last year. I want to carry forward the project > and bring the support over real ARM64 board(I would be having Rasberry > PI3 available with me pretty soon) . > > Let me know how to get started on the same. > > > Regards, > Saket Sinha > > > On Mon, Mar 7, 2016 at 4:10 AM, Stefan Reinauer > <stefan.reinauer(a)coreboot.org> wrote: >> Hi Saket! >> >> Welcome to coreboot! >> >> Please check out our GSoC page at https://www.coreboot.org/GSoC and have a >> look at our three sub projects this year: coreboot, flashrom and SerialICE. >> If you have specific questions, please don't hesitate to ask. >> >> Stefan >> >> >> On 02/29/2016 11:38 AM, Saket Sinha wrote: >>> >>> Hi, >>> >>> Congratulations to the coreboot team for selection in GSOC 2016. >>> >>> I am looking forward to participate in GSOC 2016 with coreboot for >>> ARM64 qemu port. >>> >>> I request you to guide me as where to start with to prepare for this >>> project. >>> >>> Regards, >>> Saket Sinha >>> >>> >>> >>> ---------- Forwarded message ---------- >>> From: Saket Sinha <saket.sinha89(a)gmail.com> >>> Date: Fri, Feb 12, 2016 at 10:24 AM >>> Subject: Aspirant for GSOC 2016 with coreboot for ARM64 qemu port >>> To: adurbin(a)chromium.org, coreboot(a)coreboot.org >>> Cc: Patrick Georgi <pgeorgi(a)google.com> >>> >>> >>> Hi, >>> >>> I think this is early for this but I am looking forward to participate >>> in GSOC 2016 with coreboot for ARM64 qemu port. >>> >>> This is to discuss the idea further. >>> >>> I guess the project was a part of last year GSOC as well so we already >>> have some base-work to start with. >>> >>> I request you to guide me as where to start with to prepare for this >>> project. >>> >>> >>> Regards, >>> Saket Sinha >>> >> >> >> -- >> coreboot mailing list: coreboot(a)coreboot.org >> https://www.coreboot.org/mailman/listinfo/coreboot

5 years, 6 months

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coreboot March 2016