coreboot March 2016

coreboot@coreboot.org

43 participants
117 discussions

[GSoC 2016] ROM-O-Matic project
by Yurii Shevtsov 08 Mar '16

08 Mar '16

Hello) I want to be a GSoC 2016 student. I really liked the idea of ROM-O-Matic project. Also it's a nice name. So, as I understood, the end user should get a website with a ROM configurator and a big 'Download' button, right? I'm student of Odessa polytechnic university, computer science. I have a good as for student experience in system and web programming

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Introduction
by David Parreira 08 Mar '16

08 Mar '16

Hello, i'm David and I study Computer Science at Universidade de Évora. I'm having C classes and I know how to program in Assembly. I'd like to ask you some questions. Do you have a specifical project that you want to work on? Should I propose a project? I have no expirence on this area but I really would like to work with you and learn. Thank you! Greetings.

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New on blogs.coreboot.org: GSoC 2016
by WordPress 07 Mar '16

07 Mar '16

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Re: [coreboot] Fwd: Aspirant for GSOC 2016 with coreboot for ARM64 qemu port
by Stefan Reinauer 07 Mar '16

07 Mar '16

Hi Saket! Welcome to coreboot! Please check out our GSoC page at https://www.coreboot.org/GSoC and have a look at our three sub projects this year: coreboot, flashrom and SerialICE. If you have specific questions, please don't hesitate to ask. Stefan On 02/29/2016 11:38 AM, Saket Sinha wrote: > Hi, > > Congratulations to the coreboot team for selection in GSOC 2016. > > I am looking forward to participate in GSOC 2016 with coreboot for > ARM64 qemu port. > > I request you to guide me as where to start with to prepare for this project. > > Regards, > Saket Sinha > > > > ---------- Forwarded message ---------- > From: Saket Sinha <saket.sinha89(a)gmail.com> > Date: Fri, Feb 12, 2016 at 10:24 AM > Subject: Aspirant for GSOC 2016 with coreboot for ARM64 qemu port > To: adurbin(a)chromium.org, coreboot(a)coreboot.org > Cc: Patrick Georgi <pgeorgi(a)google.com> > > > Hi, > > I think this is early for this but I am looking forward to participate > in GSOC 2016 with coreboot for ARM64 qemu port. > > This is to discuss the idea further. > > I guess the project was a part of last year GSOC as well so we already > have some base-work to start with. > > I request you to guide me as where to start with to prepare for this project. > > > Regards, > Saket Sinha >

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New on blogs.coreboot.org: coreboot changelog Feb 17 - March 1
by WordPress 07 Mar '16

07 Mar '16

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Re: [coreboot] On Memtest86+ change sets up for review
by Martin Roth 07 Mar '16

07 Mar '16

Absolutely, please do. I'm not saying that I don't want development on our tree. I'm just not trying to take over from the memtest86+ guys at canardpc. I sent Doc TB a message to let him know that I had started the repo here, but I've got no idea how active he is, or even if he's still working on Memtest86+. He hasn't responded to me yet. Martin On Wed, Mar 2, 2016 at 4:07 PM, Ben Gardner <gardner.ben(a)gmail.com> wrote: > I'm all for a sane hosting location of memtest86+. > I marked all patches that I'm current using in my personal tree with > 'code-review+2' in gerrit. > > I've been sitting on Baytrail support patches. > If you are OK with this being an active branch, I can send those patches along. > > Ben > > On Mon, Feb 29, 2016 at 3:51 PM, Martin Roth <gaumless(a)gmail.com> wrote: >> Hi Paul, >> I'm not really interested in taking over memtest86+, I'm just >> creating a repository that we can build from and run as a payload. I >> originally looked at having the build process download the tarball and >> apply patches, but once I got up to 10 patches, I opted for starting a >> repo instead. One of my patches is to brand this as a coreboot >> release of Memtest86+ so that it's not confused with the 'official' >> release. >> >> I supplied some patches to Doc TB for the 5.0 release, but i haven't >> talked to anyone there recently. If they wanted to make this the >> official upstream repository and not use the coreboot branding, I'd be >> fine with that, but that wasn't my intention in creating this repo. >> >> Martin >> >> On Mon, Feb 29, 2016 at 12:56 PM, Paul Menzel >> <paulepanter(a)users.sourceforge.net> wrote: >>> Dear coreboot folks, >>> >>> >>> There are patches up for review [1], creating a new memtest86plus >>> project [2]. >>> >>> Martin, as you are the author, could you please give a little bit more >>> information? >>> >>> The last Memtest86+ release seems to be from 2013, and looking at your >>> change sets there are a lot of patches applied from the distributions. >>> So there is not much maintenance going on upstream. I could not find a >>> mailing list, but there is some activity in the forum [4]. >>> >>> I am interested in what the goal is? Do we want to be the new >>> Memtest86+ upstream? >>> >>> Have you talked to the Memtest86+ folks, so that they are informed? >>> Will they hand over the domain for example? >>> >>> >>> Thanks, >>> >>> Paul >>> >>> >>> [1] https://review.coreboot.org/#/q/project:memtest86plus >>> [2] https://review.coreboot.org/#/c/13818/ >>> [3] http://www.memtest.org/ >>> [4] http://forum.canardpc.com/forums/73-Memtest86-Official-forum >>> -- >>> coreboot mailing list: coreboot(a)coreboot.org >>> http://www.coreboot.org/mailman/listinfo/coreboot >> >> -- >> coreboot mailing list: coreboot(a)coreboot.org >> http://www.coreboot.org/mailman/listinfo/coreboot

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Compile coreboot 4.3 for Pc Engines Alix2d3
by Reto Rayen 07 Mar '16

07 Mar '16

Hi guys I tried now with the latest coreboot 4.3 to run the coreboot bios on a Alix2d3. But it always hangs after: «* DRAM Controller init done.». After this i do not see any further Output. Does anyone of you have a an idea what could be the issue? I added a ipxe Rom Image to the coreboot Rom. The layout is as follows: Name Offset Type Size cbfs master header 0x0 cbfs header 32 fallback/romstage 0x80 stage 12404 fallback/ramstage 0x3180 stage 69972 fallback/payload 0x14340 payload 60882 pci1106,3053.rom 0x23180 raw 81920 config 0x37200 raw 428 revision 0x37400 raw 602 payload_config 0x376c0 raw 1563 payload_revision 0x37d40 raw 219 vsa 0x37e80 stage 57532 (empty) 0x45f80 null 236568 bootblock 0x7fbc0 bootblock 768 The config file with the build Options can be found here: https://file.youngsolutions.ch/index.php/s/MrXbSGYdS5E8DsH Here a trace of the full Output: Setup throttling delays to proper mode Done cpuRegInit Ram1.00 Ram2.00 * sdram_set_spd_register spd_read_byte dev 50 addr 15 returns ff * Check DIMM 0 * Check DIMM 1 spd_read_byte dev 51 returns 0xff * Check DDR MAX spd_read_byte dev 50 addr 09 returns 0a spd_read_byte dev 51 returns 0xff * AUTOSIZE DIMM 0 * Check present spd_read_byte dev 50 addr 02 returns 07 * MODBANKS spd_read_byte dev 50 addr 05 returns 01 * FIELDBANKS spd_read_byte dev 50 addr 11 returns 04 * SPDNUMROWS spd_read_byte dev 50 addr 03 returns 03 spd_read_byte dev 50 addr 04 returns 0a * SPDBANKDENSITY spd_read_byte dev 50 addr 1f returns 40 * DIMMSIZE * BEFORT CTZ * TEST DIMM SIZE>8 * PAGESIZE spd_read_byte dev 50 addr 04 returns 0a * MAXCOLADDR * >12address test * RDMSR CF07 * WRMSR CF07 * ALL DONE * AUTOSIZE DIMM 1 * Check present spd_read_byte dev 51 returns 0xff * set cas latency spd_read_byte dev 50 addr 12 returns 10 spd_read_byte dev 50 addr 17 returns 3c spd_read_byte dev 50 addr 19 returns 4b spd_read_byte dev 51 returns 0xff * set all latency spd_read_byte dev 50 addr 1e returns 28 spd_read_byte dev 51 returns 0xff spd_read_byte dev 50 addr 1b returns 0f spd_read_byte dev 51 returns 0xff spd_read_byte dev 50 addr 1d returns 0f spd_read_byte dev 51 returns 0xff spd_read_byte dev 50 addr 1c returns 0a spd_read_byte dev 51 returns 0xff spd_read_byte dev 50 addr 2a returns 46 spd_read_byte dev 51 returns 0xff * set emrs spd_read_byte dev 50 addr 16 returns ff spd_read_byte dev 51 returns 0xff * set ref rate spd_read_byte dev 50 addr 0c returns 3a spd_read_byte dev 51 returns 0xff Ram3 * DRAM controller init done. Gesendet von Mail für Windows 10

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Re: [coreboot] GSoC 2016
by Stefan Reinauer 06 Mar '16

06 Mar '16

On 03/06/2016 10:35 AM, Tahir Ramzan wrote: > Respected Sir, > > I am a MS CS scholar of Virtual University of Pakistan, I want to > participate in GSoC 2016 for coreboot. Data Science, Networks, > Information security, digital forensics and ethical hacking are my > core areas of interest. > > Currently, I am working on a research project on live forensics of GPU > and volatile memories like RAMs and Caches. > > I am looking forward your guidance to start my contribution for > coreboot, thanks in anticipation. > > Regards > Tahir Ramzan Hi Tahir, Thank you for your interest. Your background looks very interesting! did you take the time to determine what you might be interested in working on, already? Please take a look at our GSoC page at https://www.coreboot.org/GSoC and the ideas pages of the three projects we are hosting this year (coreboot, flashrom, serialice) and let us know if you have any questions Stefan

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Re: [coreboot] Coreboot table
by Stefan Reinauer 06 Mar '16

06 Mar '16

On 03/06/2016 07:50 AM, daoud yessine wrote: > Hi > > I need your help please :) > > About coreboot table , where is its location in memory ? Its size ? > Its contents ? Is it saved in buffer ? > The coreboot table typically lives at the end of physical memory in the 4G space (e.g. in "cbmem space"). There is a forwarder entry pointing to it, living in the lower 4k of memory (typically at 0x500) The coreboot table contains various information coreboot collects about the system, such as - memory map - coreboot version - cmos options - framebuffer configuration You can use the nvramtool utility to dump the coreboot table and look at it. Stefan

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Re: [coreboot] Timestamp
by Stefan Reinauer 06 Mar '16

06 Mar '16

On 03/06/2016 10:36 AM, daoud yessine wrote: > Hi > > how we can get the timestamp from coreboot ? > > what's the name of table in the source code in which the timestamps > are saved ? > What is the configuration needed to obtain the timestamp table ? > > thanks > ᐧ TThe timestamps live in an area at the end of the memory below 4G that we call "CBMEM" Other information like the in-memory console or code coverage information, lives in that same memory data structure. Stefan

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coreboot March 2016