coreboot December 2016

coreboot@coreboot.org

57 participants
121 discussions

Re: [coreboot] TALOS project short of funding goals - where to now?
by Paul Menzel 13 Dec '16

13 Dec '16

Dear Elena, Am Montag, den 12.12.2016, 14:50 +0100 schrieb Elena ``of Valhalla'': > On 2016-12-12 at 13:18:42 +0100, Łukasz Dobrowolski wrote: > > On 12/12/2016 03:27 AM, Taiidan(a)gmx.com wrote: > > > (...) considering that the average linux sysadmin makes over > > > $100K per year the community could have easily funded the > > > project. > > > > In Germany, US, France... Not in Poland, Ukraine... many hackers there. > > Indeed. In my country 20k EUR per year is a good pay, but even with a > pay of 60k EUR|$ a year, that would mean paying the whole earnings of a > month for something that is still at the crowdfunding stage and may just > disappear into nothing. > > If you consider that people have to, well, live with that money, that > would mean multiple months of savings / disposable income. > > If somebody has a family, that probably goes in the range of expenses > that have to be negotiated with the other family members. > > All of this necessarily reduces the number of people who can even think > about partecipating in that crowdfunding, not to say actually decide to > put down their money for it. Unfortunately, I don’t agree. There was the option to support the project with less money. People can pledge $10, $250, or $500. In my opinion, everybody interested in user-controlled hardware would be able to spend at least $10. But it looks like there are well below 300 people interested in that. That is very sad to see, that people are not willing to support to kick-start such a project to maybe profit in the future from cheaper devices. In my opinion, people are ignorant about the locked-down hardware issue and some don’t care. On the other hand, I also think, that maybe marketing was probably not as successful as for other projects. At least I didn’t see a lot of marketing support from the FSF, FSFE, and EFF. The media also didn’t help very much. Thanks, Paul PS: Wikipedia is also asking for donations right now. Despite the bad things about Wikipedia, I guess most of us use it daily and want it to remain maintained and free of advertisement. [1] https://www.crowdsupply.com/raptor-computing-systems/talos-secure-workstati…

1 0

Re: [coreboot] kgpe-d16 and usb boot
by ron minnich 13 Dec '16

13 Dec '16

never mind, pilot error, I did not realize it was a linux partition, not fat32. oops. On Tue, Dec 13, 2016 at 3:20 PM ron minnich <rminnich(a)gmail.com> wrote: > we have a kgpe-d16 with seabios as the payload and would like to usb boot. > We have two sticks which work fine on other systems. > > seabios is not seeing the usb sticks. Anyone have configuration or other > hints about what I might be doing wrong? > > thanks >

1 0

kgpe-d16 and usb boot
by ron minnich 13 Dec '16

13 Dec '16

we have a kgpe-d16 with seabios as the payload and would like to usb boot. We have two sticks which work fine on other systems. seabios is not seeing the usb sticks. Anyone have configuration or other hints about what I might be doing wrong? thanks

1 0

Re: [coreboot] T430s or T430 (Was: latest greatest thinkpad with coreboot)
by Klemens Nanni 13 Dec '16

13 Dec '16

On Tue, Dec 06, 2016 at 02:40:46AM +0800, Pok Gu wrote: >Thanks all. I value all your concerns on freedom (not opensource) and >security and the feeling of having control. >Let's say down to earth. I just wondering are there any other cool things >(e.g., unlocking features) we can get. Because it seems the reason that >other projects (e.g., OpenWRT) is so popular is it unlock many features >along with the freedom/security once a router flash it. Yes, you get rid of the PCI whitelist allowing you to use any wifi module (being supported by free drivers). You may also install more RAM depending on both board and RAM type. Please correct me if I'm wrong. /kl3

2 1

Re: [coreboot] TPM device has gone missing
by Trammell Hudson 12 Dec '16

12 Dec '16

On Mon, Dec 12, 2016 at 03:08:53PM -0600, Aaron Durbin via coreboot wrote: > What about the SSDT? With the patch I think the device is in the SSDT > -- not DSDT. Whups, forgot to include it. There is far less change: --- ./no-tpm/SSDT.dsl 2016-12-12 17:23:51.314355365 -0500 +++ ./yes-tpm/SSDT.dsl 2016-12-12 17:24:08.694610389 -0500 @@ -5,13 +5,13 @@ * * Disassembling to symbolic ASL+ operators * - * Disassembly of SSDT, Mon Dec 12 17:23:51 2016 + * Disassembly of SSDT, Mon Dec 12 17:24:08 2016 * * Original Table Header: * Signature "SSDT" * Length 0x0000170D (5901) * Revision 0x02 - * Checksum 0xB4 + * Checksum 0x83 * OEM ID "CORE " * OEM Table ID "COREBOOT" * OEM Revision 0x0000002A (42) @@ -73,7 +73,7 @@ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings { Memory32Fixed (ReadOnly, - 0xBFEED000, // Address Base + 0xBFEF0000, // Address Base 0x00008000, // Address Length ) }) -- Trammell

2 1

Re: [coreboot] TPM device has gone missing
by Trammell Hudson 12 Dec '16

12 Dec '16

On Mon, Dec 12, 2016 at 01:14:58PM -0600, Aaron Durbin via coreboot wrote: > Can you provide the isal -d dumps of before and after for your board? > I think in one they'll be in SSDT and the other in DSDT. They should > reside in /sys/firmware/acpi/tables/ that you can copy them and run > them through iasl -d. Here's the diff: --- ./no-tpm/DSDT.dsl 2016-12-12 15:46:55.909063709 -0500 +++ ./yes-tpm/DSDT.dsl 2016-12-12 15:56:26.308433858 -0500 @@ -5,13 +5,13 @@ * * Disassembling to symbolic ASL+ operators * - * Disassembly of DSDT, Mon Dec 12 15:46:55 2016 + * Disassembly of DSDT, Mon Dec 12 15:56:26 2016 * * Original Table Header: * Signature "DSDT" - * Length 0x000033DC (13276) + * Length 0x00003627 (13863) * Revision 0x02 - * Checksum 0x58 + * Checksum 0x26 * OEM ID "COREv4" * OEM Table ID "COREBOOT" * OEM Revision 0x20110725 (537986853) @@ -36,7 +36,7 @@ Scope (\) { - Name (NVSA, 0xBFEC8000) + Name (NVSA, 0xBFECB000) } If (Zero) @@ -3961,6 +3961,205 @@ Scope (_SB.PCI0.LPCB) { + Device (TPM) + { + Name (_HID, EisaId ("PNP0C31")) // _HID: Hardware ID + Name (_CID, EisaId ("PNP0C31")) // _CID: Compatible ID + Name (_UID, One) // _UID: Unique ID + OperationRegion (TREG, SystemMemory, 0xFED40000, 0x5000) + Field (TREG, ByteAcc, NoLock, Preserve) + { + Offset (0x08), + , 3, + ITPL, 2, + Offset (0x0C), + IVEC, 4, + Offset (0xF00), + DVID, 32 + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + If (((DVID > Zero) && (DVID < 0xFFFFFFFF))) + { + Return (0x0F) + } + Else + { + Return (Zero) + } + } + + Name (IBUF, ResourceTemplate () + { + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, _Y02) + { + 0x00000000, + } + }) + Name (RBUF, ResourceTemplate () + { + IO (Decode16, + 0x002E, // Range Minimum + 0x002E, // Range Maximum + 0x01, // Alignment + 0x02, // Length + ) + Memory32Fixed (ReadWrite, + 0xFED40000, // Address Base + 0x00005000, // Address Length + ) + }) + Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings + { + CreateField (IBUF, \_SB.PCI0.LPCB.TPM._Y02._INT, 0x20, TVEC) // _INT: Interrupts + CreateBitField (IBUF, \_SB.PCI0.LPCB.TPM._Y02._HE, TTYP) // _HE_: High-Edge + CreateBitField (IBUF, \_SB.PCI0.LPCB.TPM._Y02._LL, TPOL) // _LL_: Low Level + CreateBitField (IBUF, \_SB.PCI0.LPCB.TPM._Y02._SHR, TSHR) // _SHR: Sharable + If (Zero) + { + TVEC = Zero + TPOL = One + TTYP = Zero + TSHR = One + Return (ConcatenateResTemplate (RBUF, IBUF)) + } + Else + { + If ((IVEC > Zero)) + { + TVEC = IVEC /* \_SB_.PCI0.LPCB.TPM_.IVEC */ + If ((ITPL == Zero)) + { + TPOL = Zero + TTYP = Zero + TSHR = One + } + Else + { + If ((ITPL == One)) + { + TPOL = One + TTYP = Zero + TSHR = One + } + Else + { + If ((ITPL == 0x02)) + { + TPOL = Zero + TTYP = One + TSHR = Zero + } + Else + { + If ((ITPL == 0x03)) + { + TPOL = One + TTYP = One + TSHR = Zero + } + } + } + } + + Return (ConcatenateResTemplate (RBUF, IBUF)) + } + Else + { + Return (RBUF) /* \_SB_.PCI0.LPCB.TPM_.RBUF */ + } + } + } + + Method (_DSM, 4, Serialized) // _DSM: Device-Specific Method + { + If ((Arg0 == ToUUID ("3dddfaa6-361b-4eb4-a424-8d10089d1653") /* Physical Presence Interface */)) + { + If ((Arg2 == Zero)) + { + Return (Buffer (0x02) + { + 0xFF, 0x01 /* .. */ + }) + } + + If ((Arg2 == One)) + { + Return ("1.2") + } + + If ((Arg2 == 0x02)) + { + Return (Zero) + } + + If ((Arg2 == 0x03)) + { + Return (Package (0x02) + { + Zero, + Zero + }) + } + + If ((Arg2 == 0x04)) + { + Return (0x02) + } + + If ((Arg2 == 0x05)) + { + Return (Package (0x03) + { + Zero, + Zero, + Zero + }) + } + + If ((Arg2 == 0x06)) + { + Return (0x03) + } + + If ((Arg2 == 0x07)) + { + Return (0x03) + } + + If ((Arg2 == 0x08)) + { + Return (One) + } + + Return (One) + } + + If ((Arg0 == ToUUID ("376054ed-cc13-4675-901c-4756d7f2d45d"))) + { + If ((Arg2 == Zero)) + { + Return (Buffer (One) + { + 0x03 /* . */ + }) + } + + If ((Arg2 == One)) + { + Return (Zero) + } + + Return (One) + } + + Return (Buffer (One) + { + 0x00 /* . */ + }) + } + } } Name (_S0, Package (0x04) // _S0_: S0 System State -- Trammell

2 1

TPM device has gone missing
by Trammell Hudson 12 Dec '16

12 Dec '16

My x230's TPM has gone missing somewhere between 4.5 and the current head. CONFIG_LPC_TPM is still set, but neither coreboot nor the Linux payload detects it. Bisecting will take a while since it requires reflashing; does anyone know where it might have gone? -- Trammell

2 2

Re: [coreboot] Battery thresholds on lenovo T400
by ron minnich 12 Dec '16

12 Dec '16

I think it would be interesting to have such functionality in userspace. On Mon, Dec 12, 2016 at 8:04 AM Michal Widlok <michalwd1979(a)gmail.com> wrote: > Dear Members, > > I looking for a way to set battery charge thresholds on T400 with > coreboot. I know that tp_smapi are not supported, but I found an > interesting thread (it's for X220, but I hope that my would be > similar): > https://www.flashrom.org/pipermail/coreboot/2016-May/081460.html > > The post says: > "tp smapi depends on lot of SMM/SMI code. So tp-smapi kernel module > asked the Lenovo BIOS to tell the EC to do something. coreboot don't > want to support SMM/SMI APIs, because they are quite dangerous. > But there is another way to get those features back. > We know how to enable it, but we haven't yet create a way to control > this by the user. > > One thing could be a userspace tool executed as root or we add another > CMOS configuration for it. Any idea?" > > Is that mean that EC in lenovo laptops is "known" enough to control > it, but coreboot is not ready to implement this functionality? An if > it is known the is there any literature/posts available that says how > to control it with ectool or something? > > If there are any test needed to be done to help about this subject, > then I can do them on my laptop. Hardware flashing is possible also. > Very best regards, > Michael Widlok > > -- > coreboot mailing list: coreboot(a)coreboot.org > https://www.coreboot.org/mailman/listinfo/coreboot >

1 0

Linux 4.7 kernel payload with CoreBoot 4.4
by Trammell Hudson 12 Dec '16

12 Dec '16

The Linux 4.7 kernel payload crashes early in the boot process with CoreBoot 4.4. I traced it to these instructions that are finding a safe spot to decompress the rest of the kernel and patched around it with a hard coded location: diff -u --recursive /home/hudson/build/clean/linux-4.7/arch/x86/boot/compressed/head_64.S ./linux-4.7/arch/x86/boot/compressed/head_64.S --- /home/hudson/build/clean/linux-4.7/arch/x86/boot/compressed/head_64.S 2016-07-24 15:23:50.000000000 -0400 +++ ./linux-4.7/arch/x86/boot/compressed/head_64.S 2016-08-05 12:07:11.399854225 -0400 @@ -340,9 +357,15 @@ 1: /* Target address to relocate to for decompression */ +#if 0 movl BP_init_size(%rsi), %ebx subl $_end, %ebx addq %rbp, %rbx +#else + // coreboot does not populate the init_size boot param? + // fake it with a hard coded value + movl $0x97b000, %ebx +#endif /* Set up the stack */ leaq boot_stack_end(%rbx), %rsp It seems that the Linux kernel bzImage is supposed to set this value, rather than coreboot, so my comment is likely incorrect. Dumping linux-4.7/arch/x86/boot/header.o, it looks like init_siez is supposed to be 0xcf5000, so I wonder if %rsi is pointing to the wrong location. In 4.6.4 the computed address was hardcoded: movl $LOAD_PHYSICAL_ADDR, %ebx /* Target address to relocate to for decompression */ addl $z_extract_offset, %ebx 3e: bb 00 00 00 01 mov $0x1000000,%ebx 43: 81 c3 00 00 00 00 add $0x0,%ebx -- Trammell

4 4

Battery thresholds on lenovo T400
by Michal Widlok 12 Dec '16

12 Dec '16

Dear Members, I looking for a way to set battery charge thresholds on T400 with coreboot. I know that tp_smapi are not supported, but I found an interesting thread (it's for X220, but I hope that my would be similar): https://www.flashrom.org/pipermail/coreboot/2016-May/081460.html The post says: "tp smapi depends on lot of SMM/SMI code. So tp-smapi kernel module asked the Lenovo BIOS to tell the EC to do something. coreboot don't want to support SMM/SMI APIs, because they are quite dangerous. But there is another way to get those features back. We know how to enable it, but we haven't yet create a way to control this by the user. One thing could be a userspace tool executed as root or we add another CMOS configuration for it. Any idea?" Is that mean that EC in lenovo laptops is "known" enough to control it, but coreboot is not ready to implement this functionality? An if it is known the is there any literature/posts available that says how to control it with ectool or something? If there are any test needed to be done to help about this subject, then I can do them on my laptop. Hardware flashing is possible also. Very best regards, Michael Widlok

1 0

← Newer
1
...
5
6
7
8
9
10
11
12
13
Older →

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

coreboot December 2016