coreboot September 2015

coreboot@coreboot.org

36 participants
50 discussions

Lenovo X60 broken by Change 11388
by Mono 07 Sep '15

07 Sep '15

Hallo all, with Change 11388/commit 7dbf9c6 (edid: Use edid_mode struct to reduce redundancy) compiling coreboot for Lenovo X60 fails with this error: CC northbridge/intel/i945/gma.ramstage.o src/northbridge/intel/i945/gma.c: In function 'intel_gma_init': src/northbridge/intel/i945/gma.c:111:19: error: 'struct edid' has no member named 'phsync' hpolarity = (edid.phsync == '-'); ^ src/northbridge/intel/i945/gma.c:112:19: error: 'struct edid' has no member named 'pvsync' vpolarity = (edid.pvsync == '-'); ^ src/northbridge/intel/i945/gma.c:115:21: error: 'struct edid' has no member named 'hborder' right_border = edid.hborder; ^ src/northbridge/intel/i945/gma.c:116:22: error: 'struct edid' has no member named 'vborder' bottom_border = edid.vborder; ^ src/northbridge/intel/i945/gma.c:117:15: error: 'struct edid' has no member named 'vbl' vblank = edid.vbl; ^ src/northbridge/intel/i945/gma.c:118:15: error: 'struct edid' has no member named 'hbl' hblank = edid.hbl; ^ src/northbridge/intel/i945/gma.c:119:14: error: 'struct edid' has no member named 'vspw' vsync = edid.vspw; ^ src/northbridge/intel/i945/gma.c:120:14: error: 'struct edid' has no member named 'hspw' hsync = edid.hspw; ^ src/northbridge/intel/i945/gma.c:121:21: error: 'struct edid' has no member named 'hso' hfront_porch = edid.hso; ^ src/northbridge/intel/i945/gma.c:122:21: error: 'struct edid' has no member named 'vso' vfront_porch = edid.vso; ^ src/northbridge/intel/i945/gma.c:163:58: error: 'struct edid' has no member named 'pixel_clock' target_frequency = conf->gpu_lvds_is_dual_channel ? edid.pixel_clock ^ src/northbridge/intel/i945/gma.c:164:14: error: 'struct edid' has no member named 'pixel_clock' : (2 * edid.pixel_clock); ^ Makefile:236: recipe for target 'build/northbridge/intel/i945/gma.ramstage.o' failed make: *** [build/northbridge/intel/i945/gma.ramstage.o] Error 1 could you please point me to how to fix this? thank you! Mono

2 1

pcengines apu1 nvram support
by Maxime de Roucy 06 Sep '15

06 Sep '15

Hello, I made a patch for the pcengines apu1 board to support nvram (HAVE_OPTION_TABLE). I made/adapt this patch from the "Sage" source available at http://www.pcengines.ch/howto.php#CoreBoot -- Regards Maxime de Roucy

1 1

coreboot meeting 2015: SerialICE workshop?
by Paul Menzel 05 Sep '15

05 Sep '15

Dear coreboot folks, the coreboot meeting 2015 is taking place soon from October 9th to 11th [1]. Reading so much about SerialICE [2] and never having really used it, would there be one of the experts be willing to do some kind of workshop. That’d be really awesome! I am looking forward to seeing you all. Thanks, Paul [1] http://blogs.coreboot.org/blog/2015/08/04/coreboot-conference-in-europe-oct… [2] http://www.serialice.com

2 1

Support intel Bay-trail tablet pc board
by Adil producer 05 Sep '15

05 Sep '15

Hi, My name is Adil. I with my friend developing console for smart home system based on Intel Z3735g tablet pc motherboard. We planning use coreboot for booting write it on SPI flash. Now we have two Chinese tablet pc motherboard we BIOS on Winbond 25Q64FWSIG. But we don't found in supported hardware list Bay-trail chips. We need help to prepare firmware for this boot. Can you help us? If we successful boot on this motherboard - we send you all instructions and Bay-trail chips can supported coreboot. Thanks.

1 0

Re: [coreboot] build fails when CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT is set
by Julius Werner 04 Sep '15

04 Sep '15

+Dave for visibility, was a simple oversight in the refactoring On Fri, Sep 4, 2015 at 5:12 AM, Iru Cai <mytbk920423(a)gmail.com> wrote: > Hi, > > I was trying to build coreboot with the latest git code and build failed > when CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT is set. Some of the error message > is: > > $ make > CREATE build/mainboard/lenovo/x220/cbfs-file.c7KD3B.out (from > src/mainboard/lenovo/x220/cmos.default) > Created CBFS (capacity = 1046552 bytes) > E: Input file size (68464) greater than page size (65536). > GEN generated/romstage.ld > LINK cbfs/fallback/romstage.debug > OBJCOPY cbfs/fallback/romstage.elf > CBFS coreboot.pre > CC > northbridge/intel/sandybridge/gma_sandybridge_lvds.ramstage.o > src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c: In function > 'i915lightup_sandy': > src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c:195:21: error: > 'struct edid' has no member named 'hborder' > right_border = edid.hborder; > ^ > > After I searched the git log, I found this commit cause the error: > commit 7dbf9c6747ccdfa8b993d3843a22722742957611 > Author: David Hendricks <dhendrix(a)chromium.org> > Date: Thu Jul 30 18:49:48 2015 -0700 > > edid: Use edid_mode struct to reduce redundancy > > This replaces various timing mode parameters parameters with > an edid_mode struct within the edid struct. > > I hope someone will fix the error soon. > > Iru Cai > > > -- > coreboot mailing list: coreboot(a)coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot >

1 0

build fails when CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT is set
by Iru Cai 04 Sep '15

04 Sep '15

Hi, I was trying to build coreboot with the latest git code and build failed when CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT is set. Some of the error message is: $ make CREATE build/mainboard/lenovo/x220/cbfs-file.c7KD3B.out (from src/mainboard/lenovo/x220/cmos.default) Created CBFS (capacity = 1046552 bytes) E: Input file size (68464) greater than page size (65536). GEN generated/romstage.ld LINK cbfs/fallback/romstage.debug OBJCOPY cbfs/fallback/romstage.elf CBFS coreboot.pre CC northbridge/intel/sandybridge/gma_sandybridge_lvds.ramstage.o src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c: In function 'i915lightup_sandy': src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c:195:21: error: 'struct edid' has no member named 'hborder' right_border = edid.hborder; ^ After I searched the git log, I found this commit cause the error: commit 7dbf9c6747ccdfa8b993d3843a22722742957611 Author: David Hendricks <dhendrix(a)chromium.org> Date: Thu Jul 30 18:49:48 2015 -0700 edid: Use edid_mode struct to reduce redundancy This replaces various timing mode parameters parameters with an edid_mode struct within the edid struct. I hope someone will fix the error soon. Iru Cai

1 0

Linux 4.0.x iomem regression
by Torsten Duwe 03 Sep '15

03 Sep '15

JFYI, I got stuck with kernel 3.19 this spring, and Linux-4.0 didn't work properly on my coreboot machine. Only now I've had time to look into this. To make it short: the fault is in the Linux PCI/ACPI code; see mainline commit 2c62e8492, which fixes this in 4.1-rc3. You may want to skim through https://lkml.org/lkml/2015/4/3/608 to get an idea of this mess. " I did it because Windows apparently does that ..." I'm not sure if and why proprietary BIOSes are unaffected. Just to let you all know in case you're bisecting across 4.0 linux kernels. Torsten

2 1

Acer Chromebook 15 debug
by John Lewis 03 Sep '15

03 Sep '15

Hi Guys, Coolstar Organisation wants to do his Windows thang with one of the Broadwell Chromebooks, so I'm trying to build a working ROM with chromium.googlesource.com/chromiumos/third_party/coreboot/+/firmware-yuna-6… to give him a hand. Luckily USB debug works with this, so here is what I'm getting. What could I do next? Incidentally, if I flash back my backup, it goes into recovery mode now every time I boot (flags are 0x489), I've tried pulling the battery to no avail. If anyone has a trick to get around that, I'd appreciate it, as the Acer is my main machine. -⁠John. coreboot-⁠5cbe3a8-⁠dirty romstage Sun Aug 23 12:18:55 BST 2015 starting... PM1_STS: 8910 PM1_EN: 0000 PM1_CNT: 00000000 TCO_STS: 0000 0000 GPE0_STS: 1ef82df0 187d4fdf 0005f240 00000000 GPE0_EN: 00000000 00000000 00000000 00000000 GEN_PMCON: 0200 2024 520b Previous Sleep State: S5 CPU: Intel(R) Core(TM) i3-⁠5005U CPU @ 2.00GHz CPU: ID 306d4, Broadwell E0 or F0, ucode: 0000001d CPU: AES supported, TXT NOT supported, VT supported MCH: device id 1604 (rev 09) is Broadwell F0 PCH: device id 9cc5 (rev 03) is Broadwell U Base IGD: device id 1616 (rev 09) is Broadwell U GT2 CPU: frequency set to 2000 MHz SPD: index 1 (GPIO47=0 GPIO9=0 GPIO13=1) SPD: module type is DDR3 SPD: module part is HMT425S6AFR6A-⁠PB SPD: banks 8, ranks 1, rows 15, columns 10, density 4096 Mb SPD: device width 16 bits, bus width 64 bits SPD: module size is 2048 MB (per channel) Boot Count incremented to 8 ME: FW Partition Table : OK ME: Bringup Loader Failure : NO ME: Firmware Init Complete : NO ME: Manufacturing Mode : NO ME: Boot Options Present : NO ME: Update In Progress : NO ME: Current Working State : Normal ME: Current Operation State : Bring up ME: Current Operation Mode : Normal ME: Error Code : No Error ME: Progress Phase : BUP Phase ME: Power Management Event : Pseudo-⁠global reset ME: Progress Phase State : Waiting for DID BIOS message ME: HSIO Version : 8705 (CRC 0xfbc2) No FMAP found at ffe10000. FMAP: area RW_MRC_CACHE not found No MRC cache found. Starting Memory Reference Code Initializing Policy Installing common PPI MRC: Starting... Initializing Memory MRC: Done. MRC Version 2.6.0 Build 0 memcfg DDR3 clock 1600 MHz memcfg channel assignment: A: 0, B 1, C 2 memcfg channel[0] config (00780008): enhanced interleave mode on rank interleave on DIMMA 2048 MB width x16 single rank, selected DIMMB 0 MB width x16 single rank memcfg channel[1] config (00780008): enhanced interleave mode on rank interleave on DIMMA 2048 MB width x16 single rank, selected DIMMB 0 MB width x16 single rank CBMEM: root @ 7cfff000 254 entries. MRC data at ff7d0d9c 6246 bytes Relocate MRC DATA from ff7d0d9c to 7cfeb000 (6246 bytes) create cbmem for dimm information

2 6

Is flashrom safe on the x220 with coreboot?
by James Heald 03 Sep '15

03 Sep '15

Hi there! Just curious, I was able to successfully (albeit maybe not very intelligently) read the flash chip on my lappy twice, and it read successfully. However, since the x220 is not "officially" supported by flashrom I has to use laptop:force_i_want_a_brick. I'm curious if anyone with the x220 has reflashed coreboot (multiple times even?) on their x220 and not had any issues. I *thought* I read somewhere that since the firmware is unlocked it was safe to do, though I could have been reading something for another laptop. Thanks! Jim

1 0

New on blogs.coreboot.org: 2015-08-28 Librem 13: Weekly BIOS Update
by WordPress 02 Sep '15

02 Sep '15

1 0

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

coreboot September 2015