coreboot August 2015

coreboot@coreboot.org

45 participants
86 discussions

Is it possible to use an Ivy Bridge CPU in an Sandy Bridge laptop?
by Iru Cai 12 Aug '15

12 Aug '15

Hi, Ivy Bridge processor can be installed on a 6 series motherboard on desktop. However, Intel didn't give official support for snb laptops to install an ivb processor. Did anyone tried to insall an ivb processor into an snb machine (I think ThinkPad T520 is a good choice.) to check whether coreboot can support this? Thanks, Iru

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coreboot meeting @chaos communication camp
by Alexander Couzens 12 Aug '15

12 Aug '15

hi, some people will visit the chaos communication camp this year. I'll be around for coreboot hacking and give some people a introduction into coreboot. I've started a etherpad for (hardware) organisation. Who brings what or can bring?! https://pads.ccc.de/coreboot-camp-2015 Best, lynxis -- Alexander Couzens mail: lynxis(a)fe80.eu jabber: lynxis(a)jabber.ccc.de mobile: +4915123277221

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REACTS system sources now available under the AGPL!
by Timothy Pearson 11 Aug '15

11 Aug '15

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 All, The source code for the REACTS system is now available for download under the AGPL! Sufficiently knowledgeable developers can now assemble their own coreboot test stand(s) from COTS hardware and their favorite Linux distribution. For more information please visit this link: https://raptorengineeringinc.com/content/REACTS/sintro.html For those wanting a pre-packaged, off the shelf solution backed with professional support, we offer an easy to use solution here: https://raptorengineeringinc.com/content/REACTS/intro.html Enjoy! - -- Timothy Pearson Raptor Engineering +1 (415) 727-8645 http://www.raptorengineeringinc.com -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org/ iQEcBAEBAgAGBQJVyml3AAoJEK+E3vEXDOFbOUYH/i5mNlSImXSBxsoHddMtqK/R J7Ywg/xiD7UcSzv4f2dKzQhq6C/J3vgwYClqDr3wbPhnIwaAy/beZhLdf4Z3jGcH uwpxbQA5UsP6pY4CdpznH4WpBH5H3vr1ZPr4PfeFs4tkQQYByEImEsFLN3rIaazq 5i+ux7pkb48hVOWp5DSfFf6gaqw0Fiy4LQCBCZhPMsipM/Jy/AKp8Hr2iE2naWMR erB5FJzj7EIquaZzsOSbuNLKkQLmAteSWtvvct8f7UOIzUs1mgycDo0Y4pbFDoh8 uOBpIR0PjgeMTxX2oImh1Mnb5UR/zBtlA/HQJFIlI/574bSeIqmSVmBb1L80GFg= =35cU -----END PGP SIGNATURE-----

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QEMU crashes when pressing ESC in coreinfo payload
by Paul Menzel 11 Aug '15

11 Aug '15

Dear coreboot folks, building coreboot commit 82fe9082 (getac/p470: Clean up SIO access in ACPI) with the attached config and adding the attached coreinfo payload, everything works fine, but pressing ESC crashes QEMU. ``` $ qemu-system-i386 --version QEMU emulator version 2.3.0 (Debian 1:2.3+dfsg-6a), Copyright (c) 2003-2008 Fabrice Bellard $ build/cbfstool build/coreboot.rom add-payload -n fallback/payload -f coreinfo.elf -c lzma $ qemu-system-i386 -bios build/coreboot.rom -debugcon stdio QEMU debugcon detected [port 0xe9] coreboot-4.1-228-g82fe908 Tue Aug 11 15:54:03 UTC 2015 romstage starting... CBMEM: IMD: root @ 07fff000 254 entries. IMD: root @ 07ffec00 62 entries. CBFS provider active. CBFS @ 0 size 3fc40 CBFS: Locating 'fallback/ramstage' CBFS: Found @ offset 47c0 size a08d 'fallback/ramstage' located at offset: 47f8 size: a08d QEMU debugcon detected [port 0xe9] coreboot-4.1-228-g82fe908 Tue Aug 11 15:54:03 UTC 2015 ramstage starting... Moving GDT to 07ffe8c0...ok Enumerating buses... Show all devs... Before device enumeration. Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 DOMAIN: 0000: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:01.0: enabled 1 PCI: 00:01.1: enabled 1 PCI: 00:01.3: enabled 1 Compare with tree... Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 DOMAIN: 0000: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:01.0: enabled 1 PCI: 00:01.1: enabled 1 PCI: 00:01.3: enabled 1 Root Device scanning... root_dev_scan_bus for Root Device CPU_CLUSTER: 0 enabled DOMAIN: 0000 enabled CPU_CLUSTER: 0 scanning... QEMU: firmware config interface detected QEMU: max_cpus is 1 CPU: APIC: 00 enabled DOMAIN: 0000 scanning... PCI: pci_scan_bus for bus 00 PCI: 00:00.0 [8086/1237] ops PCI: 00:00.0 [8086/1237] enabled PCI: 00:01.0 [8086/7000] bus ops PCI: 00:01.0 [8086/7000] enabled PCI: 00:01.1 [8086/7010] ops PCI: 00:01.1 [8086/7010] enabled PCI: 00:01.3 [8086/7113] bus ops PCI: 00:01.3 [8086/7113] enabled PCI: 00:02.0 [1234/1111] ops PCI: 00:02.0 [1234/1111] enabled PCI: 00:03.0 [8086/100e] enabled PCI: 00:01.0 scanning... scan_lpc_bus for PCI: 00:01.0 scan_lpc_bus for PCI: 00:01.0 done PCI: 00:01.3 scanning... scan_smbus for PCI: 00:01.3 scan_smbus for PCI: 00:01.3 done root_dev_scan_bus for Root Device done done found VGA at PCI: 00:02.0 Setting up VGA for PCI: 00:02.0 Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device Allocating resources... Reading resources... Root Device read_resources bus 0 link: 0 CPU_CLUSTER: 0 read_resources bus 0 link: 0 APIC: 00 missing read_resources CPU_CLUSTER: 0 read_resources bus 0 link: 0 done QEMU: 11 files in fw_cfg QEMU: etc/boot-fail-wait [size=4] QEMU: etc/smbios/smbios-tables [size=320] QEMU: etc/smbios/smbios-anchor [size=31] QEMU: etc/e820 [size=20] QEMU: genroms/kvmvapic.bin [size=9216] QEMU: etc/system-states [size=6] QEMU: etc/acpi/tables [size=131072] QEMU: etc/table-loader [size=4096] QEMU: etc/tpm/log [size=0] QEMU: etc/acpi/rsdp [size=36] QEMU: bootorder [size=0] QEMU: e820/ram: 0x00000000 +0x08000000 QEMU: reserve ioports 0x0510-0x0511 [firmware-config] QEMU: reserve ioports 0x5658-0x5658 [vmware-port] QEMU: reserve ioports 0xae00-0xae0f [pci-hotplug] QEMU: reserve ioports 0xaf00-0xaf1f [cpu-hotplug] QEMU: reserve ioports 0xafe0-0xafe3 [piix4-gpe0] QEMU: reserve ioports 0x00e9-0x00e9 [debugcon] DOMAIN: 0000 read_resources bus 0 link: 0 DOMAIN: 0000 read_resources bus 0 link: 0 done Root Device read_resources bus 0 link: 0 done Done reading resources. Show resources in subtree (Root Device)...After reading. Root Device child on link 0 CPU_CLUSTER: 0 CPU_CLUSTER: 0 child on link 0 APIC: 00 APIC: 00 DOMAIN: 0000 child on link 0 PCI: 00:00.0 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100 DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index a DOMAIN: 0000 resource base c0000 size 7f40000 align 0 gran 0 limit 0 flags e0004200 index b DOMAIN: 0000 resource base 510 size 2 align 0 gran 0 limit ffff flags e0000100 index c DOMAIN: 0000 resource base 5658 size 1 align 0 gran 0 limit ffff flags e0000100 index d DOMAIN: 0000 resource base ae00 size 10 align 0 gran 0 limit ffff flags e0000100 index e DOMAIN: 0000 resource base af00 size 20 align 0 gran 0 limit ffff flags e0000100 index f DOMAIN: 0000 resource base afe0 size 4 align 0 gran 0 limit ffff flags e0000100 index 10 DOMAIN: 0000 resource base e9 size 1 align 0 gran 0 limit ffff flags e0000100 index 11 DOMAIN: 0000 resource base fec00000 size 100000 align 0 gran 0 limit ffffffff flags e0000200 index 2 DOMAIN: 0000 resource base fee00000 size 10000 align 0 gran 0 limit ffffffff flags e0000200 index 3 PCI: 00:00.0 PCI: 00:01.0 PCI: 00:01.0 resource base 0 size 1000 align 0 gran 0 limit ffff flags c0000100 index 1 PCI: 00:01.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags d0000200 index 2 PCI: 00:01.1 PCI: 00:01.1 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20 PCI: 00:01.3 PCI: 00:01.3 resource base e400 size 40 align 0 gran 0 limit ffff flags d0000100 index 1 PCI: 00:01.3 resource base f00 size 10 align 0 gran 0 limit ffff flags d0000100 index 2 PCI: 00:02.0 PCI: 00:02.0 resource base 0 size 1000000 align 24 gran 24 limit ffffffff flags 1200 index 10 PCI: 00:02.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 18 PCI: 00:02.0 resource base 0 size 10000 align 16 gran 16 limit ffffffff flags 2200 index 30 PCI: 00:03.0 PCI: 00:03.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 200 index 10 PCI: 00:03.0 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 index 14 PCI: 00:03.0 resource base 0 size 40000 align 18 gran 18 limit ffffffff flags 2200 index 30 DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff PCI: 00:03.0 14 * [0x0 - 0x3f] io PCI: 00:01.1 20 * [0x40 - 0x4f] io DOMAIN: 0000 io: base: 50 size: 50 align: 6 gran: 0 limit: ffff done DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff PCI: 00:02.0 10 * [0x0 - 0xffffff] prefmem PCI: 00:03.0 30 * [0x1000000 - 0x103ffff] mem PCI: 00:03.0 10 * [0x1040000 - 0x105ffff] mem PCI: 00:02.0 30 * [0x1060000 - 0x106ffff] mem PCI: 00:02.0 18 * [0x1070000 - 0x1070fff] mem DOMAIN: 0000 mem: base: 1071000 size: 1071000 align: 24 gran: 0 limit: ffffffff done avoid_fixed_resources: DOMAIN: 0000 avoid_fixed_resources:@DOMAIN: 0000 10000000 limit 0000ffff avoid_fixed_resources:@DOMAIN: 0000 10000100 limit ffffffff constrain_resources: DOMAIN: 0000 0a base 00000000 limit 0009ffff mem (fixed) constrain_resources: DOMAIN: 0000 0b base 000c0000 limit 07ffffff mem (fixed) constrain_resources: DOMAIN: 0000 0c base 00000510 limit 00000511 io (fixed) constrain_resources: DOMAIN: 0000 0d base 00005658 limit 00005658 io (fixed) constrain_resources: DOMAIN: 0000 0e base 0000ae00 limit 0000ae0f io (fixed) constrain_resources: DOMAIN: 0000 02 base fec00000 limit fecfffff mem (fixed) avoid_fixed_resources:@DOMAIN: 0000 10000000 base 00005659 limit 0000adff avoid_fixed_resources:@DOMAIN: 0000 10000100 base fd000000 limit febfffff Setting resources... DOMAIN: 0000 io: base:5659 size:50 align:6 gran:0 limit:adff PCI: 00:03.0 14 * [0x5800 - 0x583f] io PCI: 00:01.1 20 * [0x5840 - 0x584f] io DOMAIN: 0000 io: next_base: 5850 size: 50 align: 6 gran: 0 done DOMAIN: 0000 mem: base:fd000000 size:1071000 align:24 gran:0 limit:febfffff PCI: 00:02.0 10 * [0xfd000000 - 0xfdffffff] prefmem PCI: 00:03.0 30 * [0xfe000000 - 0xfe03ffff] mem PCI: 00:03.0 10 * [0xfe040000 - 0xfe05ffff] mem PCI: 00:02.0 30 * [0xfe060000 - 0xfe06ffff] mem PCI: 00:02.0 18 * [0xfe070000 - 0xfe070fff] mem DOMAIN: 0000 mem: next_base: fe071000 size: 1071000 align: 24 gran: 0 done Root Device assign_resources, bus 0 link: 0 DOMAIN: 0000 assign_resources, bus 0 link: 0 PCI: 00:01.1 20 <- [0x0000005840 - 0x000000584f] size 0x00000010 gran 0x04 io PCI: 00:02.0 10 <- [0x00fd000000 - 0x00fdffffff] size 0x01000000 gran 0x18 prefmem PCI: 00:02.0 18 <- [0x00fe070000 - 0x00fe070fff] size 0x00001000 gran 0x0c mem PCI: 00:02.0 30 <- [0x00fe060000 - 0x00fe06ffff] size 0x00010000 gran 0x10 romem PCI: 00:03.0 10 <- [0x00fe040000 - 0x00fe05ffff] size 0x00020000 gran 0x11 mem PCI: 00:03.0 14 <- [0x0000005800 - 0x000000583f] size 0x00000040 gran 0x06 io PCI: 00:03.0 30 <- [0x00fe000000 - 0x00fe03ffff] size 0x00040000 gran 0x12 romem DOMAIN: 0000 assign_resources, bus 0 link: 0 Root Device assign_resources, bus 0 link: 0 Done setting resources. Show resources in subtree (Root Device)...After assigning values. Root Device child on link 0 CPU_CLUSTER: 0 CPU_CLUSTER: 0 child on link 0 APIC: 00 APIC: 00 DOMAIN: 0000 child on link 0 PCI: 00:00.0 DOMAIN: 0000 resource base 5659 size 50 align 6 gran 0 limit adff flags 40040100 index 10000000 DOMAIN: 0000 resource base fd000000 size 1071000 align 24 gran 0 limit febfffff flags 40040200 index 10000100 DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index a DOMAIN: 0000 resource base c0000 size 7f40000 align 0 gran 0 limit 0 flags e0004200 index b DOMAIN: 0000 resource base 510 size 2 align 0 gran 0 limit ffff flags e0000100 index c DOMAIN: 0000 resource base 5658 size 1 align 0 gran 0 limit ffff flags e0000100 index d DOMAIN: 0000 resource base ae00 size 10 align 0 gran 0 limit ffff flags e0000100 index e DOMAIN: 0000 resource base af00 size 20 align 0 gran 0 limit ffff flags e0000100 index f DOMAIN: 0000 resource base afe0 size 4 align 0 gran 0 limit ffff flags e0000100 index 10 DOMAIN: 0000 resource base e9 size 1 align 0 gran 0 limit ffff flags e0000100 index 11 DOMAIN: 0000 resource base fec00000 size 100000 align 0 gran 0 limit ffffffff flags e0000200 index 2 DOMAIN: 0000 resource base fee00000 size 10000 align 0 gran 0 limit ffffffff flags e0000200 index 3 PCI: 00:00.0 PCI: 00:01.0 PCI: 00:01.0 resource base 0 size 1000 align 0 gran 0 limit ffff flags c0000100 index 1 PCI: 00:01.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags d0000200 index 2 PCI: 00:01.1 PCI: 00:01.1 resource base 5840 size 10 align 4 gran 4 limit 584f flags 60000100 index 20 PCI: 00:01.3 PCI: 00:01.3 resource base e400 size 40 align 0 gran 0 limit ffff flags d0000100 index 1 PCI: 00:01.3 resource base f00 size 10 align 0 gran 0 limit ffff flags d0000100 index 2 PCI: 00:02.0 PCI: 00:02.0 resource base fd000000 size 1000000 align 24 gran 24 limit fdffffff flags 60001200 index 10 PCI: 00:02.0 resource base fe070000 size 1000 align 12 gran 12 limit fe070fff flags 60000200 index 18 PCI: 00:02.0 resource base fe060000 size 10000 align 16 gran 16 limit fe06ffff flags 60002200 index 30 PCI: 00:03.0 PCI: 00:03.0 resource base fe040000 size 20000 align 17 gran 17 limit fe05ffff flags 60000200 index 10 PCI: 00:03.0 resource base 5800 size 40 align 6 gran 6 limit 583f flags 60000100 index 14 PCI: 00:03.0 resource base fe000000 size 40000 align 18 gran 18 limit fe03ffff flags 60002200 index 30 Done allocating resources. Enabling resources... PCI: 00:00.0 cmd <- 00 PCI: 00:01.0 cmd <- 00 PCI: 00:01.1 cmd <- 01 PCI: 00:01.3 cmd <- 00 PCI: 00:02.0 cmd <- 03 PCI: 00:03.0 cmd <- 03 done. Initializing devices... Root Device init ... CPU_CLUSTER: 0 init ... Initializing CPU #0 CPU: vendor Intel device 663 CPU: family 06, model 06, stepping 03 CPU #0 initialized PCI: 00:00.0 init ... Keyboard init... Assigning IRQ 10 to 0:1.3 Assigning IRQ 11 to 0:3.0 PCI: 00:01.0 init ... RTC Init PCI: 00:01.1 init ... IDE: Primary IDE interface: on IDE: Secondary IDE interface: on IDE: Access to legacy IDE ports: off PCI: 00:02.0 init ... PCI: 00:03.0 init ... Devices initialized Show all devs... After init. Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 DOMAIN: 0000: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:01.0: enabled 1 PCI: 00:01.1: enabled 1 PCI: 00:01.3: enabled 1 PCI: 00:02.0: enabled 1 PCI: 00:03.0: enabled 1 CPU: 00: enabled 1 Finalize devices... Devices finalized Copying Interrupt Routing Table to 0x000f0000... done. Copying Interrupt Routing Table to 0x07fdc000... done. PIRQ table: 128 bytes. QEMU: found acpi tables in fw_cfg. QEMU: loading "etc/acpi/rsdp" to 0x7fb8000 (len 36) QEMU: loading "etc/acpi/tables" to 0x7fb8040 (len 131072) QEMU: loaded acpi tables from fw_cfg. ACPI tables: 131136 bytes. smbios_write_tables: 07fb7000 Root Device (Emulation QEMU x86 i440fx/piix4) CPU_CLUSTER: 0 (QEMU Northbridge i440fx) APIC: 00 (unknown) DOMAIN: 0000 (QEMU Northbridge i440fx) QEMU: found smbios tables in fw_cfg (len 320). QEMU: coreboot type0 table found at 0x7fb7020. QEMU: loading smbios tables to 0x7fb705e PCI: 00:00.0 (QEMU Northbridge i440fx) PCI: 00:01.0 (Intel 82371FB/SB/MX/AB/EB/MB Southbridge) PCI: 00:01.1 (Intel 82371FB/SB/MX/AB/EB/MB Southbridge) PCI: 00:01.3 (Intel 82371FB/SB/MX/AB/EB/MB Southbridge) PCI: 00:02.0 (unknown) PCI: 00:03.0 (unknown) CPU: 00 (unknown) SMBIOS tables: 414 bytes. Writing table forward entry at 0x00000500 Wrote coreboot table at: 00000500, 0x10 bytes, checksum 7e4 Table forward entry ends at 0x00000528. ... aligned to 0x00001000 Writing coreboot table at 0x07faf000 rom_table_end = 0x07faf000 ... aligned to 0x07fb0000 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES 1. 0000000000001000-000000000009ffff: RAM 2. 00000000000c0000-0000000007faefff: RAM 3. 0000000007faf000-0000000007ffffff: CONFIGURATION TABLES 4. 00000000ff800000-00000000ffffffff: RESERVED CBFS @ 0 size 3fc40 No FMAP found at 0 offset. Wrote coreboot table at: 07faf000, 0x174 bytes, checksum bb5 coreboot table: 396 bytes. IMD ROOT 0. 07fff000 00001000 IMD SMALL 1. 07ffe000 00001000 CONSOLE 2. 07fde000 00020000 TIME STAMP 3. 07fdd000 000002e0 IRQ TABLE 4. 07fdc000 00001000 ACPI 5. 07fb8000 00024000 SMBIOS 6. 07fb7000 00000800 COREBOOT 7. 07faf000 00008000 IMD small region: IMD ROOT 0. 07ffec00 00000400 CAR GLOBALS 1. 07ffeae0 0000010c ROMSTAGE 2. 07ffeac0 00000004 GDT 3. 07ffe8c0 00000200 CBFS provider active. CBFS @ 0 size 3fc40 CBFS: Locating 'fallback/payload' CBFS: Found @ offset ec40 size 92bc 'fallback/payload' located at offset: ec78 size: 92bc Loading segment from rom address 0xfffcec78 code (compression=1) New segment dstaddr 0x100000 memsize 0x5ccf0 srcaddr 0xfffcecb0 filesize 0x9284 Loading segment from rom address 0xfffcec94 Entry Point 0x00100000 Bounce Buffer at 07f33000, 504348 bytes Loading Segment: addr: 0x0000000000100000 memsz: 0x000000000005ccf0 filesz: 0x0000000000009284 lb: [0x0000000000100000, 0x000000000011e52c) segment: [0x0000000000100000, 0x0000000000109284, 0x000000000015ccf0) bounce: [0x0000000007f33000, 0x0000000007f3c284, 0x0000000007f8fcf0) Post relocation: addr: 0x0000000007f33000 memsz: 0x000000000005ccf0 filesz: 0x0000000000009284 using LZMA [ 0x07f33000, 07f470bc, 0x07f8fcf0) <- fffcecb0 Clearing Segment: addr: 0x0000000007f470bc memsz: 0x0000000000048c34 dest 07f33000, end 07f8fcf0, bouncebuffer 7f33000 move suffix around: from 7f5152c, to 11e52c, amount: 3e7c4 Loaded segments Jumping to boot code at 00100000(07faf000) CPU0: stack: 00115000 - 00116000, lowest used address 00115c14, stack used: 1004 bytes entry = 0x00100000 lb_start = 0x00100000 lb_size = 0x0001e52c buffer = 0x07f33000 qemu: fatal: Trying to execute code outside RAM or ROM at 0xf82ba69c EAX=f82ba69c EBX=07f67454 ECX=00000000 EDX=ffffff12 ESI=07f6fa58 EDI=0011e52c EBP=00100000 ESP=00115f2c EIP=f82ba69c EFL=00000097 [--S-APC] CPL=0 II=0 A20=1 SMM=0 HLT=0 ES =0018 00000000 ffffffff 00cf9300 DPL=0 DS [-WA] CS =0010 00000000 ffffffff 00cf9b00 DPL=0 CS32 [-RA] SS =0018 00000000 ffffffff 00cf9300 DPL=0 DS [-WA] DS =0018 00000000 ffffffff 00cf9300 DPL=0 DS [-WA] FS =0018 00000000 ffffffff 00cf9300 DPL=0 DS [-WA] GS =0018 00000000 ffffffff 00cf9300 DPL=0 DS [-WA] LDT=0000 00000000 0000ffff 00008200 DPL=0 LDT TR =0000 00000000 0000ffff 00008b00 DPL=0 TSS32-busy GDT= 07ffe8c0 00000047 IDT= 00113cd0 0000009f CR0=60000011 CR2=00000000 CR3=00000000 CR4=00000000 DR0=00000000 DR1=00000000 DR2=00000000 DR3=00000000 DR6=ffff0ff0 DR7=00000400 CCS=07e5152c CCD=f82ba69c CCO=SUBL EFER=0000000000000000 FCW=037f FSW=0000 [ST=0] FTW=00 MXCSR=00001f80 FPR0=0000000000000000 0000 FPR1=0000000000000000 0000 FPR2=0000000000000000 0000 FPR3=0000000000000000 0000 FPR4=0000000000000000 0000 FPR5=0000000000000000 0000 FPR6=0000000000000000 0000 FPR7=0000000000000000 0000 XMM00=00000000000000000000000000000000 XMM01=00000000000000000000000000000000 XMM02=00000000000000000000000000000000 XMM03=00000000000000000000000000000000 XMM04=00000000000000000000000000000000 XMM05=00000000000000000000000000000000 XMM06=00000000000000000000000000000000 XMM07=00000000000000000000000000000000 Abgebrochen (Speicherabzug geschrieben) ``` Thanks, Paul

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USB data write failure
by Autoboot 11 Aug '15

11 Aug '15

Hello, running autoboot with coreboot as of commit a3e41c089602c58409e8dfd4aceecbdd7d4f4a5b being the latest not breaking USB and PCI-E on my ThinkPad X201. Writing data to USB storage appears bugged. I tested this using different disks on three different machines: - ThinkPad X201, autoboot, latest Parabola - ThinkPad T43, stock firmware, Debian 8 - Asus EeePC 901, stock firmware, latest Arch In all combinations, I created a btrfs filesystem inside a LUKS container on the whole disk, using both USB and internal SATA (except for the 901): $ crytpsetup luksFormat /dev/sdb $ cryptsetup open /dev/sdb test $ mkfs.btrfs /dev/mapper/test $ mount -o compress=lzo /dev/mapper/test /mnt $ dd if=/dev/urandom of=/mnt/20M bs=1M count=20 iflag=fullblock $ umount /mnt $ btrfs check /dev/mapper/test Only when using my X201 *with coreboot and USB*, this procedure resulted in the following error: $ btrfs check /dev/mapper/test Checking filesystem on /dev/mapper/test UUID: 33c88ec2-2c4e-4844-905f-c0fbebc00a1f checking extents bad metadata [29605888, 29622272) crossing stripe boundary bad metadata [29736960, 29753344) crossing stripe boundary Errors found in extent allocation tree or chunk allocation checking free space cache checking fs roots checking csums checking root refs found 21135362 bytes used err is 0 total csum bytes: 20480 total tree bytes: 163840 total fs tree bytes: 32768 total extent tree bytes: 16384 btree space waste bytes: 129312 file data blocks allocated: 21495808 referenced 21495808 btrfs-progs v4.1.2-32-g6054018 Using the same disk with my internal SATA port and testing from a live USB stick showed no errors at all. Every other setup worked fine and didn't show any error either. I also tested this with ext4, but as expected, with ext4 everything seems to be ok since it doesn't even provide this type of error detection. This clearly seems to be a coreboot related issue. I used to run the latest coreboot with autoboot, but booting from USB somehow didn't work and someone in #coreboot told me USB an PCI-E was broken as of commit 456f495d, so I reset to the above mentioned. USB boot worked again, but then I noticed this faulty behaviour. I attached the coreboot config used to build my current autoboot image with. Hopefully this report is useful to find the bug and eventually fix it asap.

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PciExpressGraphics on Intel Sandybridge
by Patrick Rudolph 11 Aug '15

11 Aug '15

Hello, I'm currently working on enabling PEG and run into some trouble. With pending patches [1] applied, I was able to activate the Nvidia GPU. The system hangs at Seabios/Grub2 with 2 GPUs enabled at the same time. As I'm using the EHCI Debug Port I don't have any Seabios console output. Is there EHCI Debug Port support available ? My first guess is some VGA IO ranges are overlapping. Any ideas whats wrong ? Do I need to provide two VBIOS blobs ? At the moment it is only possible to provide one (using make menuconfig). The ACPI code "parses" the IGD VBIOS, do I need to add similar code for PEG ? It looks like to best idea is to disable one GPU depending on a user setting. I would like to see a new define: PREFER_PEG_OVER_IGD If set and PEG and IGD are found, IGD is disabled. If unset and PEG and IGD are found, PEG is disabled. Some UEFI allows to run both GPUs. Running multiple GPUs at the same time seems to be possible, but requires additional testing. Regards, Patrick [1] http://review.coreboot.org/#/c/11058/ http://review.coreboot.org/#/c/11059/

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Re: [coreboot] noob question
by Johan S 11 Aug '15

11 Aug '15

I ve deleted the whole tree made crossgcc , choose qemu and get here : build/device/oprom/realmode/x86.ramstage.o: In function `vbe_mode_info_valid': /home/johan/coreboot/src/device/oprom/realmode/x86.c:226: multiple definition of `vbe_mode_info_valid' build/lib/edid.ramstage.o:/home/johan/coreboot/src/lib/edid.c:1495: first defined here build/device/oprom/realmode/x86.ramstage.o: In function `fill_lb_framebuffer': x86.c:(.text.fill_lb_framebuffer+0x0): multiple definition of `fill_lb_framebuffer' build/lib/edid.ramstage.o:edid.c:(.text.fill_lb_framebuffer+0x0): first defined here make: *** [build/generated/ramstage.o] Error 1 can't figure what is happening ... > can you share the coreboot serial log with community? > > I used to have a splash on my system, sometime I have to use a new splash > file if the original one does not show up correctly. > > On Mon, Aug 10, 2015 at 1:04 PM, Johan S <johanpsz(a)yahoo.fr> wrote: > > > Hi there, > > i m trying to understand few mechanism in coreboot can someone help ? > > I grabbed the git tree , made crossgcc , made a biosfile tested > > succesfully within qemu. > > In the menuconfig few options are quite confusing especially looking at > > the vgabios . > > I choose the oldest qemu model for emulation , enabled the vgabios , kept > > the vesa framebuffer > > did the edid patch to bypasse vbe mod multiple ... > > but i can't get my splashscreen :-/ > > > > johan@debian:~/coreboot$ file build/coreboot.rom ^C > > johan@debian:~/coreboot$ build/cbfstool build/coreboot.rom print > > coreboot.rom: 4096 kB, bootblocksize 928, romsize 4194304, offset 0x3c0000 > > alignment: 64 bytes, architecture: x86 > > > > Name Offset Type Size > > bootsplash.jpg 0x3c0000 bootsplash 50937 > > cmos_layout.bin 0x3cc740 cmos_layout 808 > > fallback/dsdt.aml 0x3ccac0 raw 4000 > > config 0x3cdac0 raw 3459 > > revision 0x3ce880 raw 569 > > (empty) 0x3ceb00 null 5208 > > fallback/romstage 0x3cff80 stage 11468 > > fallback/ramstage 0x3d2cc0 stage 46007 > > fallback/payload 0x3de0c0 payload 55823 > > vgaroms/seavgabios.bin 0x3ebb40 raw 35840 > > (empty) 0x3f4780 null 46232 > > > > I read somewhere that in vgabios i should be able to see : > > > > under "VGA ROM ---> VGA Hardware Type" select "coreboot linear framebuffer" > > > > > > Anyway i can get my os to boot , i can pass the F12 boot option , i can > > pass openfirmware but ... > > i can't even understand why with all requirement in the biosfile i could't > > get 1024*768 > > jpeg displayed with vesa enabled ... > > I 'm lost > > Thanks > > > > > > -- > > Johan S <johanpsz(a)yahoo.fr> > > > > -- > > coreboot mailing list: coreboot(a)coreboot.org > > http://www.coreboot.org/mailman/listinfo/coreboot > > -- Johan S <johanpsz(a)yahoo.fr>

1 0

Re: [coreboot] noob question
by Johan S 11 Aug '15

11 Aug '15

So here is the output of coreboot , no splash even with "-vga std" option passed to qemu ... I made a splash in lower res (800*600) johan@debian:~/coreboot$ make Created CBFS (capacity = 261144 bytes) GEN generated/romstage.ld LINK cbfs/fallback/romstage.debug OBJCOPY cbfs/fallback/romstage.elf CBFS coreboot.pre CBFS coreboot.rom PAYLOAD payloads/external/SeaBIOS/seabios/out/bios.bin.elf (compression: LZMA) SeaBIOS Adding generated legacy VGA option rom. CONFIG .config REVISION build.h CBFSPRINT coreboot.rom coreboot.rom: 4096 kB, bootblocksize 928, romsize 4194304, offset 0x3c0000 alignment: 64 bytes, architecture: x86 Name Offset Type Size bootsplash.jpg 0x3c0000 bootsplash 34070 cmos_layout.bin 0x3c8540 cmos_layout 808 fallback/dsdt.aml 0x3c88c0 raw 4000 fallback/romstage 0x3c98c0 stage 11464 fallback/ramstage 0x3cc5c0 stage 46007 fallback/payload 0x3d79c0 payload 55823 vgaroms/seavgabios.bin 0x3e5440 raw 35840 config 0x3ee080 raw 3459 revision 0x3eee40 raw 569 (empty) 0x3ef0c0 null 68440 Thanks > can you share the coreboot serial log with community? > > I used to have a splash on my system, sometime I have to use a new splash > file if the original one does not show up correctly. > > On Mon, Aug 10, 2015 at 1:04 PM, Johan S <johanpsz(a)yahoo.fr> wrote: > > > Hi there, > > i m trying to understand few mechanism in coreboot can someone help ? > > I grabbed the git tree , made crossgcc , made a biosfile tested > > succesfully within qemu. > > In the menuconfig few options are quite confusing especially looking at > > the vgabios . > > I choose the oldest qemu model for emulation , enabled the vgabios , kept > > the vesa framebuffer > > did the edid patch to bypasse vbe mod multiple ... > > but i can't get my splashscreen :-/ > > > > johan@debian:~/coreboot$ file build/coreboot.rom ^C > > johan@debian:~/coreboot$ build/cbfstool build/coreboot.rom print > > coreboot.rom: 4096 kB, bootblocksize 928, romsize 4194304, offset 0x3c0000 > > alignment: 64 bytes, architecture: x86 > > > > Name Offset Type Size > > bootsplash.jpg 0x3c0000 bootsplash 50937 > > cmos_layout.bin 0x3cc740 cmos_layout 808 > > fallback/dsdt.aml 0x3ccac0 raw 4000 > > config 0x3cdac0 raw 3459 > > revision 0x3ce880 raw 569 > > (empty) 0x3ceb00 null 5208 > > fallback/romstage 0x3cff80 stage 11468 > > fallback/ramstage 0x3d2cc0 stage 46007 > > fallback/payload 0x3de0c0 payload 55823 > > vgaroms/seavgabios.bin 0x3ebb40 raw 35840 > > (empty) 0x3f4780 null 46232 > > > > I read somewhere that in vgabios i should be able to see : > > > > under "VGA ROM ---> VGA Hardware Type" select "coreboot linear framebuffer" > > > > > > Anyway i can get my os to boot , i can pass the F12 boot option , i can > > pass openfirmware but ... > > i can't even understand why with all requirement in the biosfile i could't > > get 1024*768 > > jpeg displayed with vesa enabled ... > > I 'm lost > > Thanks > > > > > > -- > > Johan S <johanpsz(a)yahoo.fr> > > > > -- > > coreboot mailing list: coreboot(a)coreboot.org > > http://www.coreboot.org/mailman/listinfo/coreboot > > -- Johan S <johanpsz(a)yahoo.fr>

1 0

noob question
by Johan S 10 Aug '15

10 Aug '15

Hi there, i m trying to understand few mechanism in coreboot can someone help ? I grabbed the git tree , made crossgcc , made a biosfile tested succesfully within qemu. In the menuconfig few options are quite confusing especially looking at the vgabios . I choose the oldest qemu model for emulation , enabled the vgabios , kept the vesa framebuffer did the edid patch to bypasse vbe mod multiple ... but i can't get my splashscreen :-/ johan@debian:~/coreboot$ file build/coreboot.rom ^C johan@debian:~/coreboot$ build/cbfstool build/coreboot.rom print coreboot.rom: 4096 kB, bootblocksize 928, romsize 4194304, offset 0x3c0000 alignment: 64 bytes, architecture: x86 Name Offset Type Size bootsplash.jpg 0x3c0000 bootsplash 50937 cmos_layout.bin 0x3cc740 cmos_layout 808 fallback/dsdt.aml 0x3ccac0 raw 4000 config 0x3cdac0 raw 3459 revision 0x3ce880 raw 569 (empty) 0x3ceb00 null 5208 fallback/romstage 0x3cff80 stage 11468 fallback/ramstage 0x3d2cc0 stage 46007 fallback/payload 0x3de0c0 payload 55823 vgaroms/seavgabios.bin 0x3ebb40 raw 35840 (empty) 0x3f4780 null 46232 I read somewhere that in vgabios i should be able to see : under "VGA ROM ---> VGA Hardware Type" select "coreboot linear framebuffer" Anyway i can get my os to boot , i can pass the F12 boot option , i can pass openfirmware but ... i can't even understand why with all requirement in the biosfile i could't get 1024*768 jpeg displayed with vesa enabled ... I 'm lost Thanks -- Johan S <johanpsz(a)yahoo.fr>

2 1

noob question
by Johan S 10 Aug '15

10 Aug '15

2 1

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coreboot August 2015