coreboot August 2015

coreboot@coreboot.org

45 participants
86 discussions

End user flash tool - Adding new working configurations and testing

by Łukasz Dmitrowski

Hello, I am looking for people who want to help with testing automatic building of coreboot rom(and other features) with end user flash tool. To make automatic building possible for your machines first I need to prepare a configuration for particular hardware set(s). Until tomorrow I will provide a pdf with description of application features, building process and rest of details.For now best source of info about the app is here: http://blogs.coreboot.org/blog/author/dmitro/ If someone wants to help with testing (and also making a list of working configurations bigger) please contact me and send: * lspci -nn output * cat /sys/class/drm/card0-LVDS-1/edid | edid-decode * dmidecode –t 2 * short description of how you normally proceed with building image for your system (important or unusual steps), are additional option roms or other kinds of action needed? * if it needs factory VGABIOS, which one is working – extracted from memory or extracted from factory BIOS rom? please also attach needed file(s) * coreboot .config file with your configuration Thanks in advance for help! Regards, Lukasz Dmitrowski

4 years, 11 months

[Mohon Peak] Memtest86+

by Patrick Agrain

Hello, I try to perform some memory test on the Mohon Peak CRB with memtest86+. I downloaded memtest86+ v5.01 and compile it. So far, so good. Following the thread: http://www.coreboot.org/pipermail/coreboot/2015-January/079143.html concerning this topic, I modified the given values, so that now: [root@localhost memtest86+-5.01]# readelf -e memtest1modified ELF Header: Magic: 7f 45 4c 46 01 01 01 00 00 00 00 00 00 00 00 00 Class: ELF32 Data: 2's complement, little endian Version: 1 (current) OS/ABI: UNIX - System V ABI Version: 0 Type: EXEC (Executable file) Machine: Intel 80386 Version: 0x1 Entry point address: 0x10000 Start of program headers: 52 (bytes into file) Start of section headers: 151580 (bytes into file) Flags: 0x0 Size of this header: 52 (bytes) Size of program headers: 32 (bytes) Number of program headers: 1 Size of section headers: 40 (bytes) Number of section headers: 3 Section header string table index: 2 Section Headers: [Nr] Name Type Addr Off Size ES Flg Lk Inf Al [ 0] NULL 00000000 000000 000000 00 0 0 0 [ 1] .data PROGBITS 00010000 001000 024008 00 WA 0 0 1 [ 2] .shstrtab STRTAB 00000000 025008 000011 00 0 0 1 Key to Flags: W (write), A (alloc), X (execute), M (merge), S (strings) I (info), L (link order), G (group), x (unknown) O (extra OS processing required) o (OS specific), p (processor specific) Program Headers: Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align LOAD 0x010000 0x00010000 0x00010000 0x24008 0x24008 RW 0x200000 Section to Segment mapping: Segment Sections... 00 .shstrtab [root@localhost memtest86+-5.01]# What gives the same scheme as in the previously mentionned thread. Now the logs of the booting Mohon Peak (from begin of Seabios): SeaBIOS (version rel-1.8.0-12-ga1ac886-dirty-20150402_003540-localhost.localdomain) init usb EHCI init on dev 00:16.0 (regs=0xdfe89420) set_address 0x7fd41b80 config_usb: 0x7fd41a50 device rev=0200 cls=09 sub=00 proto=01 size=64 init serial Found 2 legacy serial ports init hard drives init ahci AHCI controller at 17.0, iobase dfe88000, irq 15 AHCI: cap 0xc720ff03, ports_impl 0x0 AHCI controller at 18.0, iobase dfe88800, irq 0 AHCI: cap 0xc3309f01, ports_impl 0x1 AHCI/0: probing AHCI/0: link up AHCI/0: ... finished, status 0x51, ERROR 0x4 Searching bootorder for: /pci@i0cf8/*@18/drive@0/disk@0 AHCI/0: registering: "AHCI/0: ST500DM002-1BD142 ATA-8 Hard-Disk (465 GiBytes)" Registering bootable: AHCI/0: ST500DM002-1BD142 ATA-8 Hard-Disk (465 GiBytes) (type:2 prio:103 data:f3ef0) Searching bootorder for: /rom@img/Memtest86+ Registering bootable: Payload [Memtest86+] (type:32 prio:9999 data:ffe23240) Scan for option roms Attempting to init PCI bdf 00:00.0 (vd 8086:1f08) Attempting to init PCI bdf 00:01.0 (vd 8086:1f10) Attempting to init PCI bdf 00:03.0 (vd 8086:1f12) Attempting to init PCI bdf 00:0e.0 (vd 8086:1f14) Attempting to init PCI bdf 00:0f.0 (vd 8086:1f16) Attempting to init PCI bdf 00:13.0 (vd 8086:1f15) Attempting to init PCI bdf 00:14.0 (vd 8086:1f41) Attempting to init PCI bdf 00:14.1 (vd 8086:1f41) Attempting to init PCI bdf 00:16.0 (vd 8086:1f2c) Attempting to init PCI bdf 00:17.0 (vd 8086:1f22) Attempting to init PCI bdf 00:18.0 (vd 8086:1f32) Attempting to init PCI bdf 00:1f.0 (vd 8086:1f38) Attempting to init PCI bdf 00:1f.3 (vd 8086:1f3c) Attempting to init PCI bdf 01:00.0 (vd 1415:c158) Attempting to init PCI bdf 02:00.0 (vd 10b5:8624) Attempting to init PCI bdf 03:04.0 (vd 10b5:8624) Attempting to init PCI bdf 03:05.0 (vd 10b5:8624) Attempting to init PCI bdf 03:08.0 (vd 10b5:8624) Attempting to init PCI bdf 05:00.0 (vd 8086:1528) Attempting to init PCI bdf 05:00.1 (vd 8086:1528) Press ESC for boot menu. Select boot device: 1. AHCI/0: ST500DM002-1BD142 ATA-8 Hard-Disk (465 GiBytes) 2. Payload [Memtest86+] Searching bootorder for: HALT Mapping hd drive 0x000f3ef0 to 0 drive 0x000f3ef0: PCHS=16383/16/63 translation=lba LCHS=1024/255/63 s=976773168 finalize PMM malloc finalize Space available for UMB: c1000-ee800, f0000-f3ef0 Returned 258048 bytes of ZoneHigh e820 map has 8 items: 0: 0000000000000000 - 000000000009f800 = 1 RAM 1: 000000000009f800 - 00000000000a0000 = 2 RESERVED 2: 00000000000f0000 - 0000000000100000 = 2 RESERVED 3: 0000000000100000 - 000000007fd89000 = 1 RAM 4: 000000007fd89000 - 000000007fe00000 = 2 RESERVED 5: 00000000e0000000 - 00000000f0000000 = 2 RESERVED 6: 00000000fee00000 - 00000000fee01000 = 2 RESERVED 7: 0000000100000000 - 0000000180000000 = 1 RAM Jump to int19 enter handle_19: NULL Booting from CBFS... Run img/Memtest86+ Segment 464c457f 16777216@0xffe23268 -> 256@0x02000300 No support for compression type 10101 enter handle_18: NULL Booting from 0000:7c00 GRUB Loading stage2. Output on the SERIAL line.. enter handle_12: a=00000000 b=00000000 c=00000000 d=00000080 ds=0000 es=0000 ss=0000 si=0000811e di=00028da8 bp=00001ff0 sp=00001ff4 cs=0000 ip=8a82 f=0297 no switch back. GRUB version 0.5.96 (638K lower / 2093604K upper memory) +-------------------------------------------------------------------------+ | Boot GNU/Linux [ll-ttyS1-115K2] | | Boot GNU/Linux [xx-ttyS1-115K2] | | Boot GNU/Linux [xx-ttyS1-115K2] | | Boot GNU/Linux [default] | | Install GRUB into the hard disk | | | | | | | | | | | | | | | +-------------------------------------------------------------------------+ Use the ^ and v keys to select which entry is highlighted. Press enter to boot the selected OS, 'e' to edit the commands before booting, or 'c' for a command-line. After pressing 'ESC' and select '2', I'm not able to boot memtest86+, and fall back to the hard drive. Has anyone already faced this behavior. Thanks in advance. Best regards, Patrick Agrain

4 years, 11 months

Seabios / Coreboot / splash

by Johan S

Hi all, Yet i can't get a splash i almost certain having done things right: johan@debian:~/coreboot$ strings build/coreboot.rom |grep -i splash (bootsplash.jpg johan@debian:~/coreboot$ strings build/coreboot.rom |grep -i vga VGA_ 8vgaroms/seavgabios.bin SeaVGABIOS: x86emu leal trap! vga_post set VGA mode %x Start SeaVGABIOS (version %s) coreboot vga init Attempting to allocate VGA stack via pmm call to %04x:%04x VGA stack allocated at %x Failed to initialize VGA hardware. Exiting. johan@debian:~/coreboot$ build/cbfstool build/coreboot.rom print coreboot.rom: 8192 kB, bootblocksize 928, romsize 8388608, offset 0x0 alignment: 64 bytes, architecture: x86 Name Offset Type Size cmos_layout.bin 0x0 cmos_layout 808 fallback/dsdt.aml 0x380 raw 4000 fallback/romstage 0x1380 stage 11288 fallback/ramstage 0x4000 stage 38472 fallback/payload 0xd680 payload 55071 vgaroms/seavgabios.bin 0x1ae00 raw 26112 config 0x21440 raw 414 revision 0x21640 raw 575 bootsplash.jpg 0x218c0 raw 47125 (empty) 0x2d100 null 8203032 johan@debian:~/coreboot$ identify /home/johan/bootsplash2.jpg /home/johan/bootsplash2.jpg JPEG 800x768 800x768+0+0 8-bit sRGB 47.1KB 0.000u 0:00.019 As a result i get a screen @1024*768 , displaying press F12 ... but no splash Can't figure why ... Can someone give me pointers ? Thanks -- Johan S <johanpsz(a)yahoo.fr>

4 years, 11 months

New on blogs.coreboot.org: [GSoC] End user flash tool – week #10 #11#12

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4 years, 11 months

Lenovo T60 - Intel graphics with unsupported display panel - black screen

by Łukasz Dmitrowski

Hello, I am trying to run coreboot with seabios payload on Lenovo T60: Graphic: Intel Corporation Mobile 945GM/GMS, 943/940GML Express Integrated Graphics Controller [8086:27a2] (rev 03) Display panel: LTN141XA-L01 So, graphic is Intel, but display panel LTN141XA-L01 is not supported for native graphics initialization. I dumped VGABIOS from memory and attached it to the ROM file: ./cbfstool coreboot.rom add -f vgabios_from_mem.bin -n pci8086,27a2.rom -t raw ./cbfstool coreboot.rom add-int -i 0 -n etc/optionroms-checksum Unfortunately after powering on - screen is black. Did I miss something? -------------------------------- VGABIOS which I use: Image 1: PCI Expansion ROM Header: Signature: 0x55aa (Ok) CPU unique data: 0x75 0xe9 0xa9 0xe3 0x30 0x30 0x30 0x30 0x30 0x30 0x30 0x30 0x30 0x30 0x30 0x30 Pointer to PCI Data Structure: 0x0040 PCI Data Structure: Signature: 0x50434952 'PCIR' (Ok) Vendor ID: 0x8086 Device ID: 0x27a2 Vital Product Data: 0x0000 PCI Data Structure Length: 0x0018 (24 bytes) PCI Data Structure Revision: 0x00 Class Code: 0x030000 (VGA Display controller) Image Length: 0x0080 blocks (65536 bytes) Revision Level of Code/Data: 0x0000 Code Type: 0x00 (Intel x86) Last-Image Flag: 0x80 (last image in rom) Reserved: 0x0000 Platform specific data for x86 compliant option rom: Initialization Size: 0x75 (59904 bytes) Entry point for INIT function: 0xe3af ----------------------------------- ROM contents: cmos.default 0x0 cmos_default 256 cmos_layout.bin 0x140 cmos_layout 1824 fallback/dsdt.aml 0x8c0 raw 12037 fallback/romstage 0x3800 stage 36472 fallback/ramstage 0xc6c0 stage 53914 fallback/payload 0x199c0 payload 55825 etc/ps2-keyboard-spinup 0x27440 raw 8 config 0x27480 raw 82 revision 0x27500 raw 569 etc/optionroms-checksum 0x27780 raw 8 pci8086,27a2.rom 0x277c0 raw 32768 (empty) 0x2f800 null 1901528 ------------------------------------ Regards, Lukasz Dmitrowski

4 years, 11 months

Re: [coreboot] VT-d on Pixel 2015 (samus)

by fowlslegs＠riseup.net

On 2015-08-13 23:36, fowlslegs(a)riseup.net wrote: > On 2015-07-26 07:58, ron minnich wrote: >> There are so many bits, so little time. I have utterly forgotten how >> vt-d >> gets enabled. >> >> Anyway, there's two bits and a lock bit. coreboot very deliberately >> does >> nothing with any of them -- this was a design decision a few years ago >> -- >> and it leaves them in a state that you can control them. So the >> 'enable >> vt-x' part is easy and kvm will do it for you when you load the >> module, or >> you can do it with the wrmsr command (for each core! -- if you only do >> one >> core it will go badly). I will include a few other emails in this one. The first I sent to Ron Minnich only when I meant to 'reply all' to the mailing list, and the rest are excerpted from a conversation on the Xen-devel mailing list. #%&#%&#&% Sent just to Ron, reply to quoted text above #%&#%&#%& If you saw my comments about VT-x in my conversation with John Lewis, VT-x has been working correctly while running Xen via the Qubes distribution. VT-x was being activated, I assume, by Xen, since you say Coreboot modifies none of these bits. I tried quite a few search engine queries to try to find the MSR for VT-d (assuming it exists) without any luck. So, I found that on mail-archive.com you can search through the archive history of this mailing list (which, btw is a great future the on-site archives lack, and to whomever it would concern maybe you should consider adding this feature or otherwise linking to mail-archive.com). It seems IOMMU support for Intel was first added by this commit: http://review.coreboot.org/#/c/1654/. I decided to see if any of this code is still present in firmware-samus-6300.b, and it turns out it can in fact still be found at /src/arch/x86/boot/acpi.c. There is little if any modification to it. I don't really have any clue what the code itself is doing, so beyond this I'm lost. Noah #%&#%&#%& Excerpted from Xen-devel mailing list (3 partial messages) #%&#%&#%& (1) On the VT-d troubleshooting page, I was informed to shoot you all a message if Xen had to deactivate my VT-d due to errors in my BIOS (in this case Coreboot). I am running John Lewis' Coreboot ROM for the Chromebook Pixel 2 (samus) w/ the i7-5600U processor and Xen 4.4.2 on Qubes. I downloaded and cracked open (for lack of better words) John Lewis's Coreboot image (which is a modified version of the one in the Google repos) and found that src/arch/x86/acpi.c had the same section added by the http://review.coreboot.org/#/c/1654/ commit written by Patrick Georgi a few years back that is supposed to provide ACPI DMAR tables. The problem might just be the code is out of date for modern processors or maybe it has just not been tested against many CPUs. It does appear that there has been changes to this acpi.c file in the Coreboot master branch, which makes me wonder if building against that would fix my problems. Realistically though, I have barely any experience or knowledge with Coreboot hacking and I'm assuming there is a web of dependencies that I couldn't figure out without possibly months of research, trial, and error. &%#&%#&%# (2) Please reboot and use "iommu=verbose,debug" on the Xen command line, which will offer more information. ~Andrew &%#&%#&%# (3) I was already passing iommu=verbose, but not debug as well. Here is the new log Xen 4.4.2-6.fc20 (XEN) Xen version 4.4.2 (user@) (gcc (GCC) 4.8.3 20140911 (Red Hat 4.8.3-7)) debug=n Thu Jul 23 20:12:15 UTC 2015 (XEN) Latest ChangeSet: (XEN) Bootloader: GRUB 2.00 (XEN) Command line: placeholder console=none dom0_mem=min:1024M iommu=verbose,debug (XEN) Video information: (XEN) VGA is text mode 80x25, font 8x16 (XEN) Disc information: (XEN) Found 2 MBR signatures (XEN) Found 2 EDD information structures (XEN) Xen-e820 RAM map: (XEN) 0000000000000000 - 000000000009fc00 (usable) (XEN) 000000000009fc00 - 00000000000a0000 (reserved) (XEN) 00000000000f0000 - 0000000000100000 (reserved) (XEN) 0000000000100000 - 000000007ce27000 (usable) (XEN) 000000007ce27000 - 0000000080000000 (reserved) (XEN) 00000000f0000000 - 00000000f4000000 (reserved) (XEN) 00000000fed10000 - 00000000fed1a000 (reserved) (XEN) 00000000fed40000 - 00000000fed45000 (reserved) (XEN) 00000000fed80000 - 00000000fed85000 (reserved) (XEN) 0000000100000000 - 000000047f000000 (usable) (XEN) ACPI: RSDP 000F2760, 0024 (r2 CORE ) (XEN) ACPI: XSDT 7CF440E0, 004C (r1 CORE COREBOOT 0 CORE 0) (XEN) ACPI: FACP 7CF48970, 00F4 (r5 CORE COREBOOT 0 CORE 1) (XEN) ACPI: DSDT 7CF44250, 4720 (r2 COREv4 COREBOOT 20110725 INTL 20130117) (XEN) ACPI: FACS 7CF44210, 0040 (XEN) ACPI: HPET 7CF48A70, 0038 (r1 CORE COREBOOT 0 CORE 0) (XEN) ACPI: APIC 7CF48AB0, 006C (r1 CORE COREBOOT 0 CORE 0) (XEN) ACPI: MCFG 7CF48B20, 003C (r1 CORE COREBOOT 0 CORE 0) (XEN) ACPI: SSDT 7CF49BC0, 0FF8 (r2 CORE COREBOOT 2A CORE 2A) (XEN) System RAM: 16317MB (16709400kB) (XEN) Domain heap initialised (XEN) Processor #0 7:13 APIC version 21 (XEN) Processor #1 7:13 APIC version 21 (XEN) Processor #3 7:13 APIC version 21 (XEN) Processor #2 7:13 APIC version 21 (XEN) IOAPIC[0]: apic_id 2, version 32, address 0xfec00000, GSI 0-39 (XEN) Enabling APIC mode: Flat. Using 1 I/O APICs (XEN) Not enabling x2APIC: depends on iommu_supports_eim. (XEN) Using scheduler: SMP Credit Scheduler (credit) (XEN) Detected 2394.503 MHz processor. (XEN) Initing memory sharing. (XEN) xstate_init: using cntxt_size: 0x340 and states: 0x7 (XEN) I/O virtualisation disabled (XEN) Enabled directed EOI with ioapic_ack_old on! (XEN) ENABLING IO-APIC IRQs (XEN) -> Using old ACK method (XEN) Platform timer is 14.318MHz HPET (XEN) Allocated console ring of 16 KiB. (XEN) VMX: Supported advanced features: (XEN) - APIC MMIO access virtualisation (XEN) - APIC TPR shadow (XEN) - Extended Page Tables (EPT) (XEN) - Virtual-Processor Identifiers (VPID) (XEN) - Virtual NMI (XEN) - MSR direct-access bitmap (XEN) - Unrestricted Guest (XEN) HVM: ASIDs enabled. (XEN) HVM: VMX enabled (XEN) HVM: Hardware Assisted Paging (HAP) detected (XEN) HVM: HAP page sizes: 4kB, 2MB, 1GB (XEN) Brought up 4 CPUs (XEN) *** LOADING DOMAIN 0 *** (XEN) Xen kernel: 64-bit, lsb, compat32 (XEN) Dom0 kernel: 64-bit, PAE, lsb, paddr 0x1000000 -> 0x204d000 (XEN) PHYSICAL MEMORY ARRANGEMENT: (XEN) Dom0 alloc.: 0000000468000000->0000000470000000 (4056562 pages to be allocated) (XEN) Init. ramdisk: 000000047cb6a000->000000047f000000 (XEN) VIRTUAL MEMORY ARRANGEMENT: (XEN) Loaded kernel: ffffffff81000000->ffffffff8204d000 (XEN) Init. ramdisk: 0000000000000000->0000000000000000 (XEN) Phys-Mach map: ffffffff8204d000->ffffffff83f92440 (XEN) Start info: ffffffff83f93000->ffffffff83f934b4 (XEN) Page tables: ffffffff83f94000->ffffffff83fb9000 (XEN) Boot stack: ffffffff83fb9000->ffffffff83fba000 (XEN) TOTAL: ffffffff80000000->ffffffff84400000 (XEN) ENTRY ADDRESS: ffffffff81d3f1f0 (XEN) Dom0 has maximum 4 VCPUs (XEN) Scrubbing Free RAM: .done. (XEN) Initial low memory virq threshold set at 0x4000 pages. (XEN) Std. Loglevel: Errors and warnings (XEN) Guest Loglevel: Nothing (Rate-limited: Errors and warnings) (XEN) *** Serial input -> DOM0 (type 'CTRL-a' three times to switch input to Xen) (XEN) Freed 272kB init memory. (XEN) traps.c:2524:d0 Domain attempted WRMSR 00000000c0000081 from 0xe023e00800000000 to 0x0023001000000000. (XEN) traps.c:2524:d0 Domain attempted WRMSR 00000000c0000082 from 0xffff82d0802b3000 to 0xffffffff817634d0. (XEN) traps.c:2524:d0 Domain attempted WRMSR 00000000c0000083 from 0xffff82d0802b3080 to 0xffffffff817658e0. (XEN) traps.c:2524:d0 Domain attempted WRMSR 0000000000000174 from 0x000000000000e008 to 0x0000000000000010. (XEN) traps.c:2524:d0 Domain attempted WRMSR 0000000000000175 from 0xffff82d0802b7fc0 to 0x0000000000000000. (XEN) traps.c:2524:d0 Domain attempted WRMSR 0000000000000176 from 0xffff82d08021aff0 to 0xffffffff81765bf0. (XEN) traps.c:2524:d0 Domain attempted WRMSR 00000000c0000083 from 0xffff82d0802b3080 to 0xffffffff81765e30. (XEN) traps.c:2524:d0 Domain attempted WRMSR 00000000c0000084 from 0x0000000000034700 to 0x0000000000047700. (XEN) traps.c:2524:d0 Domain attempted WRMSR 00000000c0000081 from 0xe023e00800000000 to 0x0023001000000000. (XEN) traps.c:2524:d0 Domain attempted WRMSR 00000000c0000082 from 0xffff830473323000 to 0xffffffff817634d0. (XEN) Disabling non-boot CPUs ... (XEN) Broke affinity for irq 8 (XEN) Broke affinity for irq 41 (XEN) Broke affinity for irq 1 (XEN) Broke affinity for irq 6 (XEN) Broke affinity for irq 7 (XEN) Broke affinity for irq 10 (XEN) Broke affinity for irq 42 (XEN) Entering ACPI S3 state. (XEN) mce_intel.c:725: MCA Capability: BCAST 1 SER 1 CMCI 1 firstbank 0 extended MCE MSR 0 (XEN) CPU0 CMCI LVT vector (0xf1) already installed (XEN) Finishing wakeup from ACPI S3 state. (XEN) Enabling non-boot CPUs ... (XEN) printk: 26 messages suppressed. (XEN) traps.c:2524:d0 Domain attempted WRMSR 00000000c0000081 from 0xe023e00800000000 to 0x0023001000000000. (XEN) traps.c:2524:d0 Domain attempted WRMSR 00000000c0000082 from 0xffff830473323000 to 0xffffffff817634d0. (XEN) traps.c:2524:d0 Domain attempted WRMSR 00000000c0000083 from 0xffff830473323080 to 0xffffffff817658e0. (XEN) traps.c:2524:d0 Domain attempted WRMSR 0000000000000174 from 0x000000000000e008 to 0x0000000000000010. (XEN) traps.c:2524:d0 Domain attempted WRMSR 0000000000000175 from 0xffff830473327fc0 to 0x0000000000000000. (XEN) traps.c:2524:d0 Domain attempted WRMSR 0000000000000176 from 0xffff82d08021aff0 to 0xffffffff81765bf0. (XEN) traps.c:2524:d0 Domain attempted WRMSR 00000000c0000083 from 0xffff830473323080 to 0xffffffff81765e30. (XEN) traps.c:2524:d0 Domain attempted WRMSR 00000000c0000084 from 0x0000000000034700 to 0x0000000000047700. (XEN) traps.c:2524:d0 Domain attempted WRMSR 00000000c0000081 from 0xe023e00800000000 to 0x0023001000000000. (XEN) traps.c:2524:d0 Domain attempted WRMSR 00000000c0000082 from 0xffff82d0802b3000 to 0xffffffff817634d0. (XEN) Disabling non-boot CPUs ... (XEN) Broke affinity for irq 1 (XEN) Broke affinity for irq 10 (XEN) Broke affinity for irq 41 (XEN) Broke affinity for irq 42 (XEN) Entering ACPI S3 state. (XEN) mce_intel.c:725: MCA Capability: BCAST 1 SER 1 CMCI 1 firstbank 0 extended MCE MSR 0 (XEN) CPU0 CMCI LVT vector (0xf1) already installed (XEN) Finishing wakeup from ACPI S3 state. (XEN) Enabling non-boot CPUs ... #%&#%&#%&#%&#%&#%& Thanks, Noah

4 years, 11 months

[PATCH 0/4] Libflashrom

by Łukasz Dmitrowski

Hello, I improved and extended libflashrom patch, so I am posting it for a second review. I based on work of Nico Huber and Anton Kochkov. As Nico Huber's patch has been already sent some time ago I will send only Anton Kochkov's building and compilation fixes (thanks for sharing it with me) and my changes. Content: 1 / 4 - Fix libflashrom compilation (by Anton Kochkov) 2 / 4 - Fix libflashrom building (by Anton Kochkov) 3 / 4 - Added querying functions to libflashrom 4 / 4 - Added function which returns string list of multiple chips found I will be grateful for your opinions - it helps me to improve the patch. All this code you can also find here: https://github.com/lukaszdmitrowski/flashrom/tree/libflashrom Regards, Lukasz Dmitrowski

4 years, 11 months

New on blogs.coreboot.org: 2015-08-14 Librem 13: Weekly Progress Update

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4 years, 11 months

[PATCH 3/4] Libflashrom - Querying functions

by Łukasz Dmitrowski

Added querying functions Signed-off-by: Lukasz Dmitrowski <lukasz.dmitrowski(a)gmail.com> --- Makefile | 4 +- libflashrom.c | 139 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++- libflashrom.h | 40 +++++++++++++++++ 3 files changed, 180 insertions(+), 3 deletions(-) diff --git a/Makefile b/Makefile index 2c7fccd..0c97268 100644 --- a/Makefile +++ b/Makefile @@ -726,7 +726,7 @@ FEATURE_CFLAGS += $(shell LC_ALL=C grep -q "UTSNAME := yes" .features && printf # We could use PULLED_IN_LIBS, but that would be ugly. FEATURE_LIBS += $(shell LC_ALL=C grep -q "NEEDLIBZ := yes" .libdeps && printf "%s" "-lz") -LIBFLASHROM_OBJS = $(CHIP_OBJS) $(PROGRAMMER_OBJS) $(LIB_OBJS) udelay.o +LIBFLASHROM_OBJS = $(CHIP_OBJS) $(PROGRAMMER_OBJS) $(LIB_OBJS) OBJS = $(CLI_OBJS) $(LIBFLASHROM_OBJS) all: hwlibs features $(PROGRAM)$(EXEC_SUFFIX) $(PROGRAM).8 @@ -737,7 +737,7 @@ endif $(PROGRAM)$(EXEC_SUFFIX): $(OBJS) $(CC) $(LDFLAGS) -o $(PROGRAM)$(EXEC_SUFFIX) $(OBJS) $(LIBS) $(PCILIBS) $(FEATURE_LIBS) $(USBLIBS) -libflashrom.a: $(LIBFLASHROM_OBJS) +libflashrom.a: $(LIBFLASHROM_OBJS) print.o cli_common.o $(AR) rcs $@ $^ $(RANLIB) $@ diff --git a/libflashrom.c b/libflashrom.c index c96a2e9..3b94215 100644 --- a/libflashrom.c +++ b/libflashrom.c @@ -103,7 +103,144 @@ int print(const enum msglevel level, const char *const fmt, ...) * @{ */ -/* TBD */ +/** + * @brief Returns flashrom version + * @return Flashrom version + */ +const char *fl_version(void) +{ + return flashrom_version; +} + +/** + * @brief Returns a list of supported programmers + * @return List of supported programmers + */ +const char **fl_supported_programmers(void) +{ + enum programmer p = 0; + const char **supported_programmers = NULL; + + supported_programmers = malloc((PROGRAMMER_INVALID + 1) * sizeof(char*)); + if (!supported_programmers) { + msg_gerr("Out of memory!"); + } else { + for (; p < PROGRAMMER_INVALID; ++p) { + supported_programmers[p] = programmer_table[p].name; + } + supported_programmers[PROGRAMMER_INVALID] = NULL; + } + + return supported_programmers; +} + +/** + * @brief Returns list of supported flash ROM chips + * @return List of supported flash ROM chips + */ +fl_flashchip_info *fl_supported_flash_chips(void) +{ + int i = 0; + fl_flashchip_info *flashchip_info = NULL; + + flashchip_info = malloc(flashchips_size * sizeof(fl_flashchip_info)); + if (!flashchip_info) { + msg_gerr("Out of memory!"); + } else { + for (; i < flashchips_size; ++i) { + flashchip_info[i].vendor = flashchips[i].vendor; + flashchip_info[i].name = flashchips[i].name; + flashchip_info[i].tested.erase = flashchips[i].tested.erase; + flashchip_info[i].tested.probe = flashchips[i].tested.probe; + flashchip_info[i].tested.read = flashchips[i].tested.read; + flashchip_info[i].tested.write = flashchips[i].tested.write; + flashchip_info[i].total_size = flashchips[i].total_size; + } + } + + return flashchip_info; +} + +/** + * @brief Returns list of supported mainboards + * @return List of supported mainborads + */ +fl_board_info *fl_supported_boards(void) +{ + const struct board_info *binfo = boards_known; + fl_board_info *supported_boards = NULL; + int boards_known_size = 0; + int i = 0; + + while ((binfo++)->vendor) + ++boards_known_size; + binfo = boards_known; + /* add place for {0} */ + ++boards_known_size; + + supported_boards = malloc(boards_known_size * sizeof(fl_board_info)); + + if (!supported_boards) { + msg_gerr("Out of memory!"); + } else { + for (; i < boards_known_size; ++i) { + supported_boards[i].vendor = binfo[i].vendor; + supported_boards[i].name = binfo[i].name; + supported_boards[i].working = binfo[i].working; + } + } + + return supported_boards; +} + +/** + * @brief Returns list of supported chipsets + * @return List of supported chipsets + */ +fl_chipset_info *fl_supported_chipsets(void) +{ + const struct penable *chipset = chipset_enables; + fl_chipset_info *supported_chipsets = NULL; + int chipset_enbales_size = 0; + int i = 0; + + while ((chipset++)->vendor_name) + ++chipset_enbales_size; + chipset = chipset_enables; + /* add place for {0}*/ + ++chipset_enbales_size; + + supported_chipsets = malloc(chipset_enbales_size * sizeof(fl_chipset_info)); + + if (!supported_chipsets) { + msg_gerr("Out of memory!"); + } else { + for (; i < chipset_enbales_size; ++i) { + supported_chipsets[i].vendor = chipset[i].vendor_name; + supported_chipsets[i].chipset = chipset[i].device_name; + supported_chipsets[i].status = chipset[i].status; + } + } + + return supported_chipsets; +} + +/** + * @brief Frees fl_*_info and string lists allocated by flashrom + * @param Pointer to block of memory which should be freed + * @return 0 on success + * 1 on null pointer error + */ +int fl_data_free(void *const p) +{ + if (!p) { + msg_gerr("Null pointer!"); + return 1; + } else { + free(p); + return 0; + } +} /** @} */ /* end fl-query */ diff --git a/libflashrom.h b/libflashrom.h index 2077407..5308fa3 100644 --- a/libflashrom.h +++ b/libflashrom.h @@ -38,6 +38,46 @@ typedef enum { /* This has to match enum msglevel. */ typedef int(fl_log_callback_t)(fl_log_level_t, const char *format, va_list); void fl_set_log_callback(fl_log_callback_t *); +typedef enum { + FL_TESTED_OK = 0, + FL_TESTED_NT = 1, + FL_TESTED_BAD = 2, + FL_TESTED_DEP = 3, + FL_TESTED_NA = 4, +} fl_test_state; + +typedef struct { + const char *vendor; + const char *name; + unsigned int total_size; + + struct fl_tested { + fl_test_state probe; + fl_test_state read; + fl_test_state erase; + fl_test_state write; + } tested; +} fl_flashchip_info; + +typedef struct { + const char *vendor; + const char *name; + fl_test_state working; +} fl_board_info; + +typedef struct { + const char *vendor; + const char *chipset; + fl_test_state status; +} fl_chipset_info; + +const char** fl_supported_programmers(void); +const char* fl_version(void); +fl_flashchip_info *fl_supported_flash_chips(void); +fl_board_info *fl_supported_boards(void); +fl_chipset_info *fl_supported_chipsets(void); +int fl_data_free(void *const p); + int fl_programmer_init(const char *prog_name, const char *prog_params); int fl_programmer_shutdown(void); -- 2.1.4

4 years, 11 months

[PATCH 2/4] Libflashrom: Fix libflashrom building

by Łukasz Dmitrowski

Anton Kochkov's fixes for libflashrom building Signed-off-by: Lukasz Dmitrowski <lukasz.dmitrowski(a)gmail.com> --- Makefile | 2 +- flashrom.c | 8 ++++---- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/Makefile b/Makefile index d18de09..2c7fccd 100644 --- a/Makefile +++ b/Makefile @@ -726,7 +726,7 @@ FEATURE_CFLAGS += $(shell LC_ALL=C grep -q "UTSNAME := yes" .features && printf # We could use PULLED_IN_LIBS, but that would be ugly. FEATURE_LIBS += $(shell LC_ALL=C grep -q "NEEDLIBZ := yes" .libdeps && printf "%s" "-lz") -LIBFLASHROM_OBJS = $(CHIP_OBJS) $(PROGRAMMER_OBJS) $(LIB_OBJS) +LIBFLASHROM_OBJS = $(CHIP_OBJS) $(PROGRAMMER_OBJS) $(LIB_OBJS) udelay.o OBJS = $(CLI_OBJS) $(LIBFLASHROM_OBJS) all: hwlibs features $(PROGRAM)$(EXEC_SUFFIX) $(PROGRAM).8 diff --git a/flashrom.c b/flashrom.c index 9b82d4c..0bc821a 100644 --- a/flashrom.c +++ b/flashrom.c @@ -622,7 +622,7 @@ static unsigned int count_usable_erasers(const struct flashctx *flash) return usable_erasefunctions; } -static int compare_range(const uint8_t *wantbuf, const uint8_t *havebuf, unsigned int start, unsigned int len) +int compare_range(const uint8_t *wantbuf, const uint8_t *havebuf, unsigned int start, unsigned int len) { int ret = 0, failcount = 0; unsigned int i; @@ -1563,7 +1563,7 @@ int erase_and_write_flash(struct flashctx *flash, uint8_t *oldcontents, uint8_t return ret; } -static void nonfatal_help_message(void) +void nonfatal_help_message(void) { msg_gerr("Good, writing to the flash chip apparently didn't do anything.\n"); #if CONFIG_INTERNAL == 1 @@ -1581,7 +1581,7 @@ static void nonfatal_help_message(void) "mail flashrom(a)flashrom.org, thanks!\n"); } -static void emergency_help_message(void) +void emergency_help_message(void) { msg_gerr("Your flash chip is in an unknown state.\n"); #if CONFIG_INTERNAL == 1 @@ -1605,7 +1605,7 @@ void list_programmers(const char *delim) if (p < PROGRAMMER_INVALID - 1) msg_ginfo("%s", delim); } - msg_ginfo("\n"); + msg_ginfo("\n"); } void list_programmers_linebreak(int startcol, int cols, int paren) -- 2.1.4

4 years, 11 months

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coreboot August 2015