coreboot June 2015

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New on blogs.coreboot.org: [GSoC] End user flash tool - week #4 #5
by WordPress 29 Jun '15

29 Jun '15

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Re: [coreboot] Using SeaBIOS as coreboot paylod fail
by Yu-Cheng Liu 28 Jun '15

28 Jun '15

Thanks for your kindly reply. 1.I tried your suggestion,disable CONFIG_COMPRESSED_PAYLOAD_LZMA option,but still not work(I also disable SeaBIOS any about LZMA option),do anything else I can try? 2.I can't find out where I can change the Memory begin address(I tried to change some coreboot address,but It seems no work, I find log address, nothing get change),If you know ,please point out where I need to modify. thank you~ 2015-06-24 17:55 GMT+08:00 WANG FEI <wangfei.jimei(a)gmail.com>: > Yu-Cheng, looking through the log and just have two suggestions here. > > 1. It mentions the payload size is 0xc5a5, is it too small for a payload? > My understanding is that something wrong in payload compressing, please set CONFIG_COMPRESSED_PAYLOAD_LZMA > to N and try again, I remember I saw similar issue few years ago, but never > look into the details. > > CBFS: Found @ offset 102c0 size c5a5 > > 2. I noticed you've reported 0xC000 - 0xFFFFF as the normal RAM, QEMU > should have shadow RAM switches for this special address RAM, I would > suggest you reporting the RAM starting from 0x10000. > > 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES > 1. 0000000000001000-000000000009ffff: RAM > 2. 00000000000c0000-0000000007fb0fff: RAM > 3. 0000000007fb1000-0000000007ffffff: CONFIGURATION TABLES > > > On Thu, Jun 18, 2015 at 10:58 AM, Yu-Cheng Liu <peter90609(a)gmail.com> > wrote: > >> hello, >> Below are my error message when using SeaBIOS as coreboot payload,Please >> help me figure out what’s wrong with my steps.Thank you in advance. >> >> >> coreboot table: 316 bytes. >> IMD ROOT 0. 07fff000 00001000 >> IMD SMALL 1. 07ffe000 00001000 >> CONSOLE 2. 07fde000 00020000 >> ACPI 3. 07fba000 00024000 >> SMBIOS 4. 07fb9000 00000800 >> COREBOOT 5. 07fb1000 00008000 >> IMD small region: >> IMD ROOT 0. 07ffec00 00000400 >> CAR GLOBALS 1. 07ffebe0 0000000c >> ROMSTAGE 2. 07ffebc0 00000004 >> GDT 3. 07ffe9c0 00000200 >> CBFS provider active. >> CBFS @ 100000 size ffc80 >> CBFS: Locating 'fallback/payload' >> CBFS: Found @ offset 102c0 size c5a5 >> 'fallback/payload' located at offset: 1102f8 size: c5a5 >> Loading segment from rom address 0xfff102f8 >> code (compression=1) >> New segment dstaddr 0xe7c04 memsize 0x183fc srcaddr 0xfff10330 filesize >> 0xc56d >> Loading segment from rom address 0xfff10314 >> Entry Point 0x000fcfff >> Bounce Buffer at 07f5e000, 338264 bytes >> Loading Segment: addr: 0x00000000000e7c04 memsz: 0x00000000000183fc >> filesz: 0x000000000000c56d >> lb: [0x0000000000100000, 0x00000000001294ac) >> Post relocation: addr: 0x00000000000e7c04 memsz: 0x00000000000183fc >> filesz: 0x000000000000c56d >> using LZMA >> lzma: Decoding error = 1 >> Payload not loaded. >> >> >> >> >> PS.:if you want see more about my option setting,step >> >> Setpup step: >> https://dl.dropboxusercontent.com/u/73839141/Qemu_coreboot.pdf >> >> SeaBIOS config: >> https://dl.dropboxusercontent.com/u/73839141/SeaBIOSConfig.txt >> >> Coreboot config: >> https://dl.dropboxusercontent.com/u/73839141/CorebootConfig.txt >> >> Erro Message: >> https://dl.dropboxusercontent.com/u/73839141/ErrMsg.txt >> >> >> >> >> -- >> coreboot mailing list: coreboot(a)coreboot.org >> http://www.coreboot.org/mailman/listinfo/coreboot >> > >

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flashrom claims T60 is unsupported
by Richard Simpson 28 Jun '15

28 Jun '15

Hello, I have had partial success with flashing my T60. After the first flash the laptop re-booted OK, but the screen is completely black. Fiddling with the backlight buttons doesn't have any effect. Fortunately, I can connect via ssh so I am not locked out. I believe that my mistake was to put my ATI VGA bios into coreboot rather than SeaBIOS. I have now corrected this but I can't flash the updated version. For the first flash I used the following command: ./flashrom/i686/flashrom_lenovobios_sst -p internal -w coreboot.rom I got loads of errors as mentioned in the instructions, but it seemed to work. Since I now want to do another flash I have followed the instructions and used this simpler command: ./flashrom/i686/flashrom -p internal -w coreboot.rom I get the following error: flashrom v0.9.8-unknown on Linux 3.10.0-229.4.2.el7.x86_64 (x86_64) flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OK. coreboot table found at 0xbfea0000. ======================================================================== WARNING! You seem to be running flashrom on an unsupported laptop. Laptops, notebooks and netbooks are difficult to support and we recommend to use the vendor flashing utility. The embedded controller (EC) in these machines often interacts badly with flashing. See the manpage and http://www.flashrom.org/Laptops for details. If flash is shared with the EC, erase is guaranteed to brick your laptop and write may brick your laptop. Read and probe may irritate your EC and cause fan failure, backlight failure and sudden poweroff. You have been warned. ======================================================================== Aborting. Error: Programmer initialization failed. I have tried flashrom, flashrom_lenovobios_sst and flashrom_lenovobios_macronix and get the same error every time. I have also tried re-flashing the current working but blank screen bios and that won't go in either. Suggestions gratefully received.

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New on blogs.coreboot.org: [GSoC] EC/H8S firmware week #3|4
by WordPress 27 Jun '15

27 Jun '15

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Re: [coreboot] Interrupt mapping with NetBSD
by Jonathan A. Kollasch 27 Jun '15

27 Jun '15

On Sat, Jun 27, 2015 at 04:09:08PM +0300, Andrey Korolyov wrote: > Hello, > > can anyone please provide a solid pointer for a 'patch' mentioned in > http://www.coreboot.org/NetBSD#Interrupt_routing? It looks like that > the even recent MPBIOS code in NetBSD kernel is not able to place all > interrupts correctly if coreboot is used with SeaBIOS payload, my > 82577 does not work exactly because of that under this OS. The target > hardware is a well-supported X201 platform, if this can add more > sense. The patch is unnecessary if the payload is SeaBIOS, which is the payload you want to use to boot NetBSD anyway. I barely remember the details of the patch at this point, and I have no idea if I still have it laying around. Anyway, you almost certainly don't want to be relying on anything other than the DSDT for interrupt routing on a modern machine with a modern OS. Jonathan Kollasch

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Interrupt mapping with NetBSD
by Andrey Korolyov 27 Jun '15

27 Jun '15

Hello, can anyone please provide a solid pointer for a 'patch' mentioned in http://www.coreboot.org/NetBSD#Interrupt_routing? It looks like that the even recent MPBIOS code in NetBSD kernel is not able to place all interrupts correctly if coreboot is used with SeaBIOS payload, my 82577 does not work exactly because of that under this OS. The target hardware is a well-supported X201 platform, if this can add more sense.

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Re: [coreboot] coreboot Digest, Vol 124, Issue 30
by John Lewis 26 Jun '15

26 Jun '15

On Sat, Jun 06, 2015 at 01:55:30PM -0400, Starly Solon wrote: > Hi there, > > I would like to k ow of there's a version of SeaBIOS that works with > the > BayTrail Chromebooks and if there's none where could I find information > about what's missing? I currently have a laptop with a BayTrail > processor, > is there a way of dumping the BIOS/UEFI to help (I'm currently running > a > GNU/Linux distro on it)? This will help with specifics - https://johnlewis.ie/build-your-own-baytrail-boot_stub/ John.

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Re: [coreboot] SeaBIOS on BayTrail Chromebooks
by Kevin O'Connor 24 Jun '15

24 Jun '15

On Sat, Jun 06, 2015 at 01:55:30PM -0400, Starly Solon wrote: > Hi there, > > I would like to k ow of there's a version of SeaBIOS that works with the > BayTrail Chromebooks and if there's none where could I find information > about what's missing? I currently have a laptop with a BayTrail processor, > is there a way of dumping the BIOS/UEFI to help (I'm currently running a > GNU/Linux distro on it)? I'm not sure if you obtained a response to your question. SeaBIOS should run on a BayTrial chromebook with two exceptions: the builtin keyboard may not work and seabios doesn't support builtin mmc storage. The first issue should be easy to work around if you are willing to run some tests. The second could probably also be implemented, but would need a bit more work. Also, note that the google seabios repo has patches that address both of the above. -Kevin

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coreboot for gigabyte ma785gmt failed during PCI enumeration for onboard VGA
by 김용곤 21 Jun '15

21 Jun '15

I'm trying to use coreboot for gigabyte ga-ma785gmt-ud2h but booting sequence hangs during pci enumeration in ramstage. I found that reading pci configuration space of on-board VGA (RADEON HD 4200) is source of the problem. I tried to modify compile configuration in order to disable mmconf and use ported i/o (in, out instructions) but still the coreboot fails at the same location. (pci enumeration step for the onboard VGA) My coreboot stops during pci_conf1_read_config32 call. (at 'return inl(0xCFC);' ) I also tried to extract vga bios and embed it into coreboot using "Add a VGA BIOS image" option, but it didn't make any changes. How can i resolve this situation? I have no idea. Any comments or helps will be really appreciated for me. I have attached serial port debug messages. Followings are the result of lspci command after the normal BIOS booting. ilios@ilios-GA-MA785GMT-UD2H:~$ lspci 00:00.0 Host bridge: Advanced Micro Devices, Inc. [AMD] RS880 Host Bridge 00:01.0 PCI bridge: Advanced Micro Devices, Inc. [AMD] RS780/RS880 PCI to PCI bridge (int gfx) 00:0a.0 PCI bridge: Advanced Micro Devices, Inc. [AMD] RS780/RS880 PCI to PCI bridge (PCIE port 5) 00:11.0 SATA controller: Advanced Micro Devices, Inc. [AMD/ATI] SB7x0/SB8x0/SB9x0 SATA Controller [IDE mode] 00:12.0 USB controller: Advanced Micro Devices, Inc. [AMD/ATI] SB7x0/SB8x0/SB9x0 USB OHCI0 Controller 00:12.1 USB controller: Advanced Micro Devices, Inc. [AMD/ATI] SB7x0 USB OHCI1 Controller 00:12.2 USB controller: Advanced Micro Devices, Inc. [AMD/ATI] SB7x0/SB8x0/SB9x0 USB EHCI Controller 00:13.0 USB controller: Advanced Micro Devices, Inc. [AMD/ATI] SB7x0/SB8x0/SB9x0 USB OHCI0 Controller 00:13.1 USB controller: Advanced Micro Devices, Inc. [AMD/ATI] SB7x0 USB OHCI1 Controller 00:13.2 USB controller: Advanced Micro Devices, Inc. [AMD/ATI] SB7x0/SB8x0/SB9x0 USB EHCI Controller 00:14.0 SMBus: Advanced Micro Devices, Inc. [AMD/ATI] SBx00 SMBus Controller (rev 3c) 00:14.1 IDE interface: Advanced Micro Devices, Inc. [AMD/ATI] SB7x0/SB8x0/SB9x0 IDE Controller 00:14.2 Audio device: Advanced Micro Devices, Inc. [AMD/ATI] SBx00 Azalia (Intel HDA) 00:14.3 ISA bridge: Advanced Micro Devices, Inc. [AMD/ATI] SB7x0/SB8x0/SB9x0 LPC host controller 00:14.4 PCI bridge: Advanced Micro Devices, Inc. [AMD/ATI] SBx00 PCI to PCI Bridge 00:14.5 USB controller: Advanced Micro Devices, Inc. [AMD/ATI] SB7x0/SB8x0/SB9x0 USB OHCI2 Controller 00:18.0 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 10h Processor HyperTransport Configuration 00:18.1 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 10h Processor Address Map 00:18.2 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 10h Processor DRAM Controller 00:18.3 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 10h Processor Miscellaneous Control 00:18.4 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 10h Processor Link Control 01:05.0 VGA compatible controller: Advanced Micro Devices, Inc. [AMD/ATI] RS880 [Radeon HD 4200] 01:05.1 Audio device: Advanced Micro Devices, Inc. [AMD/ATI] RS880 HDMI Audio [Radeon HD 4200 Series] 02:00.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL8111/8168/8411 PCI Express Gigabit Ethernet Controller (rev 02) 03:0e.0 FireWire (IEEE 1394): Texas Instruments TSB43AB23 IEEE-1394a-2000 Controller (PHY/Link) ilios@ilios-GA-MA785GMT-UD2H:~$

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CBFS files located outside itself error
by Tyler Parks 20 Jun '15

20 Jun '15

I'm using Fedora 20 x86_64, along with freshly pulled Coreboot source, and trying to compile Coreboot for QEMU. However I get a make error that says CBFS files located outside itself. I haven't been able to find any information on what this means, or how to fix it; I'd appreciate any hints. The actual make error looks like this: HOSTCC cbfstool/lzma.o HOSTCC cbfstool/LzFind.o HOSTCC cbfstool/LzmaDec.o HOSTCC cbfstool/LzmaEnc.o HOSTCC cbfstool/linux_trampoline.o HOSTCC cbfstool/cbfs-payload-linux.o HOSTCC cbfstool/cbfstool (link) E: CBFS file entries are located outside CBFS itself make: *** [build/coreboot.pre1] Error 1 In the menuconfig, I set up configuration for QEMU like this (other options left as defaults): General: Enable ccache to speed up (re)compiling Mainboard: vendor = emulation model = QEMU x86 i440fx/piix4 (aka qemu -M pc) rom = 256kB Devices: add VGA BIOS: vgabios-cirrus.bin (I copied qemu's vgabios into the coreboot directory) Console: use onboard VGA as primary video device Payload: SeaBIOS master use LZMA compression I don't know if it's related, but when I ran make crossgcc prior to building, it compiled the i386, x86_64, and armv7 tool chains, but failed building binutils for aarch64. I only intend to build for 32bit and 64bit x86, so I ignored the aarch64 error: Building BINUTILS 2.25 ... failed. Check build-aarch64-elf-BINUTILS/build.log. make[1]: *** [build-aarch64-without-gdb] Error 1 make: *** [crossgcc-aarch64] Error 2 greping the aarch64 build.log file for Error outputs: ./build.log:make[1]: *** [configure-libiberty] Error 1 ./build.log:make: *** [all] Error 2 ./build.log:make[1]: *** [install-bfd] Error 2 ./build.log:make: *** [install] Error 2

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coreboot June 2015