coreboot November 2015

coreboot@coreboot.org

38 participants
97 discussions

Saved SeaBIOS configuration options for mainboards.
by Martin Roth 30 Nov '15

30 Nov '15

I recently posted a patch that would allow the coreboot build to use a saved SeaBIOS .config file stored in the mainboard directory. The initial reason for this was to replace one existing SeaBIOS configuration option that was in coreboot's Kconfig, and to remove the need for a second option that was about to be added. The intention behind this is not to add full config files, but to add individual options that are required for the platforms. That said, saving a full config will almost certainly happen at some point since this change doesn't prevent this. I'm not sure how big an issue this really is, other than creating some maintenance problems. Another side effect of this is that a user could point to a saved .config outside of the coreboot tree, to customize the SeaBIOS. I don't think this should present a problem, as the .config file for SeaBIOS is getting saved in CBFS. If we want to minimize this, the prompt in Kconfig can be removed, preventing the option from showing up in menuconfig (or your favorite config method). It was requested that I post this change to the mailing list for thoughts and review. The patches in question are here: payloads/external/SeaBIOS: Add option for saved SeaBIOS .config https://review.coreboot.org/#/c/12568 intel/mohonpeak: Change SEABIOS_MALLOC_UPPERMEMORY to config_seabios https://review.coreboot.org/#/c/12569 SeaBIOS/Kconfig: Remove SEABIOS_MALLOC_UPPERMEMORY option https://review.coreboot.org/#/c/12570 payloads/Seabios: add SEABIOS_NO_HARDWARE_IRQ symbol https://review.coreboot.org/#/c/12534/ Thoughts? Review? Downsides I didn't think of? Martin

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ASUS KFSN4-DRE Automated Test Failure
by Raptor Engineering Automated Coreboot Test Stand 30 Nov '15

30 Nov '15

The ASUS KFSN4-DRE fails verification as of commit 4013469c507847d48e891c16b92f4556a2f6b76f The following tests failed: BOOT_FAILURE Commits since last successful test: See attached log for details This message was automatically generated from Raptor Engineering's ASUS KFSN4-DRE test stand Want to test on your own equipment? Check out https://www.raptorengineeringinc.com/content/REACTS/intro.html Raptor Engineering also offers coreboot consulting services! Please visit https://www.raptorengineeringinc.com for more information Please contact Timothy Pearson at Raptor Engineering <tpearson(a)raptorengineeringinc.com> regarding any issues stemming from this notification

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ASUS KFSN4-DRE (K8) Automated Test Failure
by Raptor Engineering Automated Coreboot Test Stand 30 Nov '15

30 Nov '15

The ASUS KFSN4-DRE (K8) fails verification as of commit 4013469c507847d48e891c16b92f4556a2f6b76f The following tests failed: BOOT_FAILURE Commits since last successful test: See attached log for details This message was automatically generated from Raptor Engineering's ASUS KFSN4-DRE (K8) test stand Want to test on your own equipment? Check out https://www.raptorengineeringinc.com/content/REACTS/intro.html Raptor Engineering also offers coreboot consulting services! Please visit https://www.raptorengineeringinc.com for more information Please contact Timothy Pearson at Raptor Engineering <tpearson(a)raptorengineeringinc.com> regarding any issues stemming from this notification

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What is mrc.bin and system agent binary?
by Iru Cai 28 Nov '15

28 Nov '15

Hi, I've bought a Chromebook Pixel 2013 and want to reflash the firmware. I saw in the config that I need a system agent binary. I looked into 3rdparty/blobs/nb/intel/sb/ and found three binary files, and the default one in nb/intel/sb/kconfig is systemagent-r6.bin. And I read the google/link wiki and saw another word called mrc.bin. Are they the same thing? And can I use the coreboot native MRC code for google/link? Regards, Iru

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[ANNOUNCE] SeaBIOS 1.9.0
by Kevin O'Connor 28 Nov '15

28 Nov '15

The 1.9.0 version of SeaBIOS has now been released. For more information on the release, please see: http://seabios.org/Releases New in this release: * The default boot menu key is now the ESC key (instead of F12) * Initial support for Trusted Platform Module (TPM) hardware and BIOS calls * Initial support for chain loading SeaBIOS from Grub (via multiboot support) * Initial support for booting from SD cards on real hardware * virtio 1.0 device support * The build will no longer include the build hostname or build time on "clean" builds. This makes the build binaries more "reproducible". * Basic support for running SeaBIOS on Baytrail Chromebooks * SeaVGABIOS improvements: * Improved support for old versions of x86emu (the "leal" instruction is now emulated) * Several bug fixes and code cleanups For information on obtaining SeaBIOS, please see: http://seabios.org/Download ===== git shortlog -n rel-1.8.0..rel-1.9.0 ===== Kevin O'Connor (126): docs: add page for SeaVGABIOS docs: Add page describing the patch contribution process docs: Add page on available CBFS/fw_cfg runtime config files docs: Prefer triple backticks to multiple lines with single backticks smp: Fix smp race introduced in 0673b787 docs: Note release date of 1.8.1 vgabios: On bda_save_restore() the saved vbe_mode also has flags in it vgabios: Don't use extra stack if it appears a modern OS is in use docs: Clarify that pci-optionrom-exec doesn't apply to roms in cbfs checkstack: Replace function information tuple with class checkstack: Simplify yield calculations checkstack: Prefer passing "function" class instead of function address smbios: Use integer signature instead of string signature vgabios: Don't use "smsww" instruction - it confuses x86emu vgabios: Add config option for assembler fixups vgabios: Emulate "leal" instruction checkstack: Minor - continue if not a regular asm line Don't forward declare functions with "inline" in headers build: Support "make VERSION=xyz" to override the default build version tcg: Use seabios setup()/prepboot() calling convention for tcg build: CONFIG_VGA_FIXUP_ASM should depend on CONFIG_BUILD_VGABIOS bootorder: Update "extra pci root" buses bootorder format to match qemu Make sure all code checks for malloc failures docs: Note release date of 1.8.2 block: Split process_op() command dispatch up into multiple functions block: Introduce default_process_op() with common command handling codes block: Route scsi style commands through 'struct disk_op_s' blockcmd: Introduce scsi_fill_cmd() ata: Handle ATA ATAPI drives directly via 'struct disk_op_s' requests ahci: Handle AHCI ATAPI drives directly via 'struct disk_op_s' requests usb-msc: Handle USB drives directly via 'struct disk_op_s' requests usb-uas: Handle USB drives directly via 'struct disk_op_s' requests lsi-scsi: Handle LSI drives directly via 'struct disk_op_s' requests esp-scsi: Handle ESP drives directly via 'struct disk_op_s' requests megasas: Handle Megasas drives directly via 'struct disk_op_s' requests virtio-scsi: Handle virtio drives directly via 'struct disk_op_s' requests pvscsi: Move pvscsi_fill_req() code into pvscsi_cmd() pvscsi: Handle pvscsi drives directly via 'struct disk_op_s' requests blockcmd: Remove unused scsi_process_op() and cdb_cmd_data() blockcmd: Convert cdb_is_read() to scsi_is_read() block: Rename process_XXX_op() functions to XXX_process_op() coreboot: Try to auto-detect if the CBFS anchor pointer is a relative pointer ps2: Support mode for polling the PS2 port instead of using irqs ata: Make sure "chanid" is relative to PCI device for bootorder file Don't enable interrupts prior to IVT and PIC setup ps2: Don't wait 100ms to discard possible extra reset receive byte timer: Delay timestamp counter init until after pmtimer is probed timer: Add CONFIG_TSC_TIMER build option to disable the CPU TSC timer ramdisk: Allow ramdisk support (CONFIG_FLASH_FLOPPY) under QEMU Minor - move declaration of CDRom_locks to code that uses it smm: ignore bits 16,18-31 of SMM revision ID at runtime too vgafb: Minor - move gfx_common() variables outside of switch statement sdcard: Check if card is present before sending commands to card sdcard: Implement controller frequency setting according to sdhci spec sdcard: Make sure controller support 3.3V before enabling it sdcard: Set timeout control register during init (to max allowed timeout) sdcard: Improve SD card initialization command sequence sdcard: Add proper delays during card power up mptable: Don't create mptable if it is very large optionroms: Don't run option rom on PCI bar if CBFS/fw_cfg version exists edd: Pass the segment/offset from int 1348 calls using a 'struct segoff_s' edd: Reduce parameters to fill_generic_edd() Move CanInterrupt check to check_irqs() Call cpu_relax() if yielding prior to interrupts being enabled sdcard: Fix typo - use sdcard_pio() instead of sdcard_pio_app() sdcard: Fill command bits according to spec sdcard: Support SDHCI v3.00 spec clock setting sdcard: Move power setup to new function sdcard_set_power() sdcard: Power controller up to maximum voltage supported sdcard: Power down controller on failure sdcard: The card should never be in a busy state at start of sdcard_pio() sdcard: Implement timeout on every block read in sdcard_pio_transfer() sdcard: Rename waitw() to sdcard_waitw() and simplify sdcard: Perform a controller reset at start of init sdcard: Check for error events during sdcard_pio() sdcard: Initial support for MMC cards sdcard: Allow the sdcard driver to run on real hardware rtc: Support disabling the RTC timer irq support Add minimal support for machines without hardware interrupts ps2: Eliminate "etc/ps2-poll-only"; use CONFIG_HARDWARE_IRQ instead sdcard: Allow sdcard addresses to be specified in CBFS files xhci: Minor - add USB port type comments to xhci_hub_reset() docs: Don't use an add-symbol-file offset when describing gdb debugging rtc: Disable NMI in rtc_mask() sdcard: Move sdcard_set_frequency()/sdcard_set_power() in sdcard.c sdcard: Move frequency setting into sdcard_card_setup() sdcard: Move drive registration to sdcard_card_setup() sdcard: Turn card_type into a bitmap and store if card is MMC type sdcard: Display sdcard product name in boot menu sdcard: Obtain card capacity and report it on the boot menu megasas: Use outl() on MFI_IDB register minor - correct spelling error in comment Simplify transition16/32 assembler code docs: Minor - add "code relocation" link to "Execution and code flow" document Unify smm/sloppy variants of call32_prep/post and call16_helper Rename Call32Data to Call16Data Unify inline assembler in variants of call16 functions Unify call32_sloppy() and call32() Use transition32_nmi_off from call32() and call16_back() Consolidate code16*() functions Always enable caching on transition32; backup/restore cr0 on call32 e820: Introduce e820_remove() and avoid exporting E820_HOLE e820: Rename memmap.c to e820map.c and use consistent "e820_" prefix e820: Update debugging messages to report 64bit values virtio: Simplify vring alignment code virtio: Move standard definitions from virtio-ring.h to standard headers malloc: Use consistent naming for internal low-level "alloc" functions malloc: Introduce common helper alloc_new_detail() malloc: Add warning if free() called on invalid memory malloc: Don't mix virtual and physical addresses memmap: Introduce SYMBOL() macro to access linker script symbols build: Rework version generation; don't allow make version override build: Report gcc and binutils versions in debug log build: Generate "reproducible" version strings on "clean" builds stacks: Use macro wrappers for call32() and stack_hop_back() malloc: Rename csm_malloc_preinit() to malloc_csm_preinit() build: Be more permissive in buildversion.py tool version scan docs: Document 'make EXTRAVERSION=xyz' and scripts/tarball.sh build: Allow official tarball builds to be considered "clean" coreboot: Minor - avoid K&R style function declaration biostables: Minor - fix incorrect indentation virtio: Minor - replace tab characters with space docs: Minor - replace seavgabios text in Build_overview.md with link buildversion: Avoid subprocess.check_output() as that requires python2.7 buildversion: Add debugging messages docs: Note v1.9.0 release Gerd Hoffmann (28): vga: simplify vga builds vga: rework virtio-vga support vga: add virtio-vga to kconfig pci: allow to loop over capabilities virtio: run drivers in 32bit mode virtio: add struct vp_device virtio: pass struct pci_device to vp_init_simple virtio: add version 1.0 structs and #defines virtio: add version 0.9.5 struct virtio: find version 1.0 virtio capabilities virtio: create vp_cap struct for legacy bar virtio: add read/write functions and macros virtio: make features 64bit, support version 1.0 features virtio: add version 1.0 support to vp_{get,set}_status virtio: add version 1.0 support to vp_get_isr virtio: add version 1.0 support to vp_reset virtio: add version 1.0 support to vp_notify virtio: remove unused vp_del_vq virtio: add version 1.0 support to vp_find_vq virtio-scsi: fix initialization for version 1.0 virtio-blk: fix initialization for version 1.0 virtio: use version 1.0 if available (flip the big switch) virtio: also probe version 1.0 pci ids virtio: legacy cleanup virtio-blk: 32bit cleanup virtio-scsi: 32bit cleanup virtio-ring: 32bit cleanup virtio-pci: use high memory for rings Stefan Berger (9): Add an implementation of a TPM TIS driver Implementation of the TCG BIOS extensions Support for BIOS interrupt handler Add 'measurement' code to the BIOS tpm: Introduce a #define for command tag tpm: Be consistent with array sizes in tcgbios.c tpm: clean up parameters to build_and_send_cmd tpm: Clean up in tcgbios.h tpm: Move call to tpm_option_rom into init_optionrom Paolo Bonzini (4): boot.c: delay exiting boot if menu key is ESC boot: switch default menu key to ESC smm: ignore bits 16,18-31 of SMM revision ID smm: fix outl argument order Vladimir Serbinenko (3): ahci: Ignore max_ports. Link rom.o with -N option. Add multiboot support. Marcel Apfelbaum (2): fw/pci: scan all buses if extraroots romfile is present fw/pci: map memory and IO regions for multiple pci root buses Stefan Weil (2): megasas: Fix outw, outl argument order Fix typos found by codespell Ameya Palande (1): x86: add barrier to read{b,w,l} and write{b,w,l} functions Andreas Färber (1): checkrom: Fix typo in error message Chen Fan (1): pci: enable SERR# for error forwarding in bridge control register Julius Werner (1): xhci: Count new Max Scratchpad Bufs bits from XHCI 1.1 Kyösti Mälkki (1): PCI SDHCI driver: Fix base address Magnus Granberg (1): build: use -fstack-check=no when available Marc Marí (1): Add QEMU fw_cfg DMA interface Paulo Alcantara (1): ich9: initialise RCBA register through LPC interface Quan Xu (1): make SeaBios compatible with Xen vTPM. tpearson(a)raptorengineeringinc.com (1): Add an option to only execute option ROMs contained in CBFS

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ThinkPad X120e/X140e
by Łukasz Dobrowolski 27 Nov '15

27 Nov '15

Hi all! I would like to port coreboot to one of my laptops (ThinkPad X140e and X120e). Both of them have AMD APU-s. I would be grateful if somebody could take a look at attachments and tell me how challenging the task appears to be. I read and searched for information about those for few days now. What I found (apart from attachments): X120e: Logical mainboard schematics I'm 90% sure I can get my hands on physical mainboard schematics if needed. I have detailed pictures of the mainboard. X140e: I can make detailed mainboard pictures. I haven't searched for schematics of this one yet. Regards from Lisbon lynx

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Rebuilding coreboot image generation
by Patrick Georgi 24 Nov '15

24 Nov '15

Hey coreboot folks, I'm looking for an approach to make building Chrome OS style coreboot images easier to do with regular coreboot tools, instead of the rather large post-processing pipeline we have in the Chrome OS build system. The rationale is that we also push the Chrome OS capabilities (eg. verified boot) upstream, and actually using them shouldn't depend on checking out yet another custom build environment. I wrote a proposal on how to do that, which can be found and commented at https://docs.google.com/document/d/1o2bFl5HCHDFPccQsOwa-75A8TWojjFiGK3r0yeI… If this is to be implemented, I'd do that as part of coreboot's build system, and work on supporting the regular image types (with a "simple" bootblock and a fallback/normal switch configuration) we currently have. I appreciate comments and concerns how this fits in with other use cases. Thanks, Patrick -- Google Germany GmbH, ABC-Str. 19, 20354 Hamburg Registergericht und -nummer: Hamburg, HRB 86891, Sitz der Gesellschaft: Hamburg Geschäftsführer: Matthew Scott Sucherman, Paul Terence Manicle

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Re: [coreboot] CBMEM Console corruption with fsp_baytrail in coreboot 4.2
by Aaron Durbin 23 Nov '15

23 Nov '15

On Sat, Nov 21, 2015 at 10:14 PM, Ben Gardner <gardner.ben(a)gmail.com> wrote: > I think I found the issue, but won't be able to test for another week. > > car_get_var_ptr() assumes that the migrated base is the same as _car_data_start. > On FSP 1.0, that isn't true. _car_data_start is 0x0c00 bytes past > migrated base. > > The last two lines of car_get_var_ptr() read as follows: > offset = (char *)var - (char *)_car_data_start; > return &migrated_base[offset]; > > However, migrated base matches 0xfef00000 (DCACHE_RAM_BASE), while > _car_data_start is 0xfef00c00. > So, when the data is migrated, the migrated offset is wrong and > cbmem_console_p is fairly random. > > It worked when I moved _preram_cbmem_console because that put > _car_data_start at 0xfef00000 again. > A simple fix would be to use CONFIG_DCACHE_RAM_BASE instead of > _car_data_start when calculating the base. > > I think we may also need Aaron's earlier patch proposed in this > thread, as _preram_cbmem_console is not between _car_data_start and > _car_data_end. Yes. We should bring that patch in. > > The fix might be something like the following: (gmail ate my tabs). > > What do you think? > > --- a/src/cpu/x86/car.c > +++ b/src/cpu/x86/car.c > @@ -63,15 +63,15 @@ void *car_get_var_ptr(void *var) > #if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_0) > migrated_base=(char *)find_saved_temp_mem( > *(void **)CBMEM_FSP_HOB_PTR); > + offset = (char *)var - (char *)CONFIG_DCACHE_RAM_BASE; > #else > migrated_base = cbmem_find(CBMEM_ID_CAR_GLOBALS); > + offset = (char *)var - (char *)_car_start; > #endif > > if (migrated_base == NULL) > die( "CAR: Could not find migration base!\n"); > > - offset = (char *)var - (char *)_car_start; > - > return &migrated_base[offset]; > } That makes sense. FSP 1.0 moves entire CAR region while coreboot only moves the CAR_GLOBALs proper. So the relative offset changes depending on object layout. > > > On Fri, Nov 20, 2015 at 5:11 PM, Ben Gardner <gardner.ben(a)gmail.com> wrote: >> On Fri, Nov 20, 2015 at 4:56 PM, Ben Gardner <gardner.ben(a)gmail.com> wrote: >>> Ug. I was looking at the wrong log. Time for a break. >>> >>> The output from the log was: >>> Stack: fef03fc4 or fef03fcc >>> >>> That seems to match the settings: >>> CONFIG_DCACHE_RAM_BASE=0xfef00000 >>> CONFIG_DCACHE_RAM_SIZE=0x4000 >> >> For what it is worth, I verified that ECX = 0xfef00000 and EDX = >> 0xfef04000 when the FSP's TempRamIinitEntry() function returns. >> The CAR global data makes more sense now, as that is mapped to the >> bottom of the temporary stack area. >> The CAR data location is correct and the stack data does indeed appear >> to have been copied correctly to 0x7ae230a0. >> I think I'm looking in the wrong area. >> >> Oh, well. I'll look at it again after the Thanksgiving holiday. >> >> Ben

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New on blogs.coreboot.org: coreboot changelog
by WordPress 23 Nov '15

23 Nov '15

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Re: [coreboot] CBMEM Console corruption with fsp_baytrail in coreboot 4.2 (fixed)
by Ben Gardner 23 Nov '15

23 Nov '15

Hi all, A fix to the timestamp/console issue is available here: http://review.coreboot.org/#/c/12511/ Would you mind taking a look? Thanks Ben On Sat, Nov 21, 2015 at 10:14 PM, Ben Gardner <gardner.ben(a)gmail.com> wrote: > I think I found the issue, but won't be able to test for another week. > > car_get_var_ptr() assumes that the migrated base is the same as _car_data_start. > On FSP 1.0, that isn't true. _car_data_start is 0x0c00 bytes past > migrated base. > > The last two lines of car_get_var_ptr() read as follows: > offset = (char *)var - (char *)_car_data_start; > return &migrated_base[offset]; > > However, migrated base matches 0xfef00000 (DCACHE_RAM_BASE), while > _car_data_start is 0xfef00c00. > So, when the data is migrated, the migrated offset is wrong and > cbmem_console_p is fairly random. > > It worked when I moved _preram_cbmem_console because that put > _car_data_start at 0xfef00000 again. > A simple fix would be to use CONFIG_DCACHE_RAM_BASE instead of > _car_data_start when calculating the base. > > I think we may also need Aaron's earlier patch proposed in this > thread, as _preram_cbmem_console is not between _car_data_start and > _car_data_end. > > The fix might be something like the following: (gmail ate my tabs). > > What do you think? > > --- a/src/cpu/x86/car.c > +++ b/src/cpu/x86/car.c > @@ -63,15 +63,15 @@ void *car_get_var_ptr(void *var) > #if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_0) > migrated_base=(char *)find_saved_temp_mem( > *(void **)CBMEM_FSP_HOB_PTR); > + offset = (char *)var - (char *)CONFIG_DCACHE_RAM_BASE; > #else > migrated_base = cbmem_find(CBMEM_ID_CAR_GLOBALS); > + offset = (char *)var - (char *)_car_start; > #endif > > if (migrated_base == NULL) > die( "CAR: Could not find migration base!\n"); > > - offset = (char *)var - (char *)_car_start; > - > return &migrated_base[offset]; > } > > > On Fri, Nov 20, 2015 at 5:11 PM, Ben Gardner <gardner.ben(a)gmail.com> wrote: >> On Fri, Nov 20, 2015 at 4:56 PM, Ben Gardner <gardner.ben(a)gmail.com> wrote: >>> Ug. I was looking at the wrong log. Time for a break. >>> >>> The output from the log was: >>> Stack: fef03fc4 or fef03fcc >>> >>> That seems to match the settings: >>> CONFIG_DCACHE_RAM_BASE=0xfef00000 >>> CONFIG_DCACHE_RAM_SIZE=0x4000 >> >> For what it is worth, I verified that ECX = 0xfef00000 and EDX = >> 0xfef04000 when the FSP's TempRamIinitEntry() function returns. >> The CAR global data makes more sense now, as that is mapped to the >> bottom of the temporary stack area. >> The CAR data location is correct and the stack data does indeed appear >> to have been copied correctly to 0x7ae230a0. >> I think I'm looking in the wrong area. >> >> Oh, well. I'll look at it again after the Thanksgiving holiday. >> >> Ben

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coreboot November 2015