coreboot October 2015

coreboot@coreboot.org

44 participants
137 discussions

Re: [coreboot] Goodies for Bonn meeting
by Peter Stuge 07 Oct '15

07 Oct '15

Vladimir 'phcoder' Serbinenko wrote: > > The goodies look really great! :) How many cups, plates and magnets > > are there? > > Other than the ones already spoken for, I have: > 8 L T-shirts > 1 XL > 3 white cups > 1 x Black, yellow, orange and pink cup > 6 x plates > 3 x baseball cap > 9 x magnets > 5 x coasters I would like to order 3 plates, 1 white, 1 black, 1 pink cup and 1 magnet. If you have extra white cups I'll buy those too. If I don't make it in person I'll ask if someone might courier cash and goodies on my behalf. Let me know the amount. Thanks a lot! (Images sell. :) //Peter

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Re: [coreboot] Goodies for Bonn meeting
by Peter Stuge 07 Oct '15

07 Oct '15

Vladimir 'phcoder' Serbinenko wrote: > Reminder, please write me if you want any of this. Right now only > Ron Minnich and echelon have ordered. I've added pictures at > http://coreboot.org/Coreboot_conference_Bonn_2015 The goodies look really great! :) How many cups, plates and magnets are there? What's the square thing that isn't a magnet? Coaster or mouse pad? Thanks //Peter

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Goodies for Bonn meeting
by Vladimir 'φ-coder/phcoder' Serbinenko 06 Oct '15

06 Oct '15

Hello, all. My girlfriend Maria (CC'ed) would like to organize some goodies for coreboot meeting. Already available are black T-shirts: 2 x M, 8 x L, 1 x XL according to my notes, it's no guarantee, I can't double-check now as I'm travelling. Expected price is under €20 for any of items. Capacity is limited, first come first serve, respond to this e-mail to order. What else we can do: - White t-shirt - white cups - colour cups - Fridge magnets - case for iPhone (indicate which one), not sure which ones are available - Beer coaster - mouse pad - baseball cap In addition, if you're ok with waiting about a month + delivery time we can order: - Black t-shirt (other than the sizes mentioned above, or once the stock is out) - Colour t-shirt over €20 We're doing it just for fun and to serve the community, the price is only to cover our costs.

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Re: [coreboot] About the USB issue on the Lenovo T420 port
by Nicolas Reinecke 06 Oct '15

06 Oct '15

Hi, can you send me a RCBA dump with vendor bios, coreboot after boot and suspend? util/inteltool/inteltool -r Nicolas Reinecke Am Montag, den 05.10.2015, 21:49 +0800 schrieb Iru Cai: > Hi, > > I'm using the new Lenovo T420 port on gerrit[1] and found a bug about > USB(in my post on the gerrit page). And just now I found a work > around on this issue. > > First I tested a USB disk on the buggy USB port before suspending the > system, it works fine. Then I unplugged the USB disk, suspended my > system, resume, and replugged the disk, the bug occurred. Then I > unplugged the disk, reload the ehci_pci module as follows: > > rmmod ehci_pci > modprobe ehci-pci > > The I plugged in the USB disk, it worked fine again. > > I think the kernel message[2] gives some information about it, > because it gives two different port number on the USB device. But I > know almost nothing about USB, so I'm not sure what's happening. > > [1] http://review.coreboot.org/#/c/11765/ > [2] see the attached dmesg.log > > Iru Cai > > -- > coreboot mailing list: coreboot(a)coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot

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Compiling HowTo?
by NOQ2 Webmaster 06 Oct '15

06 Oct '15

Hello, Are there any more detailed descriptions on how to create a coreboot image for let´s say Thinkpad x61 or x230? Most of the online guides out there just describe the coreboot flashing procedure itself, not how the image was compiled before (especially which settings are of importance, how to cope with two eeprom chips in x230 - does it suffice to compile / flash a 4M image?). Any help appreciated :-) noq2

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Re: [coreboot] cbmem fails with `Failed to mmap /dev/mem: Resource temporarily unavailable`
by Aaron Durbin 05 Oct '15

05 Oct '15

http://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/drive… That patch added dmi_init() which maintains a persistent dmi mapping. However, that code used ioremap() as it's mapping. Thus, we have an uncached-minus PAT entry covering the DMI tables. I'm actually not sure why they don't just maintain a copy of the tables -- maybe for eventlog purposes? So that PAT entry will always cause issues w/ cbmem trying to do brute force 1MiB mappings of /dev/mem. On Wed, Sep 30, 2015 at 8:50 AM, Aaron Durbin <adurbin(a)google.com> wrote: > On Wed, Sep 30, 2015 at 2:29 AM, Paul Menzel > <paulepanter(a)users.sourceforge.net> wrote: >> Dear Aaron, >> >> >> thank you for the quick reply. >> >> >> Am Montag, den 28.09.2015, 09:38 -0500 schrieb Aaron Durbin: >>> On Sun, Sep 27, 2015 at 2:54 PM, Paul Menzel wrote: >> >>> > building a coreboot image for the ASRock E350M1 with the attached >>> > config, having code coverage enabled, I am unable to run the >>> > utility `cbmem`. >>> > >>> > ``` >>> > $ sudo util/cbmem/cbmem -V -l >>> > Looking for coreboot table at 0 1048576 bytes. >>> > Mapping 1MB of physical memory at 0x0 (requested 0x0). >>> > Found! >>> > coreboot table entry 0x11 >>> > Found forwarding entry. >>> > Unmapping 1MB of virtual memory at 0xb74b6000. >>> > Looking for coreboot table at c7f9f000 1048576 bytes. >>> > Mapping 1MB of physical memory at 0xffffffffc7f9f000 (requested 0xc7f9f000). >>> > ... failed. Mapping 1052671B of physical memory at 0xffffffffc7f9e000. >>> > Failed to mmap /dev/mem: Resource temporarily unavailable >>> > ``` >>> > >>> > Linux complains with the messages below. >>> > >>> > ``` >>> > $ dmesg >>> > […] >>> > [ 916.233910] x86/PAT: cbmem:2647 conflicting memory types c7f9f000-c809f000 uncached-minus<->write-back >>> > [ 916.233927] x86/PAT: reserve_memtype failed [mem 0xc7f9f000-0xc809efff], track uncached-minus, req write-back >>> > […] >>> > ``` >>> > >>> >>> You are going to need to open the /dev/mem file w/ O_SYNC flags >>> because the kernel is marking that range of memory as uncacheable. >>> More info can be found here: >>> https://www.kernel.org/doc/Documentation/x86/pat.txt >> >> I totally missed, that besides selecting code coverage, the Linux >> kernel was updated to version 4.2 in between. Probably they changed >> some default. >> >> $ uname -a >> Linux my-asrocke350m1 4.2.0-1-686-pae #1 SMP Debian 4.2.1-1 (2015-09-25) i686 GNU/Linux >> >>> # cat /sys/kernel/debug/x86/pat_memtype_list >>> >>> would be helpful >> >> $ sudo more /sys/kernel/debug/x86/pat_memtype_list >> PAT memtype list: >> uncached-minus @ 0xc7fa7000-0xc7fa8000 >> write-back @ 0xc7fb8000-0xc7fbb000 >> write-back @ 0xc7fba000-0xc7fbd000 > > Interesting. The range you requested isn't listed in here. However, > the above 3 are which are smack in the middle of region you are > requesting. I suspect that's where things are falling over. Do you > know what these are? Are they listed in /proc/iomem ? The best > visibility we have currently is the e820 below which just has the > range starting at 0xc7f9d000 through 0xe0000000. There's some weird > fudging the kernel does around the usable memory boundaries so those > may not be we coreboot exported. Presumably you have coreboot logs > from a previous boot not on this kernel? That might provide some > insight as well. > > I should also note I didn't go trolling through the kernel to figure > out its logic just yet. Just noting what you're finding. > > >> write-combining @ 0xe0040000-0xe0274000 >> write-combining @ 0xe0274000-0xe0474000 >> write-combining @ 0xe0474000-0xe0475000 >> write-combining @ 0xe0478000-0xe0978000 >> uncached-minus @ 0xf0004000-0xf0005000 >> uncached-minus @ 0xf0100000-0xf0140000 >> uncached-minus @ 0xf0140000-0xf0144000 >> uncached-minus @ 0xf0144000-0xf0148000 >> uncached-minus @ 0xf0148000-0xf0149000 >> uncached-minus @ 0xf0149000-0xf014a000 >> uncached-minus @ 0xf014a000-0xf014b000 >> uncached-minus @ 0xf014b000-0xf014c000 >> uncached-minus @ 0xf014b000-0xf014c000 >> uncached-minus @ 0xf014b000-0xf014c000 >> uncached-minus @ 0xf014b000-0xf014c000 >> uncached-minus @ 0xf8088000-0xf8089000 >> uncached-minus @ 0xfed00000-0xfed01000 >> uncached-minus @ 0xfed80000-0xfed81000 >> >>> along with this: >>> >>> $ for i in /sys/firmware/memmap/*; do echo $(cat $i/type $i/start $i/end); done >> >> $ for i in /sys/firmware/memmap/*; do echo $(sudo cat $i/type $i/start $i/end); done >> System RAM 0x0 0x9fbff >> reserved 0x9fc00 0x9ffff >> reserved 0xf0000 0xfffff >> System RAM 0x100000 0xc7f9cfff >> reserved 0xc7f9d000 0xdfffffff >> reserved 0xf8000000 0xfbffffff >> System RAM 0x100000000 0x21effffff >> >> >> Thanks, >> >> Paul >> -- >> coreboot mailing list: coreboot(a)coreboot.org >> http://www.coreboot.org/mailman/listinfo/coreboot

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About the USB issue on the Lenovo T420 port
by Iru Cai 05 Oct '15

05 Oct '15

Hi, I'm using the new Lenovo T420 port on gerrit[1] and found a bug about USB(in my post on the gerrit page). And just now I found a work around on this issue. First I tested a USB disk on the buggy USB port before suspending the system, it works fine. Then I unplugged the USB disk, suspended my system, resume, and replugged the disk, the bug occurred. Then I unplugged the disk, reload the ehci_pci module as follows: rmmod ehci_pci modprobe ehci-pci The I plugged in the USB disk, it worked fine again. I think the kernel message[2] gives some information about it, because it gives two different port number on the USB device. But I know almost nothing about USB, so I'm not sure what's happening. [1] http://review.coreboot.org/#/c/11765/ [2] see the attached dmesg.log Iru Cai

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We provide stable Bettong code in github
by WANG Siyuan 05 Oct '15

05 Oct '15

Hi, all coreboot is changing all the time and the patches are reabsed when pushed to community, so it is a little difficult to provide stable Bettong code. >From now on, AMD provides source code which is validated by QA team. The code is pushed to github https://github.com/BTDC/coreboot The version is identified by a tag. All the changes will be pushed to coreboot community. ===== Version: TCMEF1F0 Release Date: 09/29/2015 Changes from last version: 1. Fix external graphics issue. 2. Add board ID support. 3. Support DDR4. 4. Support SD 2.0. 5. Fix Windows 7 S4 issue. 6. Add GPIO, I2C and UART support. 7. Fix the interrupt routine. 8. Restruct PCI interrupt table (C00/C01). 9. Fix DSDT issue. 10. Fix the PCIe lane map. 11. Lower the TOM to give more MMIO space. 12. Add USB device. 13. Set the USB3 port as unremoveable. 14. Update AGESA to CarrizoPI 1.1.0.1. Yours sincerely, WANG Siyuan

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Re: [coreboot] Emergency: Talks needed for coreboot conference in Bonn
by Carl-Daniel Hailfinger 04 Oct '15

04 Oct '15

On 04.10.2015 19:55, ron minnich wrote: > BTW, will you be recording. That's something we've lacked in the past. Um. I didn't think of that, but I like the idea. Not sure where to get some good recording equipment this quickly. Apart from that, it seems like a nice idea, but - each speaker would have to opt in individually - public discussions won't be recorded in any case. regards, Carl-Daniel > ron > > On Sun, Oct 4, 2015 at 6:02 AM Alexander Couzens <lynxis(a)fe80.eu> wrote: > >> Hi, >> >> I would like to give a talk about my embedded controller programming. >> >> And beside that, I would like to have a talk/workshop something, to >> think about the future/roadmap/vision/roadmap name how you like it. >> how coreboot should be in the next year. >> >> Best, >> lynxis >> >> On Fri, 2 Oct 2015 00:20:41 +0200 >> Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> wrote: >> -- >> Alexander Couzens >> >> mail: lynxis(a)fe80.eu >> jabber: lynxis(a)jabber.ccc.de >> mobile: +4915123277221 >> -- >> coreboot mailing list: coreboot(a)coreboot.org >> http://www.coreboot.org/mailman/listinfo/coreboot

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Emergency: Talks needed for coreboot conference in Bonn
by Carl-Daniel Hailfinger 04 Oct '15

04 Oct '15

Hey everyone, due to various reasons, a few speakers can't make it to the conference and thus I have a severe lack of talks and the agenda is starting to look like swiss cheese (holes everywhere). Admittedly I do love swiss cheese (so many delicious kinds of cheese), but for a conference agenda I'd rather like to have less holes. PLEASE PLEASE if you attend the conference PLEASE consider doing a talk about something - anything really - even if it's just three slides and five minutes of talking, followed by lots of discussion from/with the audience. Any proposals (title, duration (talk/discussion), name of speaker, preferred time (morning, noon, afternoon)) are highly appreciated. PLEASE send them to <coreboot-conference(a)bsi.bund.de> ASAP so I can allocate a slot for you. If you can't come but would be willing to donate slides for someone else to do a talk on your behalf, PLEASE tell me at <coreboot-conference(a)bsi.bund.de> or hit me up on IRC. Doing talks remotely via a video conference system of your choice is also an option. THANK YOU! Regards, Carl-Daniel

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coreboot October 2015