coreboot October 2015

coreboot@coreboot.org

44 participants
137 discussions

Re: [coreboot] steps before screen mods
by Stefan Reinauer 19 Oct '15

19 Oct '15

* Mario Goljak <goljak(a)gmail.com> [150925 16:06]: > Hi guys, > > I just came across thinkpad forum thread where people are discuss about > hardware mods for getting FHD screen on lenovo x220/x230 laptops. > http://forum.thinkpads.com/viewtopic.php?f=43&t=106919&start=90 > > What do you guys think, will this affect coreboot at all? Are there any > necessary steps before playing with the screen? You probably want to force your display to digital 2, as well, like in the example pictures on http://letsitbe.jugem.jp/?eid=62 In coreboot you can do that in the int15 handler code, part of the mainboard ramstage code. Stefan

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coreboot ported to the ASUS KGPE-D16 (Libreboot: blobless, fully functional!)
by Timothy Pearson 17 Oct '15

17 Oct '15

All, I have successfully ported coreboot to the relatively modern ASUS KGPE-D16 server board (dual AMD socket G34, 16 DDR3 DIMMs, https://www.asus.com/us/Commercial_Servers_Workstations/KGPED16/)! This port uses native Family 10h initialization (_not_ AGESA or CIMX). The Libreboot folks will be interested to know that this board can run blob-free and still retain full functionality! Port specifications: CPU: Dual AMD G34 Magny-Cours (Family 10h) RAM: 16 DDR3 DIMM slots with ECC support (tested with x4 4G DDR3-1333 unbuffered DIMMs) Peripherals: PCIe slots: all functional PCI slot: functional RS-232: functional PS/2: expected to function, not tested (on SuperIO) ASpeed VGA device: functional (text mode, see below) IEEE1394: functional On-board USB: functional On-board NICs: functional ASUS PIKE SAS controller: functional PCIe ROMs: functional Power management: DDR3 voltage set: functional ACPI/APIC: functional Suspend/resume: broken Other: cbmem console: partial support (log truncated) cbmem timestamps: functional nvram: functional BIOS recovery jumper: functional ASpeed VGA: The ASpeed VGA device initialises in text mode via its (new) coreboot driver, however this initialisation is incomplete, leading to distorted but quite usable VGA output. When Linux boots and engages the graphical framebuffer all distortion disappears. This port was not trivial. Almost every device used was broken and required debugging/repair, with the notable exception of the SuperIO chip. The AMD DDR3 controller was severely broken to the point where large rewrites were needed in order to bring it in line with the BKDG. Even after the various component drivers were repaired Due to the labor-intensive nature of the port and the extensive changes throughout the entire source tree, it is not economically feasible to merge this port upstream at this time (I estimate upward of 30 independent patches would be required just to get the board booting!). Raptor Engineering will, however, be continuing to maintain this port internally, and I am currently looking into adding native Family 15h support on top of this internal tree. Additionally, while it was not a priority for the initial port, I will be attempting to enable suspend/resume functionality as I have time. If there is sufficient interest from the community in adding this board to coreboot I would consider merging the changes in exchange for a one-time contract payment in the vicinity of $35,000 USD. When considering this offer please bear in mind that this is a fully functional blobless board with a wide range of peripherals and expansion options available, and that once these large changes are merged I will continue to enhance coreboot functionality as before (e.g. with the KFSN4-DRE and the T400). I would also be willing to add this board to the test stand as the only fully supported 4-way Opteron board (socket G34 Magny-Cours CPUs contain two separate CPUs in one package, making this 2-socket board a 4-way system from a HyperTransport perspective). Please let me know if you have any questions! -- Timothy Pearson Raptor Engineering +1 (415) 727-8645 http://www.raptorengineeringinc.com

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Re: [coreboot] intel atom e3815
by Testerman, Brett (US COM) 16 Oct '15

16 Oct '15

John, One 'gotcha' of the Minnowboard Max to look out for is based on a GPIO (jumper setting) it will override some of the DRAM settings that you put into your FSP. You probably do not want that. I found it better to use the Baker Sport for ECC designs or the Bayley Bay for non-ECC designs as a starting point with custom hardware. There are a lot of things to consider when trying to boot this chip. One thing I learned the hard way is you do not have to cover the images on the E3800 family (Baytrail-I) and it will boot without the TXE image in the boot flash. But if you leave the TXE out the XDP port is disabled. Brett Long time reader - 1st time posting to this mailing list. Thanks everyone for the support you give so many. From: coreboot [mailto:coreboot-bounces@coreboot.org] On Behalf Of Martin Roth Sent: Friday, October 16, 2015 1:08 PM To: John Cc: coreboot Subject: Re: [coreboot] intel atom e3815 ** Please note that the Sender of this email is from outside the Cobham NA IT Hub ** Hi John, coreboot does support the E3815 (Bay Trail I) with the Intel FSP. The tree is a little broken for it right now, but we're working to get it fixed. The primary example for that chip is the Minnowboard Max. A couple of resources to get you started: - http://intel.com/fsp<http://intel.com/fsp> - There are a number of cocuments in the "Intel Atom processor E3800 product family" section that would apply here. - http://www.apress.com/9781484200711?gtmf=s<http://www.apress.com/9781484200711?gtmf=s> - The Embedded Firmware Solutions book talks specifically about this family of chips If you have any questions about how to get started, the best place to get support might be the coreboot irc channel - #coreboot on freenode.net<http://freenode.net>. https://webchat.freenode.net/?channels=#coreboot<https://webchat.freenode.net/?channels=#coreboot> Martin On Mon, Oct 12, 2015 at 5:58 AM, John <john(a)iwavesystems.com<mailto:john@iwavesystems.com>> wrote: > Hi, > > > > Is the coreboot for intel atom E3815 available? > > > > Best regards, > > John OT > > > -- > coreboot mailing list: coreboot(a)coreboot.org<mailto:coreboot@coreboot.org> > http://www.coreboot.org/mailman/listinfo/coreboot<http://www.coreboot.org/mailman/listinfo/coreboot> -- coreboot mailing list: coreboot(a)coreboot.org<mailto:coreboot@coreboot.org> http://www.coreboot.org/mailman/listinfo/coreboot<http://www.coreboot.org/mailman/listinfo/coreboot>

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intel atom e3815
by John 16 Oct '15

16 Oct '15

Hi, Is the coreboot for intel atom E3815 available? Best regards, John OT

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Patchset up for review to remove external microcode file Kconfig option
by Timothy Pearson 16 Oct '15

16 Oct '15

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 All, I just wanted to alert you to this patchset up for review that removes the built-in Kconfig option to add an external microcode file. As mentioned in the commit message, this option appears to be of decreasing utility due to the recent microcode update streamlining efforts, however as it is a user visible change it was decided that the general community should be involved in the final decision: http://review.coreboot.org/#/c/11903/ I expect this to impact only a small number of users. In any case the desired microcode files(s) can still be added after build via cbfstool (this has been tested here and works well). Thank you! - -- Timothy Pearson Raptor Engineering +1 (415) 727-8645 (direct line) +1 (512) 690-0200 (switchboard) http://www.raptorengineeringinc.com -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org/ iQEcBAEBAgAGBQJWITnsAAoJEK+E3vEXDOFbh4YIAKNrtJuo/NXPnjI4ZfXciAE7 z+OhO1cwDip+/Ta/NbxTfc3xxCuGn38aOu3cWXCmOtWn2wXAsiGMQNdt+yFn6KOK a+hvy1IU4yuE5ULk1zCZ1SmkGuANzRQJIX2u09Q56h0xez8Sl/2Rt2M8TXvUYulk wIoxglPi6mIZ0VveAA28m4xKZ+KUvgJ8RS6mjmy7tKVe40ZZHvS/YczyYJL/j3ql dSs2XWBNsjKulLJqomryRv5OMyQUifpFaW1EuqMFfwfzTk3rzsukin/h3XPkuXwD L8jQhzj9O6Fcut5js5SqEIVIEwZN/Dy/agTFRD+Opn1Q6xwLZ1aBQ/jGciln3Kk= =OigL -----END PGP SIGNATURE-----

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Moving forward with armv7: Word-sized/half-word-sized memory operations for 32/16 bit read/write
by Paul Kocialkowski 15 Oct '15

15 Oct '15

For nearly a month, a few people (includign myself) have been arguing over http://review.coreboot.org/#/c/11698/ So far, we've investigated two solutions: * inline assembly * __builtin_assume_aligned builtin Each solution has its pros and cons, I'm not going to move that discussion here. However, I would like to suggest another solution: reverting the toolchain built by crossgcc-arm to GCC 4.9.0, where everything works fine. That would only be for ARM, since GCC 4.9.0 apparently breaks RISC-V support and wasn't reported to misbehave on other architectures. I wish to use the toolchain for rebuilding the cros EC firmware (especially important for libreboot) and GCC 5.2.0 is causing run-time errors that are apparently not even of the same nature as the problem discussed in code review. Would this be an agreeable solution until everything is sorted out in gcc upstream? -- Paul Kocialkowski, Replicant developer Replicant is a fully free Android distribution running on several devices, a free software mobile operating system putting the emphasis on freedom and privacy/security. Website: https://www.replicant.us/ Blog: https://blog.replicant.us/ Wiki/tracker/forums: https://redmine.replicant.us/

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ASUS KFSN4-DRE Automated Test Failure
by Raptor Engineering Automated Coreboot Test Stand 15 Oct '15

15 Oct '15

The ASUS KFSN4-DRE fails verification as of commit 58562405c8c416a415652516b8af31b204b4ff0d The following tests failed: VIDEO_FAILURE Commits since last successful test: 5856240 Revert "Remove FSP Rangeley SOC and mohonpeak board support" See attached log for details This message was automatically generated from Raptor Engineering's ASUS KFSN4-DRE test stand Want to test on your own equipment? Check out https://www.raptorengineeringinc.com/content/REACTS/intro.html Raptor Engineering also offers coreboot consulting services! Please visit https://www.raptorengineeringinc.com for more information Please contact Timothy Pearson at Raptor Engineering <tpearson(a)raptorengineeringinc.com> regarding any issues stemming from this notification

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Re: [coreboot] Rangeley SoC FSP and Mohon Peak board support
by Alex G. 14 Oct '15

14 Oct '15

Hi David, Martin suggested that we make this a standalone patch, so I've moved the update to MAINTAINERS here [1]. [1] http://review.coreboot.org/11894 When is the FSP1.0 microcode handling patch expected to reach gerrit code review on coreboot.org? Alex On 10/13/2015 03:04 AM, Guckian, David wrote: > Hi Alex, > > As per our chat yesterday with CSIG and IOTG: > Fei Wang (Wang, Fei Z <fei.z.wang(a)intel.com>) and myself will be maintainers for Rangeley/Mohon Peak. > Jin Huang and York Yang will be maintainers for FSP1.0 & FSP1.1. > Andrey Petrov will also be maintainer for FSP1.1. > > Thanks. > David. > > -----Original Message----- > From: Alex G. [mailto:mr.nuke.me@gmail.com] > Sent: Tuesday, October 13, 2015 5:14 AM > To: Guckian, David; coreboot(a)coreboot.org; gaumless(a)gmail.com > Subject: Re: Rangeley SoC FSP and Mohon Peak board support > > Hi David, > > We had some chats today with CSG and IOTG teams, and from what I understood Huang Jin, and York Yang wanted to be the maintainers. If that changed, that's fine. We've started the process [1] of re-merging Rangeley [1], but we need confirmation on who the maintainers [2] are going to be. > > Alex > > [1] http://review.coreboot.org/11860 > [2] http://review.coreboot.org/#/c/11860/3/MAINTAINERS > > On 10/12/2015 10:55 AM, Guckian, David wrote: >> Hi, >> >> >> >> I saw recently that Rangeley SoC FSP and Mohon Peak board support has >> been removed from Coreboot. >> >> One of the reasons for the removal is that this is not used by anyone. >> >> That is not the case as there are users of this SoC and board. >> >> I have tested out a patch on Mohon Peak that will enable us to easily >> integrate with the latest microcode infrastructure. >> >> Going forward I can be the maintainer for Rangeley / Mohon Peak. >> >> I would like to work with the community to get this code added back in >> to Coreboot. >> >> A patch will be forthcoming in gerrit for your review. >> >> Thanks. >> >> >> >> Regards, >> >> David >> >> >> >> >> >> -------------------------------------------------------------- >> Intel Shannon Limited >> Registered in Ireland >> Registered Office: Collinstown Industrial Park, Leixlip, County >> Kildare Registered Number: 308263 Business address: Dromore House, >> East Park, Shannon, Co. Clare >> >> This e-mail and any attachments may contain confidential material for >> the sole use of the intended recipient(s). Any review or distribution >> by others is strictly prohibited. If you are not the intended >> recipient, please contact the sender and delete all copies. >> > -------------------------------------------------------------- > Intel Shannon Limited > Registered in Ireland > Registered Office: Collinstown Industrial Park, Leixlip, County Kildare > Registered Number: 308263 > Business address: Dromore House, East Park, Shannon, Co. Clare > > This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. If you are not the intended recipient, please contact the sender and delete all copies. > >

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Possible work from home coreboot developer position
by Alex G. 14 Oct '15

14 Oct '15

I got a call yesterday from a staffing company about a coreboot position with AMD's Austin, Texas office. It's a work-from-home, 12 month contract with something to do with "AMD embedded processors". That's all I know. I turned down the guy, because I've got my own plate full of exciting coreboot adventures, but I promised the guy I'll ask around. If that sounds like something you might want you do, and the following apply to you, drop me an email: * you spell coreboot with a lowercase "c" * you use git * you use an external programmer * you don't think of a california city when people say "pomona" * you have fried at least one CPU, chipset, and memory module * you have submitted contributions to coreboot in the past Funny remarks aside, I'll get you and the recruiter in contact. I can't promise anything beyond that. Alex

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Re: [coreboot] Rangeley SoC FSP and Mohon Peak board support
by Alexander Couzens 13 Oct '15

13 Oct '15

Hi David, that's great! Welcome to the coreboot. Best, Alex -- Alexander Couzens mail: lynxis(a)fe80.eu jabber: lynxis(a)jabber.ccc.de mobile: +4915123277221

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coreboot October 2015