coreboot March 2014

coreboot@coreboot.org

57 participants
180 discussions

Re: [coreboot] Hey
by Stefan Reinauer 20 Mar '14

20 Mar '14

* Shant Kehyeian <skehyeian(a)gmail.com> [140320 12:12]: > Hello, > I have Samsung ARM chromebook series 3 "Snow" and I am trying to flesh it and > change the boot process. > So I build a coreboot.rom for that, but before I start to do that I would like > to ask about the payload. When I did the "make menuconfig" it wasn't by default > the SeaBios., there wasn't at all ...there was GRUB 2 and I selected it...so My > question is would it work as SeaBios to boot from usb ? > Thank you. Chances are, that your only option for a payload on ARM is depthcharge right now (living in the Chromium OS repository). I started a FILO port a while ago (see gerrit) but it doesn't even compile yet. Stefan

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GSoC 2014
by Allen Yan 20 Mar '14

20 Mar '14

Hi, coreboot+seabios running in QEMU output: coreboot-4.0-5656-gb34739b Thu Mar 13 10:37:43 CST 2014 starting... CBMEM region 3fee0000-3fffffff (cbmem_check_toc) CBMEM region 3fee0000-3fffffff (cbmem_initialize_empty) Adding CBMEM entry as no. 1 Adding CBMEM entry as no. 2 Trying CBFS ramstage loader. CBFS: loading stage fallback/coreboot_ram @ 0x100000 (180280 bytes), entry @ 0x100000 QEMU debugcon not found [port 0x402] coreboot-4.0-5656-gb34739b Thu Mar 13 10:37:43 CST 2014 booting... Enumerating buses... Show all devs...Before device enumeration. Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 DOMAIN: 0000: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:01.0: enabled 1 PCI: 00:01.1: enabled 1 PCI: 00:01.3: enabled 1 Compare with tree... Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 DOMAIN: 0000: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:01.0: enabled 1 PCI: 00:01.1: enabled 1 PCI: 00:01.3: enabled 1 scan_static_bus for Root Device CPU_CLUSTER: 0 enabled DOMAIN: 0000 enabled CPU_CLUSTER: 0 scanning... QEMU: firmware config interface detected QEMU: max_cpus is 1 CPU: APIC: 00 enabled DOMAIN: 0000 scanning... PCI: pci_scan_bus for bus 00 PCI: 00:00.0 [8086/1237] ops PCI: 00:00.0 [8086/1237] enabled PCI: 00:01.0 [8086/7000] bus ops PCI: 00:01.0 [8086/7000] enabled PCI: 00:01.1 [8086/7010] ops PCI: 00:01.1 [8086/7010] enabled PCI: 00:01.3 [8086/7113] bus ops Wakeup from ACPI sleep type S5 (PMCNTRL=0000) PCI: 00:01.3 [8086/7113] enabled PCI: 00:02.0 [1013/00b8] ops PCI: 00:02.0 [1013/00b8] enabled PCI: 00:03.0 [8086/100e] enabled scan_static_bus for PCI: 00:01.0 scan_static_bus for PCI: 00:01.0 done scan_static_bus for PCI: 00:01.3 scan_static_bus for PCI: 00:01.3 done PCI: pci_scan_bus returning with max=001 scan_static_bus for Root Device done done found VGA at PCI: 00:02.0 Setting up VGA for PCI: 00:02.0 Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device Allocating resources... Reading resources... Root Device read_resources bus 0 link: 0 CPU_CLUSTER: 0 read_resources bus 0 link: 0 APIC: 00 missing read_resources CPU_CLUSTER: 0 read_resources bus 0 link: 0 done QEMU: 5 files in fw_cfg QEMU: etc/boot-fail-wait [size=4] QEMU: genroms/kvmvapic.bin [size=9216] QEMU: etc/system-states [size=6] QEMU: etc/pvpanic-port [size=2] QEMU: bootorder [size=0] QEMU: cmos: 1024 MiB RAM below 4G. QEMU: cmos: 0 MiB RAM above 4G. QEMU: reserve ioports 0x0510-0x0511 [firmware-config] QEMU: reserve ioports 0x5658-0x5658 [vmware-port] QEMU: reserve ioports 0xae00-0xae0f [pci-hotplug] QEMU: reserve ioports 0xaf00-0xaf1f [cpu-hotplug] QEMU: reserve ioports 0xafe0-0xafe3 [piix4-gpe0] CBMEM region 3fee0000-3fffffff (cbmem_late_set_table) DOMAIN: 0000 read_resources bus 0 link: 0 DOMAIN: 0000 read_resources bus 0 link: 0 done Root Device read_resources bus 0 link: 0 done Done reading resources. Show resources in subtree (Root Device)...After reading. Root Device child on link 0 CPU_CLUSTER: 0 CPU_CLUSTER: 0 child on link 0 APIC: 00 APIC: 00 DOMAIN: 0000 child on link 0 PCI: 00:00.0 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100 DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index a DOMAIN: 0000 resource base c0000 size 3ff40000 align 0 gran 0 limit 0 flags e0004200 index b DOMAIN: 0000 resource base 510 size 2 align 0 gran 0 limit ffff flags e0000100 index c DOMAIN: 0000 resource base 5658 size 1 align 0 gran 0 limit ffff flags e0000100 index d DOMAIN: 0000 resource base ae00 size 10 align 0 gran 0 limit ffff flags e0000100 index e DOMAIN: 0000 resource base af00 size 20 align 0 gran 0 limit ffff flags e0000100 index f DOMAIN: 0000 resource base afe0 size 4 align 0 gran 0 limit ffff flags e0000100 index 10 DOMAIN: 0000 resource base fec00000 size 100000 align 0 gran 0 limit ffffffff flags e0000200 index 2 DOMAIN: 0000 resource base fee00000 size 10000 align 0 gran 0 limit ffffffff flags e0000200 index 3 PCI: 00:00.0 PCI: 00:01.0 PCI: 00:01.0 resource base 0 size 1000 align 0 gran 0 limit ffff flags c0000100 index 1 PCI: 00:01.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags d0000200 index 2 PCI: 00:01.1 PCI: 00:01.1 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20 PCI: 00:01.3 PCI: 00:01.3 resource base e400 size 40 align 0 gran 0 limit ffff flags d0000100 index 1 PCI: 00:01.3 resource base f00 size 10 align 0 gran 0 limit ffff flags d0000100 index 2 PCI: 00:02.0 PCI: 00:02.0 resource base 0 size 2000000 align 25 gran 25 limit ffffffff flags 1200 index 10 PCI: 00:02.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 14 PCI: 00:02.0 resource base 0 size 10000 align 16 gran 16 limit ffffffff flags 2200 index 30 PCI: 00:03.0 PCI: 00:03.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 200 index 10 PCI: 00:03.0 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 index 14 PCI: 00:03.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 2200 index 30 DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0 limit: ffff PCI: 00:03.0 14 * [0x0 - 0x3f] io PCI: 00:01.1 20 * [0x40 - 0x4f] io DOMAIN: 0000 compute_resources_io: base: 50 size: 50 align: 6 gran: 0 limit: ffff done DOMAIN: 0000 compute_resources_mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff PCI: 00:02.0 10 * [0x0 - 0x1ffffff] prefmem PCI: 00:03.0 10 * [0x2000000 - 0x201ffff] mem PCI: 00:03.0 30 * [0x2020000 - 0x203ffff] mem PCI: 00:02.0 30 * [0x2040000 - 0x204ffff] mem PCI: 00:02.0 14 * [0x2050000 - 0x2050fff] mem DOMAIN: 0000 compute_resources_mem: base: 2051000 size: 2051000 align: 25 gran: 0 limit: ffffffff done avoid_fixed_resources: DOMAIN: 0000 avoid_fixed_resources:@DOMAIN: 0000 10000000 limit 0000ffff avoid_fixed_resources:@DOMAIN: 0000 10000100 limit ffffffff constrain_resources: DOMAIN: 0000 constrain_resources: PCI: 00:00.0 constrain_resources: PCI: 00:01.0 constrain_resources: PCI: 00:01.1 constrain_resources: PCI: 00:01.3 constrain_resources: PCI: 00:02.0 constrain_resources: PCI: 00:03.0 avoid_fixed_resources2: DOMAIN: 0000@10000000 limit 0000ffff lim->base 00005659 lim->limit 0000adff avoid_fixed_resources2: DOMAIN: 0000@10000100 limit ffffffff lim->base 40000000 lim->limit febfffff Setting resources... DOMAIN: 0000 allocate_resources_io: base:5659 size:50 align:6 gran:0 limit:adff Assigned: PCI: 00:03.0 14 * [0x5800 - 0x583f] io Assigned: PCI: 00:01.1 20 * [0x5840 - 0x584f] io DOMAIN: 0000 allocate_resources_io: next_base: 5850 size: 50 align: 6 gran: 0 done DOMAIN: 0000 allocate_resources_mem: base:fc000000 size:2051000 align:25 gran:0 limit:febfffff Assigned: PCI: 00:02.0 10 * [0xfc000000 - 0xfdffffff] prefmem Assigned: PCI: 00:03.0 10 * [0xfe000000 - 0xfe01ffff] mem Assigned: PCI: 00:03.0 30 * [0xfe020000 - 0xfe03ffff] mem Assigned: PCI: 00:02.0 30 * [0xfe040000 - 0xfe04ffff] mem Assigned: PCI: 00:02.0 14 * [0xfe050000 - 0xfe050fff] mem DOMAIN: 0000 allocate_resources_mem: next_base: fe051000 size: 2051000 align: 25 gran: 0 done Root Device assign_resources, bus 0 link: 0 DOMAIN: 0000 assign_resources, bus 0 link: 0 PCI: 00:01.1 20 <- [0x0000005840 - 0x000000584f] size 0x00000010 gran 0x04 io PCI: 00:02.0 10 <- [0x00fc000000 - 0x00fdffffff] size 0x02000000 gran 0x19 prefmem PCI: 00:02.0 14 <- [0x00fe050000 - 0x00fe050fff] size 0x00001000 gran 0x0c mem PCI: 00:02.0 30 <- [0x00fe040000 - 0x00fe04ffff] size 0x00010000 gran 0x10 romem PCI: 00:03.0 10 <- [0x00fe000000 - 0x00fe01ffff] size 0x00020000 gran 0x11 mem PCI: 00:03.0 14 <- [0x0000005800 - 0x000000583f] size 0x00000040 gran 0x06 io PCI: 00:03.0 30 <- [0x00fe020000 - 0x00fe03ffff] size 0x00020000 gran 0x11 romem DOMAIN: 0000 assign_resources, bus 0 link: 0 Root Device assign_resources, bus 0 link: 0 Done setting resources. Show resources in subtree (Root Device)...After assigning values. Root Device child on link 0 CPU_CLUSTER: 0 CPU_CLUSTER: 0 child on link 0 APIC: 00 APIC: 00 DOMAIN: 0000 child on link 0 PCI: 00:00.0 DOMAIN: 0000 resource base 5659 size 50 align 6 gran 0 limit adff flags 40040100 index 10000000 DOMAIN: 0000 resource base fc000000 size 2051000 align 25 gran 0 limit febfffff flags 40040200 index 10000100 DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index a DOMAIN: 0000 resource base c0000 size 3ff40000 align 0 gran 0 limit 0 flags e0004200 index b DOMAIN: 0000 resource base 510 size 2 align 0 gran 0 limit ffff flags e0000100 index c DOMAIN: 0000 resource base 5658 size 1 align 0 gran 0 limit ffff flags e0000100 index d DOMAIN: 0000 resource base ae00 size 10 align 0 gran 0 limit ffff flags e0000100 index e DOMAIN: 0000 resource base af00 size 20 align 0 gran 0 limit ffff flags e0000100 index f DOMAIN: 0000 resource base afe0 size 4 align 0 gran 0 limit ffff flags e0000100 index 10 DOMAIN: 0000 resource base fec00000 size 100000 align 0 gran 0 limit ffffffff flags e0000200 index 2 DOMAIN: 0000 resource base fee00000 size 10000 align 0 gran 0 limit ffffffff flags e0000200 index 3 PCI: 00:00.0 PCI: 00:01.0 PCI: 00:01.0 resource base 0 size 1000 align 0 gran 0 limit ffff flags c0000100 index 1 PCI: 00:01.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags d0000200 index 2 PCI: 00:01.1 PCI: 00:01.1 resource base 5840 size 10 align 4 gran 4 limit adff flags 60000100 index 20 PCI: 00:01.3 PCI: 00:01.3 resource base e400 size 40 align 0 gran 0 limit ffff flags d0000100 index 1 PCI: 00:01.3 resource base f00 size 10 align 0 gran 0 limit ffff flags d0000100 index 2 PCI: 00:02.0 PCI: 00:02.0 resource base fc000000 size 2000000 align 25 gran 25 limit febfffff flags 60001200 index 10 PCI: 00:02.0 resource base fe050000 size 1000 align 12 gran 12 limit febfffff flags 60000200 index 14 PCI: 00:02.0 resource base fe040000 size 10000 align 16 gran 16 limit febfffff flags 60002200 index 30 PCI: 00:03.0 PCI: 00:03.0 resource base fe000000 size 20000 align 17 gran 17 limit febfffff flags 60000200 index 10 PCI: 00:03.0 resource base 5800 size 40 align 6 gran 6 limit adff flags 60000100 index 14 PCI: 00:03.0 resource base fe020000 size 20000 align 17 gran 17 limit febfffff flags 60002200 index 30 Done allocating resources. Enabling resources... PCI: 00:00.0 cmd <- 00 PCI: 00:01.0 cmd <- 00 PCI: 00:01.1 cmd <- 01 PCI: 00:01.3 cmd <- 00 PCI: 00:02.0 cmd <- 03 PCI: 00:03.0 cmd <- 03 done. Initializing devices... Root Device init CPU_CLUSTER: 0 init Initializing CPU #0 CPU: vendor Intel device 633 CPU: family 06, model 03, stepping 03 CPU #0 initialized PCI: 00:00.0 init Keyboard init... Assigning IRQ 10 to 0:1.3 i8259_configure_irq_trigger: current interrupts are 0x0 i8259_configure_irq_trigger: try to set interrupts 0x400 Assigning IRQ 11 to 0:3.0 i8259_configure_irq_trigger: current interrupts are 0x400 i8259_configure_irq_trigger: try to set interrupts 0xc00 PCI: 00:01.0 init RTC Init PCI: 00:01.1 init IDE: Primary IDE interface: on IDE: Secondary IDE interface: on IDE: Access to legacy IDE ports: off PCI: 00:02.0 init PCI: 00:03.0 init Devices initialized Show all devs...After init. Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 DOMAIN: 0000: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:01.0: enabled 1 PCI: 00:01.1: enabled 1 PCI: 00:01.3: enabled 1 PCI: 00:02.0: enabled 1 PCI: 00:03.0: enabled 1 CPU: 00: enabled 1 CBMEM region 3fee0000-3fffffff (cbmem_check_toc) Adding CBMEM entry as no. 3 Moving GDT to 3fee0600...ok Finalize devices... Devices finalized Copying Interrupt Routing Table to 0x000f0000... done. Adding CBMEM entry as no. 4 Copying Interrupt Routing Table to 0x3fee0800... done. PIRQ table: 128 bytes. Adding CBMEM entry as no. 5 ACPI: Writing ACPI tables at 3fee1800. ACPI: * HPET ACPI: added table 1/32, length now 40 ACPI: * MADT ACPI: added table 2/32, length now 44 ACPI: * MCFG ACPI: added table 3/32, length now 48 ACPI: * FACS ACPI: * DSDT @ 3fee1b20 Length fa0 ACPI: * FADT ACPI: added table 4/32, length now 52 ACPI: * SSDT Found 1 CPU(s). ACPI: added table 5/32, length now 56 current = 3fee2c00 ACPI: done. ACPI tables: 5120 bytes. Adding CBMEM entry as no. 6 smbios_write_tables: 3feecc00 Root Device (Emulation QEMU x86 i440fx/piix4) CPU_CLUSTER: 0 (QEMU Northbridge i440fx) APIC: 00 (unknown) DOMAIN: 0000 (QEMU Northbridge i440fx) PCI: 00:00.0 (QEMU Northbridge i440fx) PCI: 00:01.0 (Intel 82371FB/SB/MX/AB/EB/MB Southbridge) PCI: 00:01.1 (Intel 82371FB/SB/MX/AB/EB/MB Southbridge) PCI: 00:01.3 (Intel 82371FB/SB/MX/AB/EB/MB Southbridge) PCI: 00:02.0 (unknown) PCI: 00:03.0 (unknown) CPU: 00 (unknown) SMBIOS tables: 438 bytes. Adding CBMEM entry as no. 7 Adding CBMEM entry as no. 8 Writing table forward entry at 0x00000500 Wrote coreboot table at: 00000500, 0x10 bytes, checksum ebdf Table forward entry ends at 0x00000528. ... aligned to 0x00001000 Writing coreboot table at 0x3ffed400 rom_table_end = 0x3ffed400 ... aligned to 0x3fff0000 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES 1. 0000000000001000-000000000009ffff: RAM 2. 00000000000c0000-000000003fedffff: RAM 3. 000000003fee0000-000000003fffffff: CONFIGURATION TABLES 4. 00000000ff800000-00000000ffffffff: RESERVED Wrote coreboot table at: 3ffed400, 0x1f0 bytes, checksum 9a59 coreboot table: 520 bytes. FREE SPACE 0. 3fff5400 0000ac00 CAR GLOBALS 1. 3fee0200 00000200 ROMSTAGE 2. 3fee0400 00000200 GDT 3. 3fee0600 00000200 IRQ TABLE 4. 3fee0800 00001000 ACPI 5. 3fee1800 0000b400 SMBIOS 6. 3feecc00 00000800 ACPI RESUME 7. 3feed400 00100000 COREBOOT 8. 3ffed400 00008000 CBFS: located payload @ fffdadb8, 52477 bytes. Loading segment from rom address 0xfffdadb8 code (compression=1) New segment dstaddr 0xe6b30 memsize 0x194d0 srcaddr 0xfffdadf0 filesize 0xccc5 (cleaned up) New segment addr 0xe6b30 size 0x194d0 offset 0xfffdadf0 filesize 0xccc5 Loading segment from rom address 0xfffdadd4 Entry Point 0x000fc7a8 Bounce Buffer at 3fe87000, 360560 bytes Loading Segment: addr: 0x00000000000e6b30 memsz: 0x00000000000194d0 filesz: 0x000000000000ccc5 lb: [0x0000000000100000, 0x000000000012c038) Post relocation: addr: 0x00000000000e6b30 memsz: 0x00000000000194d0 filesz: 0x000000000000ccc5 using LZMA [ 0x000e6b30, 00100000, 0x00100000) <- fffdadf0 dest 000e6b30, end 00100000, bouncebuffer 3fe87000 Loaded segments Jumping to boot code at 000fc7a8 CPU0: stack: 00127000 - 00128000, lowest used address 00127b3c, stack used: 1220 bytes entry = 0x000fc7a8 lb_start = 0x00100000 lb_size = 0x0002c038 buffer = 0x3fe87000 Start bios (version rel-1.7.2.1-0-g88cb66e-20140313_103801-lexkde-desktop) Found mainboard Emulation QEMU x86 i440fx/piix4 Ram Size=0x3fee0000 (0x0000000000000000 high) Relocating low data from 0x000e73e0 to 0x000ef790 (size 2153) Relocating init from 0x000e7c49 to 0x3fec6070 (size 40555) Found CBFS header at 0xfffffc30 CPU Mhz=2674 Found 6 PCI devices (max PCI bus is 00) Found 1 cpu(s) max supported 1 cpu(s) Copying PIR from 0x3fee0800 to 0x000fdb70 Copying ACPI RSDP from 0x3fee1800 to 0x000fdb40 Copying SMBIOS entry point from 0x3feecc00 to 0x000fdb20 Scan for VGA option rom Running option rom at c000:0003 Turning on vga text mode console SeaBIOS (version rel-1.7.2.1-0-g88cb66e-20140313_103801-lexkde-desktop) Found 1 lpt ports Found 1 serial ports ATA controller 1 at 1f0/3f4/0 (irq 14 dev 9) ATA controller 2 at 170/374/0 (irq 15 dev 9) ata0-0: QEMU HARDDISK ATA-7 Hard-Disk (8000 MiBytes) Searching bootorder for: /pci@i0cf8/*@1,1/drive@0/disk@0 DVD/CD [ata1-0: QEMU DVD-ROM ATAPI-4 DVD/CD] Searching bootorder for: /pci@i0cf8/*@1,1/drive@1/disk@0 PS2 keyboard initialized All threads complete. Scan for option roms Running option rom at c900:0003 pmm call arg1=1 pmm call arg1=0 pmm call arg1=1 pmm call arg1=0 Searching bootorder for: /pci@i0cf8/*@3 Press F12 for boot menu. Searching bootorder for: HALT drive 0x000fdad0: PCHS=16253/16/63 translation=lba LCHS=1019/255/63 s=16384000 Space available for UMB: 000ca000-000ee800 Returned 65536 bytes of ZoneHigh e820 map has 6 items: 0: 0000000000000000 - 000000000009fc00 = 1 RAM 1: 000000000009fc00 - 00000000000a0000 = 2 RESERVED 2: 00000000000f0000 - 0000000000100000 = 2 RESERVED 3: 0000000000100000 - 000000003fee0000 = 1 RAM 4: 000000003fee0000 - 0000000040000000 = 2 RESERVED 5: 00000000ff800000 - 0000000100000000 = 2 RESERVED enter handle_19: NULL Booting from DVD/CD... Device reports MEDIUM NOT PRESENT scsi_is_ready returned -1 Boot failed: Could not read from CDROM (code 0003) enter handle_18: NULL Booting from Hard Disk... Booting from 0000:7c00

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Re: [coreboot] GSoC-2014 Coreboot project
by mrnuke 20 Mar '14

20 Mar '14

On Thursday, March 20, 2014 09:36:06 AM ron minnich wrote: > >> How about, "all of them" at one time or another. One vendor had an > >> internal memo stating that anyone who talked to me (my name was on it) > >> about LinuxBIOS would be terminated. > > > > You're popular it seems. How about within this decade (last 4 years) ? > > > > Alex > > it's a continuing problem that I doubt will ever be fully resolved, > since as you may have noticed there is no QPI support yet. > Not sure I care much about Intel nowadays. They are already part of the "fellatio_admin" group in my books. Alex

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Re: [coreboot] GSoC-2014 Coreboot project
by mrnuke 20 Mar '14

20 Mar '14

On Thursday, March 20, 2014 09:08:18 AM ron minnich wrote: > On Thu, Mar 20, 2014 at 8:36 AM, mrnuke <mr.nuke.me(a)gmail.com> wrote: > > BTW, has any manufacturer been hostile in the past in any way relating to > > coreboot supporting hardware they would rather have kept closed/secret? > > ha ha ha ha ha ha ha ha ha ha ha haha ha ha ha ha haha ha ha ha ha > haha ha ha ha ha haha ha ha ha ha haha ha ha ha ha ha > > you're killing me. > > How about, "all of them" at one time or another. One vendor had an > internal memo stating that anyone who talked to me (my name was on it) > about LinuxBIOS would be terminated. > That seems like a slap on the wrist. Terminating employees rather than taking legal action against coreboot also suggests they might feel they have no legal standing against coreboot supporting more stuff. I wonder if there's any legal action hardware vendors could take against ODM/OEM vendors who distribute and/or contribute to coreboot. And I don't mean BS lawsuits hw vendors know they'll lose. Alex

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Re: [coreboot] GSoC-2014 Coreboot project
by mrnuke 20 Mar '14

20 Mar '14

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Re: [coreboot] GSoC-2014 Coreboot project
by mrnuke 20 Mar '14

20 Mar '14

On Thursday, March 20, 2014 08:30:58 AM ron minnich wrote: > in the proposal. We'll deal with other issues later. > > The guy that gave us the first real CAR implementation was an intel > employee who had NDAs out the ... > > > and it was not an issue. > > Let's not start putting in roadblocks. We're not lawyers. > BTW, has any manufacturer been hostile in the past in any way relating to coreboot supporting hardware they would rather have kept closed/secret? Alex

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Re: [coreboot] GSoC-2014 Coreboot project
by mrnuke 20 Mar '14

20 Mar '14

Hi Allen, There's less than 24 hours left to submit proposals. If you want to do this, I suggest you get your proposal up before the deadline (March 21st). While I do not know the details of your employment contract with ASUS, I find it irrelevant for the purpose of you working on coreboot. Does it prevent you from submitting a proposal? Most likely not. Come hang out with us on IRC (#coreboot @ freenode). You can brainstorm, discuss ideas with us, get a better idea of what you'll get to work on, etc... <hint> I cannot stress the importance of being in constant contact with the community </hint>. Alex

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Re: [coreboot] coreboot GSoC 2014 - Student Application period is open
by Marc Jones 20 Mar '14

20 Mar '14

On Mon, Mar 10, 2014 at 2:21 PM, Marc Jones <marcj303(a)gmail.com> wrote: > Students: > The GSoC application period has started. Applications are due by March > 21 at 19:00 UTC. > > https://www.google-melange.com/gsoc/org2/google/gsoc2014/coreboot > http://www.coreboot.org/GSoC#coreboot_Summer_of_Code_Application A reminder that the GSoC application window is closing March 21 at 19:00 UTC. Please get your application in. Regards, Marc -- http://se-eng.com

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Re: [coreboot] GSoC-2014 Coreboot project
by Vladimir 'φ-coder/phcoder' Serbinenko 20 Mar '14

20 Mar '14

On 20.03.2014 11:25, Allen Yan wrote: > Hi, David, > When at AsusTek Suzhou, my work is mainly responsible for bios > porting and fixing bug. There were four mainboards P5KPL-S, P5QL-E, > P5QL-SE, P5QL. All based on Intel platform and AMI Legacy BIOS Core > In the second half year of 2008, I worked on pre-development of > EFI-BIOS for ASUS mainboard. I wrote a Dual bootblock module and added > NTFS support(read only) for AutoRecovery module using AMI Apito > platform (based on EFI). > Do I understand it correctly, that you've had access to proprietary BIOS code? If so which papers did you sign and under what license did you get them? Depending on the answers it may partially or fully disqualify you from contributing to coreboot. > Interesting experience, but memories will fade! Details can't be > remembered clearly. > >> As Vladimir said, if the chipset is unsupported then writing MRC for it will be a very long and difficult process. If the chipset is supported then adding mainboard support may be a relatively simple task that not sufficient for GSoC. > Do we need to write MRC by ourselves in coreboot? Isn't MRC code > supported by Intel? > >> If you have experience with UEFI, perhaps you can implement features that are missing in our Tianocore support: http://www.coreboot.org/TianoCore . > > Implementing UEFI CBFS driver and GOP driver are very clear goal. > questions: I don't know whether coreboot or some payload implement > common flash interface for flash programming software. If not, why? > >> https://trello.com/b/pEdlwYTb/tiano-payload > It seems that Tiano payload is a very activity project. I think I can > try my best to implement one feature or twp for the project! Like use > a seperate Fv in CBFS as Fault Tolerant Variable Storage > > Look forward to your kind advice! > > > > On 3/20/14, David Hendricks <dhendrix(a)google.com> wrote: >> Hi Jinyi, >> Can you provide more details about your work as a BIOS engineer? >> >> As Vladimir said, if the chipset is unsupported then writing MRC for it >> will be a very long and difficult process. If the chipset is supported then >> adding mainboard support may be a relatively simple task that not >> sufficient for GSoC. >> >> If you have experience with UEFI, perhaps you can implement features that >> are missing in our Tianocore support: http://www.coreboot.org/TianoCore . >> >> >> On Wed, Mar 19, 2014 at 6:06 AM, Allen Yan <lexkde(a)gmail.com> wrote: >> >>> Hi, >>> I am Jinyi Yan , a second year PhD candidate from Shanghai Institute >>> of Micro-system and Information Technology, Chinese Academy of >>> Sciences. I used to be a mainboard BIOS engineer in ASUS Technology >>> Suzhou Co., Ltd for about two years (2007.7~2009.2). My major now is >>> optoelectronics. But I have a lot of fun while programming, in my >>> heart the working experience of being a BIOS engineer is still very >>> exciting. >>> I think GsoC is a nice platform for me to participate the open source >>> community. When I search the GsoC projects and organizations, the >>> coreboot and flashrom projects are definitely the right choices for >>> me. I have a spare ASUS P5KPL PC at my hand, but the chipset is not in >>> the support list of coreboot project. >>> As Stefan Tauner's suggestion, maybe porting coreboot to new mainboard >>> or implementing advanced coreboot features on exsiting mainboards are >>> nice too. >>> Now I'm not very familiar with the program structure of coreboot, so I >>> expect your guidence and hope to contribute for coreboot and flashrom >>> even if my application is not accpeted. >>> Thanks! Look forward to your kind advice! >>> Regards, >>> Jinyi Yan >>> >>> -- >>> coreboot mailing list: coreboot(a)coreboot.org >>> http://www.coreboot.org/mailman/listinfo/coreboot >>> >> >> >> >> -- >> David Hendricks (dhendrix) >> Systems Software Engineer, Google Inc. >> >

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Re: [coreboot] Hey
by Vladimir 'φ-coder/phcoder' Serbinenko 20 Mar '14

20 Mar '14

On 20.03.2014 13:34, Shant Kehyeian wrote: > No I just gave in menuconfig the snow board ...and then as a payload I > chose the GRUB2...that's what I meant ...:) > Keep list CC'ed. I'm surprised it compiled at all. It should have error'ed out. > > On Thu, Mar 20, 2014 at 12:31 PM, Vladimir 'φ-coder/phcoder' Serbinenko > <phcoder(a)gmail.com <mailto:phcoder@gmail.com>> wrote: > > On 20.03.2014 13:27, Shant Kehyeian wrote: > > Yess you are saying it right... > > So I installed the coreboot source code and I compiled it with > GRUB2 so > > ...Do you think that I will get the grub options while the boot > process ? > > Thank you... > > > I don't know how you managed to compile GRUB2 for ARM coreboot but it's > unlikely to work. I'm under impression that you compile for wrong > mainboard altogether (you've chosen mobo in make menuconfig, right?) > > > > On Thu, Mar 20, 2014 at 12:23 PM, Vladimir 'φ-coder/phcoder' > Serbinenko > > <phcoder(a)gmail.com <mailto:phcoder@gmail.com> > <mailto:phcoder@gmail.com <mailto:phcoder@gmail.com>>> wrote: > > > > On 20.03.2014 13:10, Shant Kehyeian wrote: > > > In fact I do need the SeaBios not the GRUB2 to be able to boot > > from usb > > > with live CD which I can format and install my preferred OS... > > > > > I think you're missing the "ARM" part. Only ARM distros have > any chance > > to work. Given fragmentation of ARM it may even mean that only > > Linux-based works on your machine. > > > > > > On Thu, Mar 20, 2014 at 4:05 PM, Vladimir 'φ-coder/phcoder' > Serbinenko > > > <phcoder(a)gmail.com <mailto:phcoder@gmail.com> > <mailto:phcoder@gmail.com <mailto:phcoder@gmail.com>> > > <mailto:phcoder@gmail.com <mailto:phcoder@gmail.com> > <mailto:phcoder@gmail.com <mailto:phcoder@gmail.com>>>> wrote: > > > > > > On 20.03.2014 12:12, Shant Kehyeian wrote: > > > > Hello, > > > > I have Samsung ARM chromebook series 3 "Snow" and I am > > trying to flesh > > > > it and change the boot process. > > > > So I build a coreboot.rom for that, but before I start > to do > > that I > > > > would like to ask about the payload. When I did the "make > > > menuconfig" it > > > > wasn't by default the SeaBios., there wasn't at all > ...there was > > > GRUB 2 > > > > and I selected it...so My question is would it work as > > SeaBios to boot > > > > from usb ? > > > There is no arm-coreboot GRUB2 port currently. > > > > Thank you. > > > > > > > > > > > > > > > > > > > > > > > > > >

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coreboot March 2014