coreboot December 2014

coreboot@coreboot.org

33 participants
53 discussions

New Defects reported by Coverity Scan for coreboot
by scan-admin＠coverity.com 03 Dec '14

03 Dec '14

Hi, Please find the latest report on new defect(s) introduced to coreboot found with Coverity Scan. 3 new defect(s) introduced to coreboot found with Coverity Scan. 7 defect(s), reported by Coverity Scan earlier, were marked fixed in the recent build analyzed by Coverity Scan. New defect(s) Reported-by: Coverity Scan Showing 3 of 3 defect(s) ** CID 1229574: Unchecked return value (CHECKED_RETURN) /src/drivers/spi/spi_flash.c: 73 in spi_flash_read_common() ** CID 1256585: Unchecked return value (CHECKED_RETURN) /src/cpu/amd/agesa/spi.c: 39 in spi_SaveS3info() ** CID 1256584: Unchecked return value (CHECKED_RETURN) /src/ec/google/chromeec/ec_spi.c: 33 in crosec_spi_io() ________________________________________________________________________________________________________ *** CID 1229574: Unchecked return value (CHECKED_RETURN) /src/drivers/spi/spi_flash.c: 73 in spi_flash_read_common() 67 size_t cmd_len, void *data, size_t data_len) 68 { 69 struct spi_slave *spi = flash->spi; 70 int ret; 71 72 spi->rw = SPI_READ_FLAG; >>> CID 1229574: Unchecked return value (CHECKED_RETURN) >>> Calling "spi_claim_bus" without checking return value (as is done elsewhere 12 out of 15 times). 73 spi_claim_bus(spi); 74 ret = spi_flash_cmd_read(spi, cmd, cmd_len, data, data_len); 75 spi_release_bus(spi); 76 77 return ret; 78 } ________________________________________________________________________________________________________ *** CID 1256585: Unchecked return value (CHECKED_RETURN) /src/cpu/amd/agesa/spi.c: 39 in spi_SaveS3info() 33 printk(BIOS_DEBUG, "Could not find SPI device\n"); 34 /* Dont make flow stop. */ 35 return; 36 } 37 38 flash->spi->rw = SPI_WRITE_FLAG; >>> CID 1256585: Unchecked return value (CHECKED_RETURN) >>> Calling "spi_claim_bus" without checking return value (as is done elsewhere 12 out of 15 times). 39 spi_claim_bus(flash->spi); 40 41 flash->erase(flash, pos, size); 42 flash->write(flash, pos, sizeof(len), &len); 43 flash->write(flash, pos + sizeof(len), len, buf); 44 ________________________________________________________________________________________________________ *** CID 1256584: Unchecked return value (CHECKED_RETURN) /src/ec/google/chromeec/ec_spi.c: 33 in crosec_spi_io() 27 uint8_t *read_bytes, size_t read_size, 28 void *context) 29 { 30 struct spi_slave *slave = (struct spi_slave *)context; 31 int rv; 32 >>> CID 1256584: Unchecked return value (CHECKED_RETURN) >>> Calling "spi_claim_bus" without checking return value (as is done elsewhere 12 out of 15 times). 33 spi_claim_bus(slave); 34 rv = spi_xfer(slave, write_bytes, write_size, read_bytes, 35 read_size); 36 spi_release_bus(slave); 37 38 if (rv != 0) { ________________________________________________________________________________________________________ To view the defects in Coverity Scan visit, http://scan.coverity.com/projects/1016?tab=overview To manage Coverity Scan email notifications for "coreboot(a)coreboot.org", click http://scan.coverity.com/subscriptions/edit?email=coreboot%40coreboot.org&t… .

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roda rk9
by The Gluglug 02 Dec '14

02 Dec '14

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Hi, Does anyone here have this board? If so, please contact me off-list (ME related work); I need the 4K descriptor region from a factory.bin dump. Regards, Francis Rowe. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQEcBAEBAgAGBQJUfYZLAAoJEP9Ft0z50c+UchcH/iu6avKAxOtsnKcn8qWd6Kn5 xr8jn+seRLvHgL+4PIQnk74jxYdfy+i+4kWogBmhm2Pu8KI0MoZDl4heb/I+x4Mk pk0Rp87RDTp62YbPIbdKZelMUK+P8vEUtUmENVNN435FOQLGgK3Yp4mTFYARqizp LjA5vxpsXdp/4CqQeC8uJNpjSFiH6Q+tuPFMXYvA0iuI1uRl2iUS+kFJwRue2KeW OFKYHqS9nV0bgQhJdERVUmZS0Hnv5DBjBrTe2VtWBoHm0t7sClV/VMPD236wj2aQ sL+km8QGzfHBOiR4GSgJmuPTHGVDEbTjZJi9rsrwkxPD6rnbq019/qNQf7XE1uk= =FLXI -----END PGP SIGNATURE-----

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Thanks
by ron minnich 02 Dec '14

02 Dec '14

I've had lots of good reviews and help since Prague on the riscv, and we're here: http://pastebin.com/57RLmmCZ. any thoughts on the error welcome, I have to stop now. Ron

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coreboot December 2014