coreboot December 2014

coreboot@coreboot.org

33 participants
53 discussions

coreboot on mobo for i5-4690K
by gordon gordon 29 Dec '14

29 Dec '14

I am looking to build a new machine. I'd like to base it on the Intel i5-4690K CPU as it seems to be the fastest real-world number-crunching chip at a plausible price today. None of the 'K' friendly motherboards seems to be supported by coreboot today. Should I give up on coreboot? (or this chip?) Preferred Mobo: MSI Z97 PC Mate [http://uk.pcpartpicker.com/part/msi-motherboard-z97pcmate] There are tons of alternative motherboards, but I think all of the sensible options are Intel Z97 based. I am a professional programmer, but it has been a decade since I wrote a kernel module. Should I give up on the idea of coreboot (or this chipset?) for my new machine?

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patches for compiling DirectHW on OSX 10.10, XCode 6.1
by Martin Lindhe 28 Dec '14

28 Dec '14

Hello (if replying, please CC me, as i am not subscribed to this list) please find attached the changes i had to make in order to successfully build the DirectHW.dmg (and the pciutils-3.1.7.dmg) based on the code in http://review.coreboot.org/p/directhw.git <http://review.coreboot.org/p/directhw.git> Some notes: project.pbxproj: * updated and architectures removed, now it will build for the architecture matching your system Makefile: * i386 arch removed, only x86_64 is now built * DirectHW-i386-only.diff is no longer applied * SetFile should be available in path, so "/Developer/Tools/SetFile” was replaced by SetFile * PackageMaker seems to be deprecated, but can be found in “Auxility tools Late July 2012” at https://developer.apple.com/downloads/index.action?name=PackageMaker, changed path from /Developer/usr/bin/packagemaker to /Applications/Utilities/PackageMaker.app/Contents/MacOS/PackageMaker create-dmg: * tries to run template.applescript directly using osascript, not sure i got this part working properly. It is not needed to produce the .dmg:s tho, only to succeed automatically install them also, as far as i can tell. /m Martin Lindhe martin(a)ubique.se <mailto:martin@ubique.se> (pgp id 0F5C84F8) +46 70 730 8763

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problem booting AMD RS780 boards
by Scott Duplichan 27 Dec '14

27 Dec '14

I found the AMD mahogany Family 10h coreboot is no longer booting on my ECS-A780GM-M3 board. The first problem it encounters is a hang after warm reset. The hang is due to HT training fail. Using the config option to limit the HT speed works around the problem. Though older coreboot builds do not have this problem with my board and processor, I am not too concerned with it at the moment. The more serious problem is a hang at "PCI: pci_scan_bus for bus 01". This hang is due to commit http://review.coreboot.org/#/c/3606/. If the changed default config access mechanism is reverted back to CF8 I/O, then the board boots normally. I noticed the comment for commit http://review.coreboot.org/#/c/3608/: "On older AMD platform PCI MMIO may not be able to fully configure all PCI devices/nodes, while MMIO_SUPPORT_DEFAULT would be preferred due to its atomic nature. So those can be forced to IO config instead." I tried removing "select MMCONF_SUPPORT_DEFAULT" from src\cpu\amd\model_10xxx\Kconfig. With that change, the board can sometimes boot, but boot progress is slow and often hangs before completing. Any suggestions for a proper fix? I may be able to look at it more later next week. Thanks, Scott

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Re: [coreboot] Interested in Contributing to coreboot
by Paul Menzel 26 Dec '14

26 Dec '14

Dear Prannoy, Am Donnerstag, den 18.12.2014, 19:46 +0530 schrieb Prannoy Pilligundla: > I am Prannoy currently pursuing undergrad in India. I am competent in C, > Java and Python. I have experience of working in Assembly on x86 > processors. I have been using Linux since last two years. I successfully > completed Google Summer of Code 2014 with LyX. nice! Welcome to coreboot¹! > I am interested to start contributing to Core Boot but I am not sure about > where to start and how to start. So it would be great if someone could > brief me about the areas where I can contribute considering the fact that I > am new to Core Boot. Please take a look at the GSoC Wiki page [1]. You could start by getting coreboot to run with QEMU and play around a little. Then you could try make a coreboot port for the hardware you own. Please get back to us if you have any other questions or if the project are not so appealing to you. There is currently some work going on, getting native graphics initialization implemented for certain AMD graphics chipsets. Also implementing a test setup, testing each coreboot commit with QEMU and testing the utilities under `util/` would be interesting projects. Thanks, Paul ¹ Please note, the official spelling is all lowercase. [1] http://www.coreboot.org/GSoC [2] http://blogs.coreboot.org/

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xmas present - a minimal debian jessie with fastboot for X60 coreboot users
by Charles Devereaux 25 Dec '14

25 Dec '14

Hello and merry Christmas, For x60 owners who want to experiment with a very fast boot, I've prepared as a xmas present a minimal debian distribution that implements every idea I posted before, including a brand new systemd to help a bit more with DHCP requests time. It's currently available on: https://www.dropbox.com/s/hyzjfbehqy58y5g/attempt.tgz?dl=0 (If you've a suggestion to host ~200 to 500Mb tarballs, please tell me!) Booting to X is not included in this release since I'm still trying to optimize a few things related to the wacom driver taking way too much time (log attached). It currently takes about 1.2s more, while the target is 0.5s. To install it, simply format a partition in the filesystem of your choice (I suggest XFS), mount it as /attempt, unpack the tarball, edit attempt/etc/fstab to match the device and filesystem. To boot it, add to your grub.cfg (here for /dev/sda3 i.e. ahci0,3): menuentry '1: Debian GNU/Linux coreboot systemd' { set root=(ahci0,3) linux /kernel/bzImage libahci.ignore_sss=1 raid=noautodetect i915.lvds_downclock=1 i915.i915_enable_rc6=7 nohz=on nmi_watchdog=0 thinkpad_acpi.brightness_enable=0 thinkpad_acpi.force_load=1 thinkpad_acpi.fan_control=1 snd-hda-intel.index=0 snd_hda_intel.power_save=10 snd_hda_intel.model=thinkpad snd-hda-intel.probe_mask=0x103 snd-pcsp.index=1 btusb.reset=1 ath9k.ps_enable=1 ath9k.btcoex_enable=1 i915.fastboot=1 pcie=aspm pcie_aspm.policy=powersave tpm_tis.force=1 tpm_tis.interrupts=0 tpm_tis.hid=PNP0C31 quiet root=/dev/sda3 systemd.unit=graphical.target } Step-by-step intructions to replicate that debian jessie + vanilla systemd have been posted on http://en.blog.guylhem.net/post/106153399669/how-to-recreate-the-x60-corebo… Presently, booting to the command-line takes about 1.3s (kernel + system) as tested with systemd-analyze: Startup finished in 763ms (kernel) + 579ms (userspace) = 1.343s In both cases, the net is available very quickly thanks to systemd starting wpa_supplicant as soon as the ath9k is initialized, but this is still a limiting factor as you need to wait an additional 1.3s to have a usable connection. I'm still working on that. It may need native wpa support within systemd to be really improved, which may happen someday. >From the dmesg: [ 1.496135] IPv6: ADDRCONF(NETDEV_UP): wlan0: link is not ready [ 2.652574] wlan0: authenticate with 00:11:22:33:44:55 [ 2.667119] wlan0: send auth to 00:11:22:33:44:55 (try 1/3) [ 2.669174] wlan0: authenticated [ 2.669280] ath9k 0000:02:00.0 wlan0: disabling HT as WMM/QoS is not supported by the AP [ 2.669285] ath9k 0000:02:00.0 wlan0: disabling VHT as WMM/QoS is not supported by the AP [ 2.670064] wlan0: associate with 00:11:22:33:44:55 (try 1/3) [ 2.672618] wlan0: RX AssocResp from 00:11:22:33:44:55 (capab=0x411 status=0 aid=5) [ 2.672680] wlan0: associated [ 2.672704] IPv6: ADDRCONF(NETDEV_CHANGE): wlan0: link becomes ready Still, anyone can now have a debian jessie booting decently fast on a x60. When the X fixups are done, I'll try to make a youtube video demonstrating how fast boot can be. I'm now wondering about how to make coreboot boot faster. Suggestions are welcome. Enjoy! Charles

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Getting more useful patterns out of replay logs
by mrnuke 18 Dec '14

18 Dec '14

I want to convert a replay log to something that looks more structured, and easier to parse through mentally. I've tried to use coccinelle, but I came across a couple of problems. First, the file is over 13000 (thirteen thousand) lines long, and coccinelle crashes with a "stack overflow" error even on the simplest patterns. Second, I couldn't figure out how to use coccinelle to extract the bits I want from those 32-bit constants. This is an example pattern. I've described the relevant information I want to extract in '//' style comments: read(0x6530); /* 0f410000 */ write(0x6530, 0x0f410000); read(0x6530); /* 0f410000 */ write(0x6530, 0x0f410000); read(0x6200); /* 21000101 */ write(0x6200, 0x21000101); // <- [30:28] hpd_id (2) read(0x6200); /* 21000101 */ write(0x6200, 0x21000101); read(0x9fffbe00); /* 50400050 */ read(0x6204); /* 00030000 */ write(0x6204, 0x00050000); // <- [20:16] tx_bytes (5) read(0x6204); /* 00050000 */ write(0x6204, 0x00050000); read(0x9fffbe00); /* 50400050 */ write(0x6218, 0x80004000); // <- [15:8] cmd_byte read(0x9fffbe00); /* 50400050 */ write(0x6218, 0x00000000); // <- [15:8] address[15:8] read(0x9fffbe00); /* 50400050 */ write(0x6218, 0x00005000); // <- [15:8] address[7:0] (0x50) read(0x9fffbe00); /* 50400050 */ write(0x6218, 0x00000000); // <- [15:8] expected_rx_bytes - 1 read(0x9fffbe04); /* 00000050 */ write(0x6218, 0x00003000); // <- [15:8] i2c_reg (0x30) read(0x9fffbe04); /* 00000050 */ write(0x6218, 0x00000000); read(0x9fffbe04); /* 00000050 */ write(0x6218, 0x00000000); read(0x9fffbe04); /* 00000050 */ write(0x6218, 0x00000000); read(0x620c); /* 00000000 */ write(0x620c, 0x00000002); read(0x6204); /* 00050000 */ write(0x6204, 0x00050001); read(0x6210); /* c1000000 */ delay(0x0088c9bd - 0x0088c79b); read(0x6210); /* c1000000 */ delay(0x0088f0b7 - 0x0088ee9b); read(0x6210); /* 01000001 */ read(0x6210); /* 01000001 */ write(0x6218, 0x80000001); read(0x6218); /* 00000001 */ // <- [15:8] reply (0) read(0x6210); /* 01000001 */ // <- [28:24] actual_rx_bytes (1) read(0x9fffa414); /* 22232121 */ read(0x9fffa418); /* 00000000 */ read(0x9fffa52c); /* 80010000 */ read(0x9fffa530); /* 00000108 */ write(0x9fffbe04, 0x08800100); write(0x9fffbe00, 0x4f500050); Now assuming I have a struct called jelly_donut instantiated as 'donut', I'd like the output to look like: donut->hpd_id = 2; donut->tx_bytes = 5; donut->cmd_byte = 0x40; donut->address = 0x0050; donut->i2c_reg = 0x30; process_food(donut); /* .reply = 0; actual_rx_bytes = 1 */ or, I'll even settle for something like: regurgitate(2, 5, 0x40, 0x0050, 0x30); /* .reply = 0; actual_rx_bytes = 1 */ Any ideas how I'd get this done? Alex

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[RFC] coreboot for businesses
by Stefan Reinauer 18 Dec '14

18 Dec '14

Dear coreboot community members: Marc, Ron, Patrick, Aaron and I have been discussing for a while about how to make coreboot more accessible for businesses. We would like to found a business organization (a.k.a. a coreboot consortium) that helps commercial players out there to become a part of the coreboot community, share marketing materials, and other efforts to promote the use of coreboot in the market place and be successful with coreboot based solutions. If you work for an organization that is using coreboot, developing coreboot, or is just interested in coreboot, please help us learn about your needs and wishes and fill out the following form: http://goo.gl/glhNh5 If you know someone who might be interested, but is not on this mailing list, please forward this message to them. Best regards, Stefan

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Interested in Contributing to Core Boot
by Prannoy Pilligundla 18 Dec '14

18 Dec '14

Hi Everyone, I am Prannoy currently pursuing undergrad in India. I am competent in C, Java and Python. I have experience of working in Assembly on x86 processors. I have been using Linux since last two years. I successfully completed Google Summer of Code 2014 with LyX. I am interested to start contributing to Core Boot but I am not sure about where to start and how to start. So it would be great if someone could brief me about the areas where I can contribute considering the fact that I am new to Core Boot. Thanks and Regards Prannoy Pilligundla ᐧ

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Re: [coreboot] PCIe PME vs ACPI Interrupt
by Martin Roth 17 Dec '14

17 Dec '14

Hi Gailu, Sorry, wake on lan wasn't tested during the Bayley Bay development, so something was probably missed. I'm doing some baytrail work right now, so I might get around to looking at it and pushing a change, but I can't make any guarantees about when or if that might happen. Regards, Martin On 12/08/2014 01:49 PM, Gailu Singh wrote: > Hi Experts, > > I am working on S3 wakeup from PCIE WAKE Signal on Baytrail SOC > (Bayleybay board) with Intel FSP. > When I send WOL packet ACPI interrupt count does not increase though > PCIe PME interrupt count increases. > > Can you please provide some pointers why I am not getting ACPI > interrupt for the wake event? > > in /proc/interrupts, PCIe PME counter increments and acpi counter > remains 0. > Â 9:Â Â Â Â Â Â Â Â Â 0Â Â Â Â Â Â Â Â Â 0Â Â IO-APIC-fasteoiÂ Â acpi > 103:Â Â Â Â Â Â Â Â 2Â Â Â Â Â Â Â Â Â 0Â Â PCI-MSI-edgeÂ Â Â Â Â > PCIe PME > > > My Root Port ASL is below. > > Â Â Â Device (RP01) > Â Â Â { > Â Â Â Â Â Â Â Name (_ADR, 0x001c0000) > Â Â Â Â Â Â Â Name (_PRW, Package (0x02) > Â Â Â Â Â Â Â { > Â Â Â Â Â Â Â Â Â Â Â 0x09, > Â Â Â Â Â Â Â Â Â Â Â 0x03 > Â Â Â Â Â Â Â }) > Â Â Â Â Â Â Â Device (PXSX) > Â Â Â Â Â Â Â { > Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Name (_ADR, Zero) > Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Name (_PRW, Package (0x02) > Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â { > Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â 0x09, > Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â 0x03 > Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â }) > Â Â Â Â Â Â Â } > Â Â Â Â Â Â Â Method (_PRT) > Â Â Â Â Â Â Â { > Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â If (PICM) { > Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Return (Package() { > Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â #undef > PIC_MODE > Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â #include > "irq_helper.h" > Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â > PCI_DEV_PIRQ_ROUTE(0x0, A, B, C, D) > Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â }) > Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â } Else { > Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Return (Package() { > Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â #define > PIC_MODE > Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â #include > "irq_helper.h" > Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â > PCI_DEV_PIRQ_ROUTE(0x0, A, B, C, D) > Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â }) > Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â } > Â Â Â Â Â Â Â } > Â Â Â } > > >

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Updated coreboot build environment for Windows
by Scott Duplichan 16 Dec '14

16 Dec '14

I have maintained a coreboot build environment for Windows for a while: http://notabs.org/coreboot/windows-build.htm Though maintaining it has never been a priority for me, the website log files show quite a few people download it. For this reason I am trying to improve this project. The recently submitted patches get the Windows hosted coreboot build environment working well enough for abuild to pass for all builds using gcc: x86, ARM, and AARCH64. There is no clang or riscv support. There is one patch I haven't been able to submit. For Windows hosted building, file util/nvidia/cbootimage/src/set.c needs to fopen binary files using "rb" instead of "r". This file is part of a git 'submodule'. How do build and upload a patch for this file? Thanks, Scott

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coreboot December 2014