coreboot January 2014

coreboot@coreboot.org

54 participants
116 discussions

Re: [coreboot] Are any Chromebooks able to run fully libre?
by Patrick Georgi 02 Jan '14

02 Jan '14

Am 02.01.2014 19:15, schrieb Sam Kuper: > As I understand it, there are two distinct reasons why some BLOBs, in > certain systems, cannot be eliminated/replaced by executing > appropriate software on those systems: [...] Option 3: The image is signed with some vendor key. You could replace it, but the hardware prevents running any unsigned alternative. Regards, Patrick

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Re: [coreboot] Are any Chromebooks able to run fully libre?
by Sam Kuper 02 Jan '14

02 Jan '14

On 20/12/2013, ron minnich <rminnich(a)gmail.com> wrote: > I can go > into more detail if you want to know the particulars, but there's so > many places in our systems containing blobs As I understand it, there are two distinct reasons why some BLOBs, in certain systems, cannot be eliminated/replaced by executing appropriate software on those systems: 1. Because the BLOB is stored in a genuine ROM (or equivalent or EPROM or equivalent; but not an EEPROM or equivalent) and therefore cannot physically be eliminated/replaced just by (setting a jumper if necessary, and) executing software; 2. Because although the BLOB could in principle be eliminated/replaced, no libre (or even open-source) alternative for it exists yet that would lead to error-free operation of the hardware. (Intel CPU microcode updates are a prime example of such BLOBs.) Assuming I haven't got the wrong end of this stick, I would be grateful if you (or anyone else reading this) could go into more detail (or point me to a resource that does) regarding which BLOBs exist on the following two models of Chromebook, and which of those two cases they fall under: - Acer C7/C710 - HP Pavilion 14 For instance, I've not yet figured out whether those Chromebook models currently upload microcode to the Celeron 847 (or Celeron 1007U). (Unless my search-fu has failed me, Intel doesn't seem to have released any microcode updates for the 847 or 1007U; but perhaps that is irrelevant, because BIOS/OS-uploadable microcode for the 847 might have been released without any further microcode *updates* being released?) Thanks again, Sam

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Super I/O: Nuvoton NCT6779D support (Incomplete and stuck)
by Alec Ari 02 Jan '14

02 Jan '14

Hello everyone! Please note I am not subscribed to the coreboot mailing list so if you want to contact me, please do so directly or CC my email address. I wrote an incomplete port to the Nuvoton NCT6779D Super I/O chip ( http://review.coreboot.org/4589 ) I am not sure if publicly sharing the datasheet is OK or not (if it is alright, let me know so I can post it as I am not under an NDA with Nuvoton by any means) but anyone with Super I/O and general hardware / electrical engineering should be able to easily finish up the port as most of the work is already done and just needs some tidying up (comments in patch indicate possible issues and things I am stuck on.) The Super I/O is currently used with several ASUS boards such as some of their Intel Z77 chipset motherboards (Sabertooth and Maximus V series) F2A85V-PRO (AMD FM2 A-series CPUs) and possibly a few others. A few other coreboot developers are working on some boards right now that use it, so hopefully my patch will assist their efforts. Thank you, happy coding, and New Years. Alec Ari

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Asus M2V-MX SE: Resume from S3 broken: `CBFS: ERROR: No file header found at 0x0 - try next aligned address: 0x40.`
by Paul Menzel 02 Jan '14

02 Jan '14

Dear coreboot folks, using coreboot with the attached configuration (with CBMEM) on the Asus M2V-MX SE [1], resume from S3 does not work for me. $ more serial.log […] [ 818.013737] PM: Syncing filesystems ... done. [ 818.021643] (NULL device *): firmware: agent loaded rt2870.bin into memory [ 818.028721] Freezing user space processes ... (elapsed 0.01 seconds) done. [ 818.050706] Freezing remaining freezable tasks ... (elapsed 0.01 seconds) done. [ 818.070691] Suspending console(s) (use no_console_suspend to debug) coreboot-4.0-5045-g0fd505b Tue Dec 17 00:36:07 CET 2013 starting... now booting... Enabling routing table for node 00 done. Enabling UP settings Disabling read/write/fill probes for UP... done. coherent_ht_finalize done core0 started: now booting... All core 0 started started ap apicid: SBLink=00 NC node|link=00 00entering optimize_link_incoherent_ht sysinfo->link_pair_num=0x1 entering ht_optimize_link pos=0x8a, unfiltered freq_cap=0x8035 pos=0x8a, filtered freq_cap=0x35 Limiting HT to 800/600/400/200 MHz until K8M890 HT1000 is fixed. pos=0x6e, unfiltered freq_cap=0x75 pos=0x6e, filtered freq_cap=0x75 Limiting HT to 800/600/400/200 MHz until K8M890 HT1000 is fixed. freq_cap1=0x35, freq_cap2=0x35 dev1 old_freq=0x0, freq=0x5, needs_reset=0x1 dev2 old_freq=0x0, freq=0x5, needs_reset=0x1 width_cap1=0x11, width_cap2=0x11 dev1 input ln_width1=0x4, ln_width2=0x4 dev1 input width=0x1 dev1 output ln_width1=0x4, ln_width2=0x4 dev1 input|output width=0x11 old dev1 input|output width=0x11 dev2 input|output width=0x11 old dev2 input|output width=0x11 after ht_optimize_link for link pair 0, reset_needed=0x1 after optimize_link_read_pointers_chain, reset_needed=0x1 01K8M890 found at LDT 00 Agreed on width: 01 CPU programmed to HT freq: 05 VIA HT caps: 0075 01ht reset - soft reset coreboot-4.0-5045-g0fd505b Tue Dec 17 00:36:07 CET 2013 starting... now booting... Enabling routing table for node 00 done. Enabling UP settings Disabling read/write/fill probes for UP... done. coherent_ht_finalize done core0 started: now booting... All core 0 started started ap apicid: SBLink=00 NC node|link=00 00entering optimize_link_incoherent_ht sysinfo->link_pair_num=0x1 entering ht_optimize_link pos=0x8a, unfiltered freq_cap=0x8035 pos=0x8a, filtered freq_cap=0x35 Limiting HT to 800/600/400/200 MHz until K8M890 HT1000 is fixed. pos=0x6e, unfiltered freq_cap=0x75 pos=0x6e, filtered freq_cap=0x75 Limiting HT to 800/600/400/200 MHz until K8M890 HT1000 is fixed. freq_cap1=0x35, freq_cap2=0x35 dev1 old_freq=0x5, freq=0x5, needs_reset=0x0 dev2 old_freq=0x5, freq=0x5, needs_reset=0x0 width_cap1=0x11, width_cap2=0x11 dev1 input ln_width1=0x4, ln_width2=0x4 dev1 input width=0x1 dev1 output ln_width1=0x4, ln_width2=0x4 dev1 input|output width=0x11 old dev1 input|output width=0x11 dev2 input|output width=0x11 old dev2 input|output width=0x11 after ht_optimize_link for link pair 0, reset_needed=0x0 after optimize_link_read_pointers_chain, reset_needed=0x0 00K8M890 found at LDT 00 Agreed on width: 01 CPU programmed to HT freq: 05 VIA HT caps: 0075 00after enable_fid_change toggle LDTSTP# done Current fid_cur: 0x2, fid_max: 0xa Requested fid_new: 0xa FidVid table step fidvid: 0xa toggle LDTSTP# done toggle LDTSTP# done Ram1.00 setting up CPU 00 northbridge registers done. Ram2.00 sdram_set_spd_registers: paramx :000cfee0 Device error Device error Enabling dual channel memory Unbuffered 400MHz 400MHz set_ecc: ECC disabled Interleaved RAM end at 0x00200000 kB Ram3 IN TEST WAKEUP 400Wakeup! before resume errata #125 before exit errata - timer enabled before exit errata - after mdelay pcidev is 8000c290 after exit errata Exiting memory from self refresh: done DQS RESTORE FROM NVRAM: c2000 Loading 113222 of size 4 to nvram pos:0 Loading 18181718 of size 4 to nvram pos:4 Loading 17171617 of size 4 to nvram pos:8 Loading 16 of size 1 to nvram pos:12 Loading 202520 of size 4 to nvram pos:13 Loading 14141413 of size 4 to nvram pos:17 Loading 16141415 of size 4 to nvram pos:21 Loading 14 of size 1 to nvram pos:25 Loading 29 of size 1 to nvram pos:26 Loading 0 of size 1 to nvram pos:27 Loading 0 of size 1 to nvram pos:28 Loading 0 of size 1 to nvram pos:29 Loading 113222 of size 4 to nvram pos:30 Loading 18171717 of size 4 to nvram pos:34 Loading 16161717 of size 4 to nvram pos:38 Loading 17 of size 1 to nvram pos:42 Loading 202520 of size 4 to nvram pos:43 Loading 14151514 of size 4 to nvram pos:47 Loading 15151414 of size 4 to nvram pos:51 Loading 14 of size 1 to nvram pos:55 Loading 2c of size 1 to nvram pos:56 Loading 0 of size 1 to nvram pos:57 Loading 0 of size 1 to nvram pos:58 Loading 0 of size 1 to nvram pos:59 Loading 7410809b of size 4 to nvram pos:60 Mem running ! Ram4 v_esp=000cff28 IN TEST WAKEUP 400IN TEST WAKEUP 400CBMEM region 7dec0000-7dffffff (cbmem_reinit) IN TEST WAKEUP 400Will copy coreboot region to: 7dedc200 Copying data from cache to RAM -- switching to use RAM as stack... Done Disabling cache as ram now Clearing initial memory region: Loading image. CBFS: ERROR: No file header found at 0x0 - try next aligned address: 0x40. It then just hangs there. $ sudo ./cbmem -l CBMEM table of contents: ID START LENGTH 0. FREE SPACE 7dfe4200 0001be00 1. GDT 7dec0200 00000200 2. CONSOLE 7dec0400 00010000 3. TIME STAMP 7ded0400 00000200 4. ACPI 7ded0600 0000b400 5. SMBIOS 7dedba00 00000800 6. ACPI RESUME 7dedc200 00100000 7. COREBOOT 7dfdc200 00008000 $ sudo cbmem -t # truncated with the error message 10 entries total: 10:start of ramstage Could not open /sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_max_freq: No such file or directory Thanks, Paul [1] http://www.coreboot.org/ASUS_M2V-MX_SE

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Re: [coreboot] BadBIOS Thoughts
by Alex G. 01 Jan '14

01 Jan '14

On 11/20/2013 09:23 AM, ron minnich wrote: > I've got a student coming in January and he's going to work on > ChromeOS on AMD CPUs, starting with the Gizmo. If, at that time, > someone has a suggestion for an AMD laptop which might be suitable, > let me know. Would you care to elaborate on that? As much as I hate HP, they do seem to have some of the best AMD-based laptops. I would look at the ProBook 655 G1 / 645 G1 or the HP ProBook 6475b. Alex P.S. One fornicating annoying downside is that HP's firmware really sucks. Suspend-and-not-crash-and-overheat (TM) is sometimes working, while Resume-and-not-defecate (TM) seems to be slightly more reliable.

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Re: [coreboot] Coreboot and the NSA's expressed preference for subverting BIOSes
by mrnuke 01 Jan '14

01 Jan '14

On Tuesday, December 31, 2013 11:54:21 PM Sam Kuper wrote: > Which other Coreboot-supported systems/motherboards have hardware > write-protection (or can be easily modified to at least write-protect > the BIOS)? > Most SPI flash chips have a write-protect pin. It depends on the model how much that actually protects, but externally shorting that to GND might do the trick. Alex

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coreboot January 2014